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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p09n03i00343ent IS
END c03s02b01x00p09n03i00343ent;
ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS
type M1 is array (1 to 4) of BIT;
signal X1 : M1;
BEGIN
TESTING: PROCESS
BEGIN
X1(1) <= '0' after 10 ns;
X1(2) <= '1' after 20 ns;
X1(3) <= '1' after 30 ns;
X1(4) <= '0' after 40 ns; -- No_failure_here
wait for 50 ns;
assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***PASSED TEST: c03s02b01x00p09n03i00343"
severity NOTE;
assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p09n03i00343arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p09n03i00343ent IS
END c03s02b01x00p09n03i00343ent;
ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS
type M1 is array (1 to 4) of BIT;
signal X1 : M1;
BEGIN
TESTING: PROCESS
BEGIN
X1(1) <= '0' after 10 ns;
X1(2) <= '1' after 20 ns;
X1(3) <= '1' after 30 ns;
X1(4) <= '0' after 40 ns; -- No_failure_here
wait for 50 ns;
assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***PASSED TEST: c03s02b01x00p09n03i00343"
severity NOTE;
assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p09n03i00343arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Cobham Gaisler AB
-- Description: Vendor and devices IDs for AMBA plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_RESERVED : amba_vendor_type := 16#00#; -- Do not use!
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_DLR : amba_vendor_type := 16#0A#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#;
constant VENDOR_DTU : amba_vendor_type := 16#0D#;
constant VENDOR_BSC : amba_vendor_type := 16#0E#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_NASA : amba_vendor_type := 16#22#;
constant VENDOR_S3 : amba_vendor_type := 16#31#;
constant VENDOR_ACTEL : amba_vendor_type := 16#AC#;
constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#;
constant VENDOR_C3E : amba_vendor_type := 16#C3#;
constant VENDOR_CBKPAN : amba_vendor_type := 16#C8#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
-- Cobham Gaisler device ids
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_I2C2AHB : amba_device_type := 16#00B#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_AHBDPRAM : amba_device_type := 16#00F#;
constant GAISLER_GRIOMMU2 : amba_device_type := 16#010#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBDC : amba_device_type := 16#021#;
constant GAISLER_USB_DCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_L4STAT : amba_device_type := 16#047#;
constant GAISLER_LEON4 : amba_device_type := 16#048#;
constant GAISLER_LEON4DSU : amba_device_type := 16#049#;
constant GAISLER_PWM : amba_device_type := 16#04A#;
constant GAISLER_L2CACHE : amba_device_type := 16#04B#;
constant GAISLER_SDCTRL64 : amba_device_type := 16#04C#;
constant GAISLER_GR1553B : amba_device_type := 16#04D#;
constant GAISLER_1553TST : amba_device_type := 16#04E#;
constant GAISLER_GRIOMMU : amba_device_type := 16#04F#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_MEMSCRUB : amba_device_type := 16#057#;
constant GAISLER_FTSDCTRL64: amba_device_type := 16#058#;
constant GAISLER_NANDFCTRL : amba_device_type := 16#059#;
constant GAISLER_N2DLLCTRL : amba_device_type := 16#05A#;
constant GAISLER_N2PLLCTRL : amba_device_type := 16#05B#;
constant GAISLER_SPI2AHB : amba_device_type := 16#05C#;
constant GAISLER_DDRSDMUX : amba_device_type := 16#05D#;
constant GAISLER_AHBFROM : amba_device_type := 16#05E#;
constant GAISLER_PCIEXP : amba_device_type := 16#05F#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_MP7WRAP : amba_device_type := 16#065#;
constant GAISLER_GRSYSMON : amba_device_type := 16#066#;
constant GAISLER_GRACECTRL : amba_device_type := 16#067#;
constant GAISLER_ATAHBSLV : amba_device_type := 16#068#;
constant GAISLER_ATAHBMST : amba_device_type := 16#069#;
constant GAISLER_ATAPBSLV : amba_device_type := 16#06A#;
constant GAISLER_MIGDDR2 : amba_device_type := 16#06B#;
constant GAISLER_LCDCTRL : amba_device_type := 16#06C#;
constant GAISLER_SWITCHOVER: amba_device_type := 16#06D#;
constant GAISLER_FIFOUART : amba_device_type := 16#06E#;
constant GAISLER_MUXCTRL : amba_device_type := 16#06F#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
constant GAISLER_AESDMA : amba_device_type := 16#07B#;
constant GAISLER_GRPCI2 : amba_device_type := 16#07C#;
constant GAISLER_GRPCI2_DMA: amba_device_type := 16#07D#;
constant GAISLER_GRPCI2_TB : amba_device_type := 16#07E#;
constant GAISLER_MMA : amba_device_type := 16#07F#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_GRTMDESC : amba_device_type := 16#084#;
constant GAISLER_GRTMVC : amba_device_type := 16#085#;
constant GAISLER_GEFFE : amba_device_type := 16#086#;
constant GAISLER_GPREG : amba_device_type := 16#087#;
constant GAISLER_GRTMPAHB : amba_device_type := 16#088#;
constant GAISLER_SPWCUC : amba_device_type := 16#089#;
constant GAISLER_SPW2_DMA : amba_device_type := 16#08A#;
constant GAISLER_SPWROUTER : amba_device_type := 16#08B#;
constant GAISLER_EDCLMST : amba_device_type := 16#08C#;
constant GAISLER_GRPWTX : amba_device_type := 16#08D#;
constant GAISLER_GRPWRX : amba_device_type := 16#08E#;
constant GAISLER_GPREGBANK : amba_device_type := 16#08F#;
constant GAISLER_MIG_7SERIES : amba_device_type := 16#090#;
constant GAISLER_GRSPW2_SIST : amba_device_type := 16#091#;
constant GAISLER_SGMII : amba_device_type := 16#092#;
constant GAISLER_RGMII : amba_device_type := 16#093#;
constant GAISLER_IRQGEN : amba_device_type := 16#094#;
constant GAISLER_GRDMAC : amba_device_type := 16#095#;
constant GAISLER_AHB2AVLA : amba_device_type := 16#096#;
constant GAISLER_SPWTDP : amba_device_type := 16#097#;
constant GAISLER_L3STAT : amba_device_type := 16#098#;
constant GAISLER_GR740THS : amba_device_type := 16#099#;
constant GAISLER_GRRM : amba_device_type := 16#09A#;
constant GAISLER_CMAP : amba_device_type := 16#09B#;
constant GAISLER_CPGEN : amba_device_type := 16#09C#;
constant GAISLER_AMBAPROT : amba_device_type := 16#09D#;
constant GAISLER_IGLOO2_BRIDGE : amba_device_type := 16#09E#;
constant GAISLER_AHB2AXI : amba_device_type := 16#09F#;
constant GAISLER_AXI2AHB : amba_device_type := 16#0A0#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- CBK PAN
constant CBKPAN_FTNANDCTRL : amba_device_type := 16#001#;
constant CBKPAN_FTEEPROMCTRL : amba_device_type := 16#002#;
constant CBKPAN_FTSDCTRL16 : amba_device_type := 16#003#;
constant CBKPAN_STIXCTRL : amba_device_type := 16#300#;
-- European Space Agency device ids
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip IDs
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device ids
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
constant GLEICHMANN_AC97 : amba_device_type := 16#009#;
-- MENTA device ids
constant MENTA_EFPGA_IP : amba_device_type := 16#002#;
-- DTU device ids
constant DTU_IV : amba_device_type := 16#001#;
constant DTU_RBMMTRANS : amba_device_type := 16#002#;
constant DTU_FTMCTRL : amba_device_type := 16#054#;
-- BSC device ids
constant BSC_CORE1 : amba_device_type := 16#001#;
constant BSC_CORE2 : amba_device_type := 16#002#;
-- Orbita device ids
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Actel device ids
constant ACTEL_COREMP7 : amba_device_type := 16#001#;
-- NASA device ids
constant NASA_EP32 : amba_device_type := 16#001#;
-- AppleCore device ids
constant APPLECORE_UTLEON3 : amba_device_type := 16#001#;
constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#;
constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#;
-- Contribution library IDs
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device ids
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_ACT_FUSION : system_device_type := 16#0105#;
constant LEON3_RTAX_CID1 : system_device_type := 16#0201#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID3 : system_device_type := 16#0203#;
constant LEON3_RTAX_CID4 : system_device_type := 16#0204#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_RTAX_CID6 : system_device_type := 16#0206#;
constant LEON3_RTAX_CID7 : system_device_type := 16#0207#;
constant LEON3_RTAX_CID8 : system_device_type := 16#0208#;
constant LEON3_PROXIMA : system_device_type := 16#0252#;
constant ALTERA_DE2 : system_device_type := 16#0302#;
constant ALTERA_DE4 : system_device_type := 16#0303#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant LEON3FT_GRXC4V : system_device_type := 16#0453#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant XILINX_ML506 : system_device_type := 16#0506#;
constant XILINX_ML507 : system_device_type := 16#0507#;
constant XILINX_ML509 : system_device_type := 16#0509#;
constant XILINX_ML510 : system_device_type := 16#0510#;
constant MICROSEMI_M2GL_EVAL : system_device_type := 16#0560#;
constant XILINX_SP601 : system_device_type := 16#0601#;
constant XILINX_ML605 : system_device_type := 16#0605#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Cobham Gaisler ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "LEON2 Debug Support Unit ",
GAISLER_LEON3 => "LEON3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "LEON3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Single-port AHB SRAM module ",
GAISLER_AHBDPRAM => "Dual-port AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "PCI/AHB DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_AHBDMA => "Simple AHB DMA controller ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "LEON3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_FTSDCTRL64=> "64-bit FT SDRAM Controller ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_GRTMDESC => "CCSDS Telemetry Descriptor ",
GAISLER_GRTMVC => "CCSDS Telemetry VC Generator ",
GAISLER_GRTMPAHB => "CCSDS Telemetry VC AHB Input ",
GAISLER_GEFFE => "Geffe Generator ",
GAISLER_SPWCUC => "CCSDS CUC / SpaceWire I/F ",
GAISLER_GPREG => "General Purpose Register ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_AESDMA => "AES 256 DMA ",
GAISLER_GRPCI2 => "GRPCI2 PCI/AHB bridge ",
GAISLER_GRPCI2_DMA=> "GRPCI2 DMA interface ",
GAISLER_GRPCI2_TB => "GRPCI2 Trace buffer ",
GAISLER_MMA => "Memory Mapped AMBA ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBDC => "GR USB 2.0 Device Controller ",
GAISLER_USB_DCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
GAISLER_L4STAT => "LEON4 Statistics Unit ",
GAISLER_LEON4 => "LEON4 SPARC V8 Processor ",
GAISLER_LEON4DSU => "LEON4 Debug Support Unit ",
GAISLER_PWM => "PWM generator ",
GAISLER_L2CACHE => "L2-Cache Controller ",
GAISLER_SDCTRL64 => "64-bit PC133 SDRAM Controller ",
GAISLER_MP7WRAP => "CoreMP7 wrapper ",
GAISLER_GRSYSMON => "AMBA wrapper for System Monitor",
GAISLER_GRACECTRL => "System ACE I/F Controller ",
GAISLER_ATAHBSLV => "AMBA Test Framework AHB Slave ",
GAISLER_ATAHBMST => "AMBA Test Framework AHB Master ",
GAISLER_ATAPBSLV => "AMBA Test Framework APB Slave ",
GAISLER_MIGDDR2 => "Xilinx MIG DDR2 Controller ",
GAISLER_LCDCTRL => "LCD Controller ",
GAISLER_SWITCHOVER=> "Switchover Logic ",
GAISLER_FIFOUART => "UART with large FIFO ",
GAISLER_MUXCTRL => "Analogue multiplexer control ",
GAISLER_GR1553B => "MIL-STD-1553B Interface ",
GAISLER_1553TST => "MIL-STD-1553B Test Device ",
GAISLER_MEMSCRUB => "AHB Memory Scrubber ",
GAISLER_GRIOMMU => "IO Memory Management Unit ",
GAISLER_SPW2_DMA => "GRSPW Router DMA interface ",
GAISLER_SPWROUTER => "GRSPW Router ",
GAISLER_EDCLMST => "EDCL master interface ",
GAISLER_GRPWTX => "PacketWire Transmitter with DMA",
GAISLER_GRPWRX => "PacketWire Receiver with DMA ",
GAISLER_GRIOMMU2 => "IOMMU secondary master i/f ",
GAISLER_I2C2AHB => "I2C to AHB Bridge ",
GAISLER_NANDFCTRL => "NAND Flash Controller ",
GAISLER_N2PLLCTRL => "N2X PLL Dynamic Config. i/f ",
GAISLER_N2DLLCTRL => "N2X DLL Dynamic Config. i/f ",
GAISLER_GPREGBANK => "General Purpose Register Bank ",
GAISLER_SPI2AHB => "SPI to AHB Bridge ",
GAISLER_DDRSDMUX => "Muxed FT DDR/SDRAM controller ",
GAISLER_AHBFROM => "Flash ROM Memory ",
GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ",
GAISLER_MIG_7SERIES => "Xilinx MIG DDR3 Controller ",
GAISLER_GRSPW2_SIST => "GRSPW Router SIST ",
GAISLER_SGMII => "XILINX SGMII Interface ",
GAISLER_RGMII => "Gaisler RGMII Interface ",
GAISLER_IRQGEN => "Interrupt generator ",
GAISLER_GRDMAC => "DMA Controller with APB bridge ",
GAISLER_AHB2AVLA => "Avalon-MM memory controller ",
GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ",
GAISLER_L3STAT => "LEON3 Statistics Unit ",
GAISLER_GR740THS => "Temperature sensor ",
GAISLER_GRRM => "Reconfiguration Module ",
GAISLER_CMAP => "CCSDS Memory Access Protocol ",
GAISLER_CPGEN => "Discrete Command Pulse Gen ",
GAISLER_AMBAPROT => "AMBA Protection Unit ",
GAISLER_IGLOO2_BRIDGE => "Microsemi IGLOO2 HPMS Wrapper ",
GAISLER_AHB2AXI => "AMBA AHB/AXI Bridge ",
GAISLER_AXI2AHB => "AMBA AXI/AHB Bridge ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "LEON2 SPARC V8 Processor ",
ESA_LEON2APB => "LEON2 Peripheral Bus ",
ESA_IRQ => "LEON2 Interrupt Controller ",
ESA_TIMER => "LEON2 Timer ",
ESA_UART => "LEON2 UART ",
ESA_CFG => "LEON2 Configuration Register ",
ESA_IO => "LEON2 Input/Output ",
ESA_MCTRL => "LEON2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "LEON2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "LEON2 Secondary Irq Controller ",
ESA_AHBSTAT => "LEON2 AHB Status Register ",
ESA_WPROT => "LEON2 Write Protection ",
ESA_WPROT2 => "LEON2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
GLEICHMANN_AC97 => "AC97 Controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
MENTA_EFPGA_IP => "eFPGA Core IP ",
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CBKPAN_DESC : vendor_description := "CBK PAN ";
constant cbkpan_device_table : device_table_type := (
CBKPAN_FTNANDCTRL => "NAND FLASH controller w/DMA ",
CBKPAN_FTEEPROMCTRL => "Fault Toler. EEPROM Controller ",
CBKPAN_FTSDCTRL16 => "Fault Toler. 16-bit SDRAM Ctrl.",
CBKPAN_STIXCTRL => "SolO/STIX IDPU dedicated ctrl. ",
others => "Unknown Device ");
constant cbkpan_lib : vendor_library_type := (
vendorid => VENDOR_CBKPAN,
vendordesc => CBKPAN_DESC,
device_table => cbkpan_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant dlr_device_table : device_table_type := (
others => "Unknown Device ");
constant DLR_DESC : vendor_description := "German Aerospace Center ";
constant dlr_lib : vendor_library_type := (
vendorid => VENDOR_DLR,
vendordesc => DLR_DESC,
device_table => dlr_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant telecompt_device_table : device_table_type := (
others => "Unknown Device ");
constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech ";
constant telecompt_lib : vendor_library_type := (
vendorid => VENDOR_TELECOMPT,
vendordesc => TELECOMPT_DESC,
device_table => telecompt_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant bsc_device_table : device_table_type := (
BSC_CORE1 => "Core 1 ",
BSC_CORE2 => "Core 2 ",
others => "Unknown Device ");
constant BSC_DESC : vendor_description := "BSC ";
constant bsc_lib : vendor_library_type := (
vendorid => VENDOR_BSC,
vendordesc => BSC_DESC,
device_table => bsc_device_table
);
constant dtu_device_table : device_table_type := (
DTU_IV => "Instrument Virtualizer ",
DTU_RBMMTRANS => "RB/MM Transfer ",
DTU_FTMCTRL => "Memory controller with 8CS ",
others => "Unknown Device ");
constant DTU_DESC : vendor_description := "DTU Space ";
constant dtu_lib : vendor_library_type := (
vendorid => VENDOR_DTU,
vendordesc => DTU_DESC,
device_table => dtu_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant ACTEL_DESC : vendor_description := "Actel Corporation ";
constant actel_device_table : device_table_type := (
ACTEL_COREMP7 => "CoreMP7 Processor ",
others => "Unknown Device ");
constant actel_lib : vendor_library_type := (
vendorid => VENDOR_ACTEL,
vendordesc => ACTEL_DESC,
device_table => actel_device_table
);
constant NASA_DESC : vendor_description := "NASA ";
constant nasa_device_table : device_table_type := (
NASA_EP32 => "EP32 Forth processor ",
others => "Unknown Device ");
constant nasa_lib : vendor_library_type := (
vendorid => VENDOR_NASA,
vendordesc => NASA_DESC,
device_table => nasa_device_table
);
constant S3_DESC : vendor_description := "S3 Group ";
constant s3_device_table : device_table_type := (
others => "Unknown Device ");
constant s3_lib : vendor_library_type := (
vendorid => VENDOR_S3,
vendordesc => S3_DESC,
device_table => s3_device_table
);
constant APPLECORE_DESC : vendor_description := "AppleCore ";
constant applecore_device_table : device_table_type := (
APPLECORE_UTLEON3 => "AppleCore uT-LEON3 Processor ",
APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ",
others => "Unknown Device ");
constant applecore_lib : vendor_library_type := (
vendorid => VENDOR_APPLECORE,
vendordesc => APPLECORE_DESC,
device_table => applecore_device_table
);
constant C3E_DESC : vendor_description := "TU Braunschweig C3E ";
constant c3e_device_table : device_table_type := (
others => "Unknown Device ");
constant c3e_lib : vendor_library_type := (
vendorid => VENDOR_C3E,
vendordesc => C3E_DESC,
device_table => c3e_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_DLR => dlr_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_TELECOMPT => telecompt_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
VENDOR_ACTEL => actel_lib,
VENDOR_NASA => nasa_lib,
VENDOR_S3 => s3_lib,
others => unknown_lib);
type system_table_type is array (0 to 4095) of device_description;
constant system_table : system_table_type := (
LEON3_ACT_FUSION => "LEON3 Actel Fusion Dev. board ",
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ",
LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ",
LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ",
LEON3_PROXIMA => "LEON3 PROXIMA FPGA design ",
ALTERA_DE2 => "Altera DE2 Development board ",
ALTERA_DE4 => "TerASIC DE4 Development board ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
XILINX_ML506 => "Xilinx ML506 Development board ",
XILINX_ML507 => "Xilinx ML507 Development board ",
XILINX_ML509 => "Xilinx ML509 Development board ",
XILINX_ML510 => "Xilinx ML510 Development board ",
MICROSEMI_M2GL_EVAL=> "Microsemi IGLOO2 Evaluation kit",
XILINX_SP601 => "Xilinx SP601 Development board ",
XILINX_ML605 => "Xilinx ML605 Development board ",
others => "Unknown system ");
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity RegFile_T is
end RegFile_T;
architecture Beh of RegFile_T is
component RegFile
generic (
-- èíèöèàëèçàöèÿ ðåãèñòðà ïëþñ ðàçðÿäíîé øèíû äàííûõ
INITREG: std_logic_vector := "0000";
-- ðàçðÿäíîñòü øèíû àäðåñà
a: integer := 2);
port (
-- ñèãíàë èíèöèàëèçàöèè ðåãèñòðîâ
INIT: in std_logic;
-- øèíà äàííûõ äëÿ çàïèñè
WDP: in std_logic_vector(INITREG'range);
-- øèíà àäðåñà äëÿ çàïèñè
WA: in std_logic_vector(a-1 downto 0);
-- øèíà àäðåñà äëÿ ÷òåíèÿ
RA: in std_logic_vector(a-1 downto 0);
-- ñèãíàë ðàçðåøåíèÿ çàïèñè
WE: in std_logic;
-- ïðî÷èòàííûå äàííûå
RDP: out std_logic_vector(INITREG'range));
end component;
signal init: std_logic := '0';
signal wdp: std_logic_vector(3 downto 0):= "0000";
signal wa: std_logic_vector(1 downto 0) := "00";
signal ra: std_logic_vector(1 downto 0) := "00";
signal we: std_logic := '0';
signal rdp: std_logic_vector(3 downto 0) := "0000";
constant WAIT_Period: time := 10 ns;
begin
ufile: RegFile port map (
init => init,
wdp => wdp,
wa => wa,
ra => ra,
we => we,
rdp => rdp
);
main: process
begin
wait for wait_period;
init <= '1';
wait for wait_period / 2;
init <= '0';
wdp <= "1100";
wa <= "00";
we <= '1';
wait for wait_period / 2;
we <= '0';
wdp <= "1010";
wa <= "01";
wait for wait_period / 2;
we <= '1';
wait for wait_period / 2;
we <= '0';
wait for wait_period / 2;
ra <= "00";
wait for wait_period;
ra <= "01";
wait;
end process;
end Beh; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/12/2017 06:15:00 PM
-- Design Name:
-- Module Name: RAM_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_Controller is
generic( constant samples : integer := 128);
Port ( clk11kHz : in STD_LOGIC;
clk : in std_logic;
clk500kHz : in STD_LOGIC;
idata_valid : in std_logic;
sel : in STD_LOGIC_vector(1 downto 0);
reset : in std_logic;
iadcsel : in std_logic;
ointernalCount : out std_logic;
ena1 : out std_logic;
enb1 : out std_logic;
ena2 : out std_logic;
enb2 : out std_logic;
wea : out std_logic_vector(0 downto 0);
UARTen : out std_logic;
ocount1 : out std_logic_vector(13 downto 0);
ocount2 : out std_logic_vector(13 downto 0);
ocount4 : out std_logic_vector(13 downto 0);
ocount3 : out std_logic_vector(13 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
signal count1 : integer:= -1;
signal count2 : integer:= -1;
signal count3 : integer:= -1;
signal count4 : integer:= -1;
signal count2flag : std_logic;
signal count3flag : std_logic;
signal doneFlag : std_logic:= '0';
signal doneCount : integer :=0;
signal internalCount : std_logic:= '0';
signal Ssel : std_logic_vector(1 downto 0) := "00";
signal selRes : std_logic_vector(1 downto 0) := "00";
--signal sel : std_logic_vector(1 downto 0):= "11";
signal clk_cnt : integer;
signal clk_en : std_logic:= '0';
begin
--Ssel <= sel;
ointernalCount <= internalCount;
process(clk500kHz)
begin
if rising_edge(clk500kHz) then
if clk_cnt >= 2 then
clk_en <= not(clk_en);
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
process(iadcsel, reset,clk)--idata_valid, iadcsel, reset)
begin
if rising_edge(clk) then
wea <= "1";
if reset = '1' then
count1 <= -1;
elsif reset = '0' then
if iadcsel = '0' then
if count1 < samples then
count1 <= count1 + 1;
--ena1 <= '1';
elsif count1 >= samples - 1 AND ((count2 = samples -1 and sel = "01") or (count2 = samples - 1 and count3 = samples - 1 and internalCount = '0' and doneFlag = '1' and sel = "11")) then
count1 <= -1;
--ena1 <= '0';
end if;
end if;
end if;
end if;
end process;
process(iadcsel)
begin
if iadcsel = '0' then
ena1 <= '1';
ena2 <= '0';
elsif iadcsel = '1' then
ena1 <= '0';
ena2 <= '1';
end if;
end process;
process(iadcsel, reset,clk)--idata_valid, iadcsel, reset)
begin
if rising_edge(clk) then
wea <= "1";
if reset = '1' then
count4 <= -1;
elsif reset = '0' then
if iadcsel = '1' then
if count4 < samples then
count4 <= count4 + 1;
--ena1 <= '1';
elsif count4 >= samples - 1 AND ((count3 = samples -1 and sel = "01") or (count2 = samples - 1 and count3 = samples - 1 and internalCount = '0' and doneFlag = '1' and sel = "11")) then
count4 <= -1;
--ena1 <= '0';
end if;
end if;
end if;
end if;
end process;
-- if count1 < samples and iadcsel = '0' and idata_valid = '1' and Ssel = "00" then
-- count1 <= count1 + 1;
-- ena1 <= '1';
-- ena2 <= '0';
-- elsif count1 >= samples-1 AND ((count2 = samples - 1 and sel = "01") or (count2 = samples -1 and count3 = samples -1 and internalCount = '1' and doneFlag = '1' and sel = "11")) then
-- count1 <= -1;
-- end if;
-- if count4 < samples and iadcsel = '1' and idata_valid = '1' and Ssel = "00" then
-- count4 <= count4 + 1;
-- ena1 <= '0';
-- ena2 <= '1';
-- elsif count4 >= samples-1 AND ((count3 = samples - 1 and sel = "10") or (count2 = samples -1 and count3 = samples -1 and internalCount = '1' and doneFlag = '1' and sel = "11")) then
-- count4 <= -1;
-- end if;
--end if;
-- if rising_edge(clk500kHz) and iadcsel = '1' then
-- if count4 < samples then
-- count4 <= count1 + 1;
-- elsif count4 >= samples-1 AND (internalCount = '0' and doneFlag = '0') then --((count2 = samples-1 and sel = "01") or (count3 = samples-1 and sel = "10") or (count2 = samples - 1 and count3 = samples - 1 and sel = "11") or sel = "00") then
-- count4 <= 0;
-- end if;
-- end if;
--end process;
process(clk11kHz,sel)
begin
if rising_edge(clk11kHz) then
if reset = '1' then
count2 <= -1;
count3 <= -1;
enb1 <= '0';
enb2 <= '0';
--selRes <= "00";
elsif sel = "00" then--selRes = "00" then
elsif sel = "01" then
--selRes <= "01";
if count2 = samples - 1 then
count2 <= -1;
internalCount <= '0';
UARTen <= '0';
enb1 <= '0';
--doneFlag <= '1';
else
count2 <= count2 + 1;
UARTen <= '1';
enb1 <= '1';
internalCount <= '1';
end if;
elsif sel = "10" then
--selRes <= "01";
if count3 = samples - 1 then
count3 <= -1;
internalCount <= '0';
UARTen <= '0';
enb2 <= '0';
else
count3 <= count3 + 1;
internalCount <= '1';
UARTen <= '1';
enb2 <= '1';
end if;
elsif sel = "11" then
--selRes <= "01";
UARTen <= '1';
if count2 = samples - 1 then
if count3 = samples - 1 then
enb1 <= '0';
enb2 <= '0';
doneFlag <= '1';
internalCount <= '0';
--UARTen <= '0';
else
enb1 <= '0';
enb2 <= '1';
count3 <= count3 + 1;
--UARTen <= '1';
internalCount <= '1';
end if;
else
enb1 <= '1';
enb2 <= '0';
count2 <= count2 + 1;
--UARTen <= '1';
internalCount <= '1';
end if;
if doneFlag = '1' then
enb1 <= '0';
enb2 <= '0';
doneCount <= doneCount + 1;
internalCount <= '0';
if doneCount = samples then
count2 <= -1;
count3 <= -1;
doneFlag <= '0';
doneCount <= 0;
end if;
end if;
end if;
end if;
end process;
ocount1 <= std_logic_vector(to_signed(count1, ocount1'length));
ocount2 <= std_logic_vector(to_signed(count2, ocount2'length));
ocount3 <= std_logic_vector(to_signed(count3, ocount3'length));
ocount4 <= std_logic_vector(to_signed(count4, ocount4'length));
end Behavioral;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package %wbs_package_name is
type %wbs_reg_type is record
%wbs_register_typedef
end record;
component %wbs_component_name
port (
-- register outputs
%register_output_definitions
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.%wbs_package_name.all;
-------------------------------------------------------------------------------
entity %wbs_component_name is
-------------------------------------------------------------------------------
port (
-- register outputs
%register_output_definitions
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end %wbs_component_name;
-------------------------------------------------------------------------------
architecture behavioral of %wbs_component_name is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
%register_address_constants
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : %wbs_reg_type;
%signal_definitions
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
%address_comparators
-- register enable signals
%register_enables
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
%register_inputs
-- register output -> wbs_out via demultiplexer
%register_out_demux
-- register outputs -> non-wishbone outputs
%register_outputs
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- reset all registers
if (wbs_in.rst = '1') then
%register_reset_assignments
%register_store_conditions
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
|
entity e1 is
generic (
a : integer;
b : integer := a; -- OK
c : integer := d; -- Error
d : integer;
e, f : integer := e -- Error
);
end entity;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_nexys4d (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-23 1092 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
-------------------------------------------------------------------------------
--
-- The T48 Bus Connector.
-- Multiplexes all drivers of the T48 bus.
--
-- $Id: bus_mux.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity t48_bus_mux is
port (
alu_data_i : in word_t;
bus_data_i : in word_t;
dec_data_i : in word_t;
dm_data_i : in word_t;
pm_data_i : in word_t;
p1_data_i : in word_t;
p2_data_i : in word_t;
psw_data_i : in word_t;
tim_data_i : in word_t;
data_o : out word_t
);
end t48_bus_mux;
use work.t48_pack.bus_idle_level_c;
architecture rtl of t48_bus_mux is
begin
or_tree: if bus_idle_level_c = '0' generate
data_o <= alu_data_i or
bus_data_i or
dec_data_i or
dm_data_i or
pm_data_i or
p1_data_i or
p2_data_i or
psw_data_i or
tim_data_i;
end generate;
and_tree: if bus_idle_level_c = '1' generate
data_o <= alu_data_i and
bus_data_i and
dec_data_i and
dm_data_i and
pm_data_i and
p1_data_i and
p2_data_i and
psw_data_i and
tim_data_i;
end generate;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
entity FIFO is
begin
end entity;
entity FIFO is
begin
end entity;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:23:02 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.vhdl
-- Design : vio_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0],probe_out0[0:0],probe_out1[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2016.3";
begin
end;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: parity-generator.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity parity_generator is
port (w, clk, reset : in std_logic;
p : out std_logic);
end entity parity_generator;
architecture rtl of parity_generator is
type state is (even, odd);
signal current_state, next_state : state;
begin
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
current_state <= even;
else
current_state <= next_state;
end if;
end if;
end process;
process (current_state, w)
begin
if current_state = even then
if w = '1' then
p <= '1';
next_state <= odd;
else
p <= '0';
next_state <= even;
end if;
else
if w = '1' then
p <= '0';
next_state <= even;
else
p <= '1';
next_state <= odd;
end if;
end if;
end process;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity cyclic_reg_with_clock_vlg_vec_tst is
end cyclic_reg_with_clock_vlg_vec_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_core_lite_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- Output register from ARM (i.e. Send commands and Data)
SLV_REG00_OUT : out std_logic_vector(31 downto 0);
SLV_REG01_OUT : out std_logic_vector(31 downto 0);
SLV_REG02_OUT : out std_logic_vector(31 downto 0);
SLV_REG03_OUT : out std_logic_vector(31 downto 0);
-- Input register to ARM (i.e. Receive status and Data)
SLV_REG04_IN : in std_logic_vector(31 downto 0);
SLV_REG05_IN : in std_logic_vector(31 downto 0);
SLV_REG06_IN : in std_logic_vector(31 downto 0);
SLV_REG07_IN : in std_logic_vector(31 downto 0);
SLV_REG08_IN : in std_logic_vector(31 downto 0);
SLV_REG09_IN : in std_logic_vector(31 downto 0);
SLV_REG10_IN : in std_logic_vector(31 downto 0);
SLV_REG11_IN : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end example_core_lite_v1_0_S00_AXI;
architecture arch_imp of example_core_lite_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 12
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= slv_reg2;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= SLV_REG04_IN;
when b"0101" =>
reg_data_out <= SLV_REG05_IN;
when b"0110" =>
reg_data_out <= SLV_REG06_IN;
when b"0111" =>
reg_data_out <= SLV_REG07_IN;
when b"1000" =>
reg_data_out <= SLV_REG08_IN;
when b"1001" =>
reg_data_out <= SLV_REG09_IN;
when b"1010" =>
reg_data_out <= SLV_REG10_IN;
when b"1011" =>
reg_data_out <= SLV_REG11_IN;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
SLV_REG00_OUT <= slv_reg0;
SLV_REG01_OUT <= slv_reg1;
SLV_REG02_OUT <= slv_reg2;
SLV_REG03_OUT <= slv_reg3;
-- User logic ends
end arch_imp;
|
-- $Id: ibd_ibmon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_ibmon - syn
-- Description: ibus dev: ibus monitor
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4-2018.3; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-14 873 14.7 131013 xc6slx16-2 121 205 0 77 s 5.5
-- 2015-04-24 668 14.7 131013 xc6slx16-2 112 235 0 83 s 5.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 2.1.1 track ack properly
-- 2019-02-23 1115 2.1 revised iface, busy 10->8, delay 14->16 bits
-- 2017-04-16 879 2.0 revised interface, add suspend and repeat collapse
-- 2017-03-04 858 1.0.2 BUGFIX: wrap set when go=0 due to wena=0
-- 2015-05-02 672 1.0.1 use natural for AWIDTH to work around a ghdl issue
-- 2015-04-24 668 1.0 Initial version (derived from rbd_rbmon)
------------------------------------------------------------------------------
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 08 rcolw r/w/- repeat collapse writes
-- 07 rcolr r/w/- repeat collapse reads
-- 06 wstop r/w/- stop on wrap
-- 05 conena r/w/- con enable
-- 04 remena r/w/- rem enable
-- 03 locena r/w/- loc enable
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/w/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 12:01 hilim r/w/- upper address limit, inclusive (def: 177776)
-- 011 12:01 lolim r/w/- lower address limit, inclusive (def: 160000)
-- 100 addr r/w/- Address register
-- *:02 laddr r/w/- line address
-- 01:00 waddr r/w/- word address
-- 101 data r/w/- Data register
--
-- data format:
-- word 3 15 : burst (2nd re/we in a aval sequence)
-- 14 : tout (busy in last re-we cycle)
-- 13 : nak (no ack in last non-busy cycle)
-- 12 : ack (ack seen)
-- 11 : busy (busy seen)
-- 10 : -- (reserved)
-- 09 : we (write cycle)
-- 08 : rmw (read-modify-write)
-- 07:00 : nbusy (number of busy cycles)
-- word 2 : ndly (delay to previous request)
-- word 1 : data
-- word 0 15 : be1 (byte enable low)
-- 14 : be0 (byte enable high)
-- 13 : racc (remote access)
-- 12:01 : addr (word address)
-- 0 : cacc (console access)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
-- entities the validity of generics, that's why natural needed here ....
entity ibd_ibmon is -- ibus dev: ibus monitor
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); -- base address
AWIDTH : natural := 9); -- buffer size
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus: request
IB_SRES : out ib_sres_type; -- ibus: response
IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor)
);
end entity ibd_ibmon;
architecture syn of ibd_ibmon is
constant ibaddr_cntl : slv3 := "000"; -- cntl address offset
constant ibaddr_stat : slv3 := "001"; -- stat address offset
constant ibaddr_hilim : slv3 := "010"; -- hilim address offset
constant ibaddr_lolim : slv3 := "011"; -- lolim address offset
constant ibaddr_addr : slv3 := "100"; -- addr address offset
constant ibaddr_data : slv3 := "101"; -- data address offset
constant cntl_ibf_rcolw : integer := 8;
constant cntl_ibf_rcolr : integer := 7;
constant cntl_ibf_wstop : integer := 6;
constant cntl_ibf_conena : integer := 5;
constant cntl_ibf_remena : integer := 4;
constant cntl_ibf_locena : integer := 3;
subtype cntl_ibf_func is integer range 2 downto 0;
subtype stat_ibf_bsize is integer range 15 downto 13;
constant stat_ibf_wrap : integer := 2;
constant stat_ibf_susp : integer := 1;
constant stat_ibf_run : integer := 0;
subtype addr_ibf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_ibf_waddr is integer range 1 downto 0;
subtype iba_ibf_pref is integer range 15 downto 13;
subtype iba_ibf_addr is integer range 12 downto 1;
constant dat3_ibf_burst : integer := 15;
constant dat3_ibf_tout : integer := 14;
constant dat3_ibf_nak : integer := 13;
constant dat3_ibf_ack : integer := 12;
constant dat3_ibf_busy : integer := 11;
constant dat3_ibf_we : integer := 9;
constant dat3_ibf_rmw : integer := 8;
subtype dat3_ibf_nbusy is integer range 7 downto 0;
constant dat0_ibf_be1 : integer := 15;
constant dat0_ibf_be0 : integer := 14;
constant dat0_ibf_racc : integer := 13;
subtype dat0_ibf_addr is integer range 12 downto 1;
constant dat0_ibf_cacc : integer := 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rcolw : slbit; -- rcolw flag (repeat collect writes)
rcolr : slbit; -- rcolr flag (repeat collect reads)
wstop : slbit; -- wstop flag (stop on wrap)
conena : slbit; -- conena flag (record console access)
remena : slbit; -- remena flag (record remote access)
locena : slbit; -- locena flag (record local access)
susp : slbit; -- suspended flag
go : slbit; -- go flag (actively running)
hilim : slv13_1; -- upper address limit
lolim : slv13_1; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
addrsame: slbit; -- curr ib addr equal last ib addr
addrwind: slbit; -- curr ib addr in [lolim,hilim] window
aval_1 : slbit; -- last cycle aval
arm1r : slbit; -- 1st level arm for read
arm2r : slbit; -- 2nd level arm for read
arm1w : slbit; -- 1st level arm for write
arm2w : slbit; -- 2nd level arm for write
rcol : slbit; -- repeat collaps
ibtake_1: slbit; -- ib capture active in last cycle
ibaddr : slv13_1; -- ibus trace: addr
ibwe : slbit; -- ibus trace: we
ibrmw : slbit; -- ibus trace: rmw
ibbe0 : slbit; -- ibus trace: be0
ibbe1 : slbit; -- ibus trace: be1
ibcacc : slbit; -- ibus trace: cacc
ibracc : slbit; -- ibus trace: racc
iback : slbit; -- ibus trace: ack seen
ibbusy : slbit; -- ibus trace: busy seen
ibnak : slbit; -- ibus trace: nak detected
ibtout : slbit; -- ibus trace: tout detected
ibburst : slbit; -- ibus trace: burst detected
ibdata : slv16; -- ibus trace: data
ibnbusy : slv8; -- ibus number of busy cycles
ibndly : slv16; -- ibus delay to prev. access
end record regs_type;
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0', -- rcolw,rcolr,wstop
'1','1','1', -- conena,remena,locena
'0','1', -- susp,go
(others=>'1'), -- hilim (def: 177776)
(others=>'0'), -- lolim (def: 160000)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
'0','0','0', -- addrsame,addrwind,aval_1
'0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
'0', -- ibtake_1
(others=>'0'), -- ibaddr (startup: 160000)
'0','0','0','0','0','0', -- ibwe,ibrmw,ibbe0,ibbe1,ibcacc,ibracc
'0','0', -- iback,ibbusy
'0','0','0', -- ibnak,ibtout,ibburst
(others=>'0'), -- ibdata
(others=>'0'), -- ibnbusy
(others=>'0') -- ibndly
);
constant ibnbusylast : slv8 := (others=>'1');
constant ibndlylast : slv16 := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM0_DI : slv32 := (others=>'0');
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
severity failure;
BRAM1 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM1_DI,
DO => BRAM1_DO
);
BRAM0 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM0_DI,
DO => BRAM0_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, IB_SRES_SUM, BRAM0_DO, BRAM1_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iib_ack : slbit := '0';
variable iib_busy : slbit := '0';
variable iib_dout : slv16 := (others=>'0');
variable iibena : slbit := '0';
variable ibramen : slbit := '0'; -- BRAM enable
variable ibramwe : slbit := '0'; -- BRAN we
variable ibtake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat0 : slv16 := (others=>'0');
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iib_ack := '0';
iib_busy := '0';
iib_dout := (others=>'0');
iibena := IB_MREQ.re or IB_MREQ.we;
ibramen := '0';
ibramwe := '0';
laddr_inc := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 4)=IB_ADDR(12 downto 4) then
n.ibsel := '1';
ibramen := '1'; -- ensures bram read before ibus read
end if;
-- ibus transactions (react only on rem access; invisible on loc side)
if r.ibsel = '1' and IB_MREQ.racc='1' then
iib_ack := iibena; -- ack all accesses
case IB_MREQ.addr(3 downto 1) is
when ibaddr_cntl => -- cntl ------------------
if IB_MREQ.we = '1' then
case IB_MREQ.din(cntl_ibf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.rcolw := IB_MREQ.din(cntl_ibf_rcolw);
n.rcolr := IB_MREQ.din(cntl_ibf_rcolr);
n.wstop := IB_MREQ.din(cntl_ibf_wstop);
n.conena := IB_MREQ.din(cntl_ibf_conena);
n.remena := IB_MREQ.din(cntl_ibf_remena);
n.locena := IB_MREQ.din(cntl_ibf_locena);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
when func_sus => -- func: susp ------------
if r.go = '1' then -- noop unless running
n.go := '0';
n.susp := r.go;
end if;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when ibaddr_stat => null; -- stat ------------------
when ibaddr_hilim => -- hilim -----------------
if IB_MREQ.we = '1' then
n.hilim := IB_MREQ.din(iba_ibf_addr);
end if;
when ibaddr_lolim => -- lolim -----------------
if IB_MREQ.we = '1' then
n.lolim := IB_MREQ.din(iba_ibf_addr);
end if;
when ibaddr_addr => -- addr ------------------
if IB_MREQ.we = '1' then
if r.go = '0' then -- if not active OK
n.laddr := IB_MREQ.din(addr_ibf_laddr);
n.waddr := IB_MREQ.din(addr_ibf_waddr);
else
iib_ack := '0'; -- otherwise error, do nak
end if;
end if;
when ibaddr_data => -- data ------------------
-- write to data is an error, do nak
if IB_MREQ.we='1' then
iib_ack := '0';
end if;
-- read to data always allowed, addr only incremented when not active
if IB_MREQ.re = '1' and r.go = '0' then
n.waddr := slv(unsigned(r.waddr) + 1);
if r.waddr = "11" then
laddr_inc := '1';
end if;
end if;
when others => -- <> --------------------
iib_ack := '0'; -- error, do nak
end case;
end if;
-- ibus output driver
if r.ibsel = '1' then
case IB_MREQ.addr(3 downto 1) is
when ibaddr_cntl => -- cntl ------------------
iib_dout(cntl_ibf_rcolw) := r.rcolw;
iib_dout(cntl_ibf_rcolr) := r.rcolr;
iib_dout(cntl_ibf_wstop) := r.wstop;
iib_dout(cntl_ibf_conena) := r.conena;
iib_dout(cntl_ibf_remena) := r.remena;
iib_dout(cntl_ibf_locena) := r.locena;
when ibaddr_stat => -- stat ------------------
iib_dout(stat_ibf_bsize) := slv(to_unsigned(AWIDTH-9,3));
iib_dout(stat_ibf_wrap) := r.wrap;
iib_dout(stat_ibf_susp) := r.susp; -- started and suspended
iib_dout(stat_ibf_run) := r.go or r.susp; -- started
when ibaddr_hilim => -- hilim -----------------
iib_dout(iba_ibf_pref) := (others=>'1');
iib_dout(iba_ibf_addr) := r.hilim;
when ibaddr_lolim => -- lolim -----------------
iib_dout(iba_ibf_pref) := (others=>'1');
iib_dout(iba_ibf_addr) := r.lolim;
when ibaddr_addr => -- addr ------------------
iib_dout(addr_ibf_laddr) := r.laddr;
iib_dout(addr_ibf_waddr) := r.waddr;
when ibaddr_data => -- data ------------------
case r.waddr is
when "11" => iib_dout := BRAM1_DO(31 downto 16);
when "10" => iib_dout := BRAM1_DO(15 downto 0);
when "01" => iib_dout := BRAM0_DO(31 downto 16);
when "00" => iib_dout := BRAM0_DO(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- ibus monitor
-- a ibus transaction are captured if the address is in alim window
-- and the access is not refering to ibd_ibmon itself
-- ibus address monitor
if IB_MREQ.aval='1' and r.aval_1='0' then
n.ibaddr := IB_MREQ.addr;
n.addrsame := '0';
if IB_MREQ.addr = r.ibaddr then
n.addrsame := '1';
end if;
n.addrwind := '0';
if unsigned(IB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(IB_MREQ.addr)<=unsigned(r.hilim) then
n.addrwind := '1';
end if;
end if;
n.aval_1 := IB_MREQ.aval;
-- ibus data monitor
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
if IB_MREQ.we='1' then -- for write of din
n.ibdata := IB_MREQ.din;
else -- for read of dout
n.ibdata := IB_SRES_SUM.dout;
end if;
end if;
-- track state and decide on storage
ibtake := '0';
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
if r.addrwind='1' and r.ibsel='0' then -- and in window and not self
if (r.locena='1' and IB_MREQ.cacc='0' and IB_MREQ.racc='0') or
(r.remena='1' and IB_MREQ.racc='1') or
(r.conena='1' and IB_MREQ.cacc='1') then
ibtake := '1';
end if;
end if;
end if;
if ibtake = '1' then -- if capture active
n.ibwe := IB_MREQ.we; -- keep track of some state
n.ibrmw := IB_MREQ.rmw;
n.ibbe0 := IB_MREQ.be0;
n.ibbe1 := IB_MREQ.be1;
n.ibcacc := IB_MREQ.cacc;
n.ibracc := IB_MREQ.racc;
if r.ibtake_1 = '0' then -- if initial cycle of a transaction
n.iback := IB_SRES_SUM.ack;
n.ibbusy := IB_SRES_SUM.busy;
n.ibnbusy := (others=>'0');
else -- if non-initial cycles
n.iback := r.iback or IB_SRES_SUM.ack;
if r.ibnbusy /= ibnbusylast then -- and count
n.ibnbusy := slv(unsigned(r.ibnbusy) + 1);
end if;
end if;
n.ibnak := not IB_SRES_SUM.ack;
n.ibtout := IB_SRES_SUM.busy;
if IB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
n.arm1r := r.rcolr and IB_MREQ.re;
n.arm1w := r.rcolw and IB_MREQ.we;
n.arm2r := r.arm1r and r.addrsame and IB_MREQ.re;
n.arm2w := r.arm1w and r.addrsame and IB_MREQ.we;
n.rcol := ((r.arm2r and IB_MREQ.re) or
(r.arm2w and IB_MREQ.we)) and r.addrsame;
end if;
else -- if capture not active
if r.go='1' and r.ibtake_1='1' then -- active and transaction just ended
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
n.ibburst := '1'; -- assume burst
end if;
if r.ibtake_1 = '1' then -- ibus transaction just ended
n.ibndly := (others=>'0'); -- clear delay counter
else -- just idle
if r.ibndly /= ibndlylast then -- count cycles
n.ibndly := slv(unsigned(r.ibndly) + 1);
end if;
end if;
end if;
if IB_MREQ.aval = '0' then -- if aval gone
n.ibburst := '0'; -- clear burst flag
end if;
iaddrinc := (others=>'0');
iaddroff := (others=>'0');
iaddrinc(0) := not (r.rcol and r.go);
iaddroff(0) := (r.rcol and r.go);
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
end if;
idat3 := (others=>'0');
idat3(dat3_ibf_burst) := r.ibburst;
idat3(dat3_ibf_tout) := r.ibtout;
idat3(dat3_ibf_nak) := r.ibnak;
idat3(dat3_ibf_ack) := r.iback;
idat3(dat3_ibf_busy) := r.ibbusy;
idat3(dat3_ibf_we) := r.ibwe;
idat3(dat3_ibf_rmw) := r.ibrmw;
idat3(dat3_ibf_nbusy) := r.ibnbusy;
idat2 := r.ibndly;
idat1 := r.ibdata;
idat0(dat0_ibf_be1) := r.ibbe1;
idat0(dat0_ibf_be0) := r.ibbe0;
idat0(dat0_ibf_racc) := r.ibracc;
idat0(dat0_ibf_addr) := r.ibaddr;
idat0(dat0_ibf_cacc) := r.ibcacc;
n.ibtake_1 := ibtake;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
IB_SRES.dout <= iib_dout;
IB_SRES.ack <= iib_ack;
IB_SRES.busy <= iib_busy;
end process proc_next;
end syn;
|
--------------------------------------------------------------------------
-- Company: Gruppo IV - Sistemi Embedded 2016-17
-- Engineer: Colella Gianni, Guida Ciro, Lombardi Daniele
--
-- Create Date: 10.05.2017 12:34:37
-- Module Name: gpio_array - Structural
-- Target Devices: Zynq Z-7010
-- Tool Versions: Vivado 2016.4
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gpio_array is
Generic ( gpio_size : natural := 8);
Port ( pad_out : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_rw_n : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_en : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_in : out STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad : inout STD_LOGIC_VECTOR (gpio_size-1 downto 0));
end gpio_array;
architecture Structural of gpio_array is
component gpio is
Port ( pad_out : in STD_LOGIC;
pad_rw_n : in STD_LOGIC;
pad_en : in STD_LOGIC;
pad_in : out STD_LOGIC;
pad : inout STD_LOGIC);
end component;
begin
MULTI_GPIO : for i in 0 to gpio_size-1 generate
SINGLE_GPIO : gpio port map (
pad_rw_n=>pad_rw_n(i),
pad_out => pad_out(i),
pad_en => pad_en(i),
pad => pad(i),
pad_in => pad_in(i));
end generate;
end Structural;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Vektor
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
type TYPE_STATE_BYTE_CHECK is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK
signal n_SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, neuer Wert
signal SV_BYTE_CHECK_M : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, Ausgang Master
signal PARITY_OK : std_logic; --Signal, Parität in Ordnung
signal BYTE_CMPLT : std_logic; -- Signal, Byte vollständig
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
--NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
SV_BYTE_CHECK_M <= ST_BC_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
SV_BYTE_CHECK_M <= n_SV_BYTE_CHECK;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
SV_BYTE_CHECK_M <= SV_BYTE_CHECK_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
SV_BYTE_CHECK <= ST_BC_00;
else
if falling_edge(CLK)
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
SV_BYTE_CHECK <= SV_BYTE_CHECK_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV_BYTE_CHECK, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV_BYTE_CHECK is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_12; --Stoppbit erkannt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Vektor
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
type TYPE_STATE_BYTE_CHECK is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK
signal n_SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, neuer Wert
signal SV_BYTE_CHECK_M : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, Ausgang Master
signal PARITY_OK : std_logic; --Signal, Parität in Ordnung
signal BYTE_CMPLT : std_logic; -- Signal, Byte vollständig
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
--NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
SV_BYTE_CHECK_M <= ST_BC_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
SV_BYTE_CHECK_M <= n_SV_BYTE_CHECK;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
SV_BYTE_CHECK_M <= SV_BYTE_CHECK_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
SV_BYTE_CHECK <= ST_BC_00;
else
if falling_edge(CLK)
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
SV_BYTE_CHECK <= SV_BYTE_CHECK_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV_BYTE_CHECK, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV_BYTE_CHECK is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_12; --Stoppbit erkannt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00149.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149.P2: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149.P3: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00149
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00149)
-- ENT00149_Test_Bench(ARCH00149_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00149 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
end ARCH00149 ;
--
entity ENT00149_Test_Bench is
end ENT00149_Test_Bench ;
--
architecture ARCH00149_Test_Bench of ENT00149_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00149 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00149_Test_Bench ;
|
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CLAH8bits;
ARCHITECTURE strc_CLAH8bits of CLAH8bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4:STD_LOGIC_VECTOR(1 DOWNTO 0);
Component CLA2bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg8Bit
PORT (
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0),
val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2),
val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4),
val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout_sig
);
Som4: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6),
val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
Out_sig <= SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH8bits; |
-- NEED RESULT: ARCH00001: Different architectures associated with same entity passed
-- NEED RESULT: ARCH00001_1: Different architectures associated with same entity passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00001
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00001)
-- E00000(ARCH00001_1)
-- ENT00001_Test_Bench(ARCH00001_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00001 of E00000 is
begin
process
begin
test_report ( "ARCH00001" ,
"Different architectures associated with same entity" ,
true ) ;
wait ;
end process ;
end ARCH00001 ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00001_1 of E00000 is
begin
process
begin
test_report ( "ARCH00001_1" ,
"Different architectures associated with same entity" ,
true ) ;
wait ;
end process ;
end ARCH00001_1 ;
entity ENT00001_Test_Bench is
end ENT00001_Test_Bench ;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
begin
L1 :
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00001 );
for CIS2 : UUT use entity WORK.E00000 ( ARCH00001_1 );
begin
CIS1 : UUT;
CIS2 : UUT;
end block L1 ;
end ARCH00001_Test_Bench ;
|
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`protect end_protected
|
use std.textio.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149_TB is
end;
architecture Sim of YM2149_TB is
component YM2149
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end component;
-- signals
constant CLKPERIOD : time := 25 ns;
signal func : string(8 downto 1);
signal clk : std_logic;
signal reset_l : std_logic;
signal reset_h : std_logic;
signal da_in : std_logic_vector(7 downto 0);
signal da_out : std_logic_vector(7 downto 0);
signal da_oe_l : std_logic;
signal bdir : std_logic;
signal bc2 : std_logic;
signal bc1 : std_logic;
signal audio : std_logic_vector(7 downto 0);
signal ioa_in : std_logic_vector(7 downto 0);
signal ioa_out : std_logic_vector(7 downto 0);
signal ioa_oe_l : std_logic;
signal iob_in : std_logic_vector(7 downto 0);
signal iob_out : std_logic_vector(7 downto 0);
signal iob_oe_l : std_logic;
begin
u0 : YM2149
port map (
-- data bus
I_DA => da_in,
O_DA => da_out,
O_DA_OE_L => da_oe_l,
-- control
I_A9_L => '0',
I_A8 => '1',
I_BDIR => bdir,
I_BC2 => bc2,
I_BC1 => bc1,
I_SEL_L => '1',
O_AUDIO => audio,
-- port a
I_IOA => ioa_in,
O_IOA => ioa_out,
O_IOA_OE_L => ioa_oe_l,
-- port b
I_IOB => iob_in,
O_IOB => iob_out,
O_IOB_OE_L => iob_oe_l,
ENA => '1',
RESET_L => reset_l,
CLK => clk
);
p_clk : process
begin
CLK <= '0';
wait for CLKPERIOD / 2;
CLK <= '1';
wait for CLKPERIOD - (CLKPERIOD / 2);
end process;
p_debug_comb : process(bdir, bc2, bc1)
variable sel : std_logic_vector(2 downto 0);
begin
func <= "-XXXXXX-";
sel := bdir & bc2 & bc1;
case sel is
when "000" |
"010" |
"101" => func <= "inactive";
when "001" |
"100" |
"111" => func <= "address ";
when "011" => func <= "read ";
when "110" => func <= "write ";
when others => null;
end case;
end process;
p_test : process
procedure write(
addr : in bit_vector(3 downto 0);
data : in bit_vector(7 downto 0)
) is
begin
wait until rising_edge(clk);
-- addr
bdir <= '1';
bc2 <= '1';
bc1 <= '1';
da_in <= x"0" & to_stdlogicvector(addr);
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 80 ns;
da_in <= (others => 'Z');
wait for 100 ns;
-- write
bdir <= '1';
bc2 <= '1';
bc1 <= '0';
da_in <= to_stdlogicvector(data);
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 80 ns;
da_in <= (others => 'Z');
wait for 100 ns;
wait until rising_edge(clk);
end write;
procedure read(
addr : in bit_vector(3 downto 0)
) is
begin
wait until rising_edge(clk);
-- addr
bdir <= '1';
bc2 <= '1';
bc1 <= '1';
da_in <= x"0" & to_stdlogicvector(addr);
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 80 ns;
da_in <= (others => 'Z');
wait for 100 ns;
-- read
bdir <= '0';
bc2 <= '1';
bc1 <= '1';
da_in <= (others => 'Z');
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 180 ns;
wait until rising_edge(clk);
end read;
begin
reset_l <= '0';
reset_h <= '1';
da_in <= (others => 'Z');
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 100 ns;
reset_l <= '1';
reset_h <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
write(x"0",x"08");
write(x"1",x"00");
read(x"0");
wait for 500 ns;
write(x"7",x"fb");
write(x"8",x"00");
write(x"a",x"0f");
write(x"B",x"00");
write(x"C",x"00");
write(x"D",x"0E");
wait;
end process;
end Sim;
|
--------------------------------------------------------------------------------------------------
-- Signal Decomposition
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package decomposition_pkg is
--FIR filter component declaration
component decomposition is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y_low : out sig;
y_high : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.decimator_pkg.all;
entity decomposition is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y_low : out sig;
y_high : out sig);
end decomposition;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of decomposition is
begin
--Decimate the signal using a low pass filter
low_filter_bank : decimator
generic map(h => low_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_high => x,
sig_low => y_low);
--Decimate the signal using a high pass filter
high_filter_bank : decimator
generic map(h => high_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_high => x,
sig_low => y_high);
end behave;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned;
use IEEE.NUMERIC_STD.ALL;
package VHDL_lib is
function next_power_2(len: positive) return positive;
function char2int(arg : character) return natural;
function test_factor(input:std_logic_vector; value: integer; factor: integer) return boolean;
function char2std(arg : character) return std_logic_vector;
function log2 (x : positive) return natural;
function scale_log(input:std_logic_vector; max: integer) return std_logic_vector;
component fft is
generic(
vga_width:integer := 1920;
vga_height:integer := 1200;
input_size:integer := 16
);
port(
clk: in std_logic;
input: in std_logic_vector(input_size-1 downto 0);
valid: out std_logic;
index: out std_logic_vector(log2(vga_width)-1 downto 0);
output: out std_logic_vector(log2(vga_height)-1 downto 0)
);
end component;
component prn32 is
generic(
n: integer:= 4;
seed: std_logic_vector:= X"12345678"
);
port(
clk: in std_logic;
pn_val: out std_logic_vector(n-1 downto 0)
);
end component;
component audio is
generic(
bits_per_ch:integer := 24
);
port(
clk: in std_logic;
mclk: out std_logic;
bclk: out std_logic;
lrclk: out std_logic;
adc_sdata: in std_logic;
dac_sdata: out std_logic;
input: in std_logic_vector(bits_per_ch-1 downto 0)
);
end component;
component pwm is
Generic (
width:integer := 25;
size:integer := 50000000
);
Port (
clk: in std_logic;
duty: in std_logic_vector(width-1 downto 0);
output: out std_logic
);
end component;
component audio_i2c_drv is
port(
clk: in std_logic;
data: out std_logic_vector(31 downto 0);
ready: in std_logic;
valid: out std_logic
);
end component;
component spi is
port(
clk: in std_logic;
data: in std_logic_vector(31 downto 0);
ready: out std_logic;
valid: in std_logic;
clatch: out std_logic;
cclk: out std_logic;
cdata: out std_logic
);
end component;
component i2c is
port(
clk: in std_logic;
data: in std_logic_vector(31 downto 0);
ready: out std_logic;
valid: in std_logic;
sck: inout std_logic;
sda: inout std_logic
);
end component;
component mux is
generic(
size:integer := 4
);
port (
s : in std_logic_vector(log2(size)-1 downto 0);
input : in std_logic_vector(size-1 downto 0);
output : out std_logic
);
end component;
component delayer is
generic(
width:integer := 8;
stages:integer := 2
);
port(
clk: in std_logic;
input: in std_logic_vector(width-1 downto 0);
output: out std_logic_vector(width-1 downto 0)
);
end component;
component truncate is
generic(
size_in:integer := 10;
size_out:integer := 10
);
port(
clk: std_logic;
input: in std_logic_vector(size_in-1 downto 0);
output: out std_logic_vector(size_out-1 downto 0)
);
end component;
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
component xor_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
component ascii_table is
port(
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(40-1 downto 0)
);
end component;
component cro is
generic(
vga_width:integer := 1920;
vga_height:integer := 1200
);
Port (
clk_250MHz : in std_logic;
clk_100MHz : in STD_LOGIC;
ch1_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch1_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch1_update: in STD_LOGIC;
ch2_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch2_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch2_update: in STD_LOGIC;
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end component;
component and_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
component multi_mux is
generic(
size:integer := 4;
width:integer := 2
);
port (
s : in std_logic_vector(log2(size)-1 downto 0);
input : in std_logic_vector((width*size)-1 downto 0);
output : out std_logic_vector(width-1 downto 0)
);
end component;
component running_avg is
generic(
size:integer := 11
);
port(
clk: in std_logic;
input: in std_logic_vector(size-1 downto 0);
output: out std_logic_vector(size-1 downto 0)
);
end component;
component FULL_ADDER is
port (
A,B,CIN : in std_logic;
SUM,CARRY : out std_logic
);
end component;
component debounce is
generic(
delay:integer := 50000
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end component;
component n_register is
generic (
width:integer := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component;
component clk_div is
generic(
div:integer := 8
);
port(
input: in std_logic;
output: out std_logic;
state: out std_logic_vector(log2(div/2)-1 downto 0)
);
end component;
component adc is
port (
clk_250MHz : in std_logic;
adc_clk_in_p: in std_logic;
adc_clk_in_n: in std_logic;
adc_data_in_p: in std_logic_vector(7 downto 0);
adc_data_in_n: in std_logic_vector(7 downto 0);
adc_data: out std_logic_vector(15 downto 0)
);
end component;
component vga is
generic(
Hsync:integer := 208;
Hact:integer := 1920;
Hfp:integer := 128;
Hbp:integer := 336;
Vsync:integer := 3;
Vact:integer := 1200;
Vfp:integer := 1;
Vbp:integer := 38
);
port(
clk: in std_logic;
hscnt: out std_logic_vector(11 downto 0);
vscnt: out std_logic_vector(11 downto 0);
hspulse: out std_logic;
vspulse: out std_logic
);
end component;
component bitshift_div is
generic(
scale_size:integer := 3;
size:integer := 10
);
port(
scale: in std_logic_vector(scale_size-1 downto 0);
input: in std_logic_vector(size-1 downto 0);
output: out std_logic_vector(size-1 downto 0)
);
end component;
component HALF_ADDER is
port (
A,B : in std_logic;
SUM,CARRY : out std_logic
);
end component;
component dmod is
generic(
width:integer := 16
);
port(
clk: in std_logic;
I: in std_logic_vector(width-1 downto 0);
Q: in std_logic_vector(width-1 downto 0);
output: out std_logic_vector(width-1 downto 0)
);
end component;
component audio_spi_drv is
port(
clk: in std_logic;
data: out std_logic_vector(31 downto 0);
ready: in std_logic;
valid: out std_logic
);
end component;
component or_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
component modn is
generic(
size:integer := 4
);
port (
clk : in std_logic;
output : out std_logic_vector(log2(size)-1 downto 0)
);
end component;
component trigger is
generic(
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port (
clk : in STD_LOGIC;
input: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
valid: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0)
);
end component;
end;
package body VHDL_lib is
function next_power_2(len: positive) return positive is
variable n: positive;
begin
n := 1;
while n <= len loop
n := n * 2;
end loop;
return n;
end;
function char2int(arg : character) return natural is
begin
return character'pos(arg);
end char2int;
function test_factor(input:std_logic_vector; value: integer; factor: integer) return boolean is
variable result: boolean := false;
begin
for f in 0 to factor loop
if(to_integer(unsigned(input)) = (f*value)/factor )then
result := true;
end if;
end loop;
return result;
end;
function char2std(arg : character) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(char2int(arg), 8));
end char2std;
function log2 (x : positive) return natural is
variable i : natural;
begin
i := 0;
while (2**i < x) and i < 31 loop
i := i + 1;
end loop;
return i;
end function;
function scale_log(input:std_logic_vector; max: integer) return std_logic_vector is
constant level : integer := max/input'high;
variable result: integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
result := i;
exit;
end if;
end loop;
return std_logic_vector(to_signed(result*level,log2(max)));
end;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:31:38 03/28/2017
-- Design Name:
-- Module Name: Somador1bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Somador1bit is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC;
p : out STD_LOGIC;
g : out STD_LOGIC);
end Somador1bit;
architecture Behavioral of Somador1bit is
signal a: std_logic;
signal b: std_logic;
begin
a <= x and y;
b <= x xor y;
z <= x xor y xor cin;
cout <= a or (b and cin);
p <= b;
g <= a;
end Behavioral;
|
-- Flopoco adder pipeline delay: 14 clock cycles
-- TODO: verilog instantiation
--------------------------------------------------------------------------------
-- IntAdder_66_f400_uid4
-- (IntAdderAlternative_66_f400_uid8)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_66_f400_uid4 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end entity;
architecture arch of IntAdder_66_f400_uid4 is
signal s_sum_l0_idx0 : std_logic_vector(42 downto 0);
signal s_sum_l0_idx1, s_sum_l0_idx1_d1 : std_logic_vector(24 downto 0);
signal sum_l0_idx0, sum_l0_idx0_d1 : std_logic_vector(41 downto 0);
signal c_l0_idx0, c_l0_idx0_d1 : std_logic_vector(0 downto 0);
signal sum_l0_idx1 : std_logic_vector(23 downto 0);
signal c_l0_idx1 : std_logic_vector(0 downto 0);
signal s_sum_l1_idx1 : std_logic_vector(24 downto 0);
signal sum_l1_idx1 : std_logic_vector(23 downto 0);
signal c_l1_idx1 : std_logic_vector(0 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
s_sum_l0_idx1_d1 <= s_sum_l0_idx1;
sum_l0_idx0_d1 <= sum_l0_idx0;
c_l0_idx0_d1 <= c_l0_idx0;
end if;
end process;
--Alternative
s_sum_l0_idx0 <= ( "0" & X(41 downto 0)) + ( "0" & Y(41 downto 0)) + Cin;
s_sum_l0_idx1 <= ( "0" & X(65 downto 42)) + ( "0" & Y(65 downto 42));
sum_l0_idx0 <= s_sum_l0_idx0(41 downto 0);
c_l0_idx0 <= s_sum_l0_idx0(42 downto 42);
sum_l0_idx1 <= s_sum_l0_idx1(23 downto 0);
c_l0_idx1 <= s_sum_l0_idx1(24 downto 24);
----------------Synchro barrier, entering cycle 1----------------
s_sum_l1_idx1 <= s_sum_l0_idx1_d1 + c_l0_idx0_d1(0 downto 0);
sum_l1_idx1 <= s_sum_l1_idx1(23 downto 0);
c_l1_idx1 <= s_sum_l1_idx1(24 downto 24);
R <= sum_l1_idx1(23 downto 0) & sum_l0_idx0_d1(41 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_11_52_uid2_RightShifter
-- (RightShifter_53_by_max_55_uid10)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity FPAdder_11_52_uid2_RightShifter is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
S : in std_logic_vector(5 downto 0);
R : out std_logic_vector(107 downto 0) );
end entity;
architecture arch of FPAdder_11_52_uid2_RightShifter is
signal level0 : std_logic_vector(52 downto 0);
signal ps, ps_d1 : std_logic_vector(5 downto 0);
signal level1 : std_logic_vector(53 downto 0);
signal level2 : std_logic_vector(55 downto 0);
signal level3 : std_logic_vector(59 downto 0);
signal level4, level4_d1 : std_logic_vector(67 downto 0);
signal level5 : std_logic_vector(83 downto 0);
signal level6 : std_logic_vector(115 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
ps_d1 <= ps;
level4_d1 <= level4;
end if;
end process;
level0<= X;
ps<= S;
level1<= (0 downto 0 => '0') & level0 when ps(0) = '1' else level0 & (0 downto 0 => '0');
level2<= (1 downto 0 => '0') & level1 when ps(1) = '1' else level1 & (1 downto 0 => '0');
level3<= (3 downto 0 => '0') & level2 when ps(2) = '1' else level2 & (3 downto 0 => '0');
level4<= (7 downto 0 => '0') & level3 when ps(3) = '1' else level3 & (7 downto 0 => '0');
----------------Synchro barrier, entering cycle 1----------------
level5<= (15 downto 0 => '0') & level4_d1 when ps_d1(4) = '1' else level4_d1 & (15 downto 0 => '0');
level6<= (31 downto 0 => '0') & level5 when ps_d1(5) = '1' else level5 & (31 downto 0 => '0');
R <= level6(115 downto 8);
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_56_f400_uid12
-- (IntAdderClassical_56_f400_uid14)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_56_f400_uid12 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(55 downto 0);
Y : in std_logic_vector(55 downto 0);
Cin : in std_logic;
R : out std_logic_vector(55 downto 0) );
end entity;
architecture arch of IntAdder_56_f400_uid12 is
signal x0 : std_logic_vector(10 downto 0);
signal y0 : std_logic_vector(10 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(2 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(2 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(11 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
end if;
end process;
--Classical
x0 <= X(10 downto 0);
y0 <= Y(10 downto 0);
x1 <= X(52 downto 11);
y1 <= Y(52 downto 11);
x2 <= X(55 downto 53);
y2 <= Y(55 downto 53);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin;
----------------Synchro barrier, entering cycle 1----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(11);
----------------Synchro barrier, entering cycle 2----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(2 downto 0) & sum1_d1(41 downto 0) & sum0_d2(10 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- LZCShifter_57_to_57_counting_64_uid18
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Florent de Dinechin, Bogdan Pasca (2007)
--------------------------------------------------------------------------------
-- Pipeline depth: 5 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity LZCShifter_57_to_57_counting_64_uid18 is
port ( clk, rst : in std_logic;
I : in std_logic_vector(56 downto 0);
Count : out std_logic_vector(5 downto 0);
O : out std_logic_vector(56 downto 0) );
end entity;
architecture arch of LZCShifter_57_to_57_counting_64_uid18 is
signal level6, level6_d1 : std_logic_vector(56 downto 0);
signal count5, count5_d1, count5_d2, count5_d3, count5_d4, count5_d5 : std_logic;
signal level5 : std_logic_vector(56 downto 0);
signal count4, count4_d1, count4_d2, count4_d3, count4_d4 : std_logic;
signal level4, level4_d1 : std_logic_vector(56 downto 0);
signal count3, count3_d1, count3_d2, count3_d3 : std_logic;
signal level3, level3_d1 : std_logic_vector(56 downto 0);
signal count2, count2_d1, count2_d2 : std_logic;
signal level2, level2_d1 : std_logic_vector(56 downto 0);
signal count1, count1_d1 : std_logic;
signal level1, level1_d1 : std_logic_vector(56 downto 0);
signal count0 : std_logic;
signal level0 : std_logic_vector(56 downto 0);
signal sCount : std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
level6_d1 <= level6;
count5_d1 <= count5;
count5_d2 <= count5_d1;
count5_d3 <= count5_d2;
count5_d4 <= count5_d3;
count5_d5 <= count5_d4;
count4_d1 <= count4;
count4_d2 <= count4_d1;
count4_d3 <= count4_d2;
count4_d4 <= count4_d3;
level4_d1 <= level4;
count3_d1 <= count3;
count3_d2 <= count3_d1;
count3_d3 <= count3_d2;
level3_d1 <= level3;
count2_d1 <= count2;
count2_d2 <= count2_d1;
level2_d1 <= level2;
count1_d1 <= count1;
level1_d1 <= level1;
end if;
end process;
level6 <= I ;
count5<= '1' when level6(56 downto 25) = (56 downto 25=>'0') else '0';
----------------Synchro barrier, entering cycle 1----------------
level5<= level6_d1(56 downto 0) when count5_d1='0' else level6_d1(24 downto 0) & (31 downto 0 => '0');
count4<= '1' when level5(56 downto 41) = (56 downto 41=>'0') else '0';
level4<= level5(56 downto 0) when count4='0' else level5(40 downto 0) & (15 downto 0 => '0');
----------------Synchro barrier, entering cycle 2----------------
count3<= '1' when level4_d1(56 downto 49) = (56 downto 49=>'0') else '0';
level3<= level4_d1(56 downto 0) when count3='0' else level4_d1(48 downto 0) & (7 downto 0 => '0');
----------------Synchro barrier, entering cycle 3----------------
count2<= '1' when level3_d1(56 downto 53) = (56 downto 53=>'0') else '0';
level2<= level3_d1(56 downto 0) when count2='0' else level3_d1(52 downto 0) & (3 downto 0 => '0');
----------------Synchro barrier, entering cycle 4----------------
count1<= '1' when level2_d1(56 downto 55) = (56 downto 55=>'0') else '0';
level1<= level2_d1(56 downto 0) when count1='0' else level2_d1(54 downto 0) & (1 downto 0 => '0');
----------------Synchro barrier, entering cycle 5----------------
count0<= '1' when level1_d1(56 downto 56) = (56 downto 56=>'0') else '0';
level0<= level1_d1(56 downto 0) when count0='0' else level1_d1(55 downto 0) & (0 downto 0 => '0');
O <= level0;
sCount <= count5_d5 & count4_d4 & count3_d3 & count2_d2 & count1_d1 & count0;
Count <= sCount;
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_66_f400_uid20
-- (IntAdderClassical_66_f400_uid22)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_66_f400_uid20 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end entity;
architecture arch of IntAdder_66_f400_uid20 is
signal x0 : std_logic_vector(17 downto 0);
signal y0 : std_logic_vector(17 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(5 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(5 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(18 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(6 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
end if;
end process;
--Classical
x0 <= X(17 downto 0);
y0 <= Y(17 downto 0);
x1 <= X(59 downto 18);
y1 <= Y(59 downto 18);
x2 <= X(65 downto 60);
y2 <= Y(65 downto 60);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin;
----------------Synchro barrier, entering cycle 1----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(18);
----------------Synchro barrier, entering cycle 2----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(5 downto 0) & sum1_d1(41 downto 0) & sum0_d2(17 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_11_52_uid2
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 14 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity FPAdder_11_52_uid2 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(11+52+2 downto 0);
Y : in std_logic_vector(11+52+2 downto 0);
R : out std_logic_vector(11+52+2 downto 0) );
end entity;
architecture arch of FPAdder_11_52_uid2 is
component FPAdder_11_52_uid2_RightShifter is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
S : in std_logic_vector(5 downto 0);
R : out std_logic_vector(107 downto 0) );
end component;
component IntAdder_56_f400_uid12 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(55 downto 0);
Y : in std_logic_vector(55 downto 0);
Cin : in std_logic;
R : out std_logic_vector(55 downto 0) );
end component;
component IntAdder_66_f400_uid20 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end component;
component IntAdder_66_f400_uid4 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end component;
component LZCShifter_57_to_57_counting_64_uid18 is
port ( clk, rst : in std_logic;
I : in std_logic_vector(56 downto 0);
Count : out std_logic_vector(5 downto 0);
O : out std_logic_vector(56 downto 0) );
end component;
signal excExpFracX : std_logic_vector(64 downto 0);
signal excExpFracY : std_logic_vector(64 downto 0);
signal eXmeY, eXmeY_d1 : std_logic_vector(11 downto 0);
signal eYmeX, eYmeX_d1 : std_logic_vector(11 downto 0);
signal addCmpOp1 : std_logic_vector(65 downto 0);
signal addCmpOp2 : std_logic_vector(65 downto 0);
signal cmpRes : std_logic_vector(65 downto 0);
signal swap : std_logic;
signal newX, newX_d1, newX_d2, newX_d3 : std_logic_vector(65 downto 0);
signal newY, newY_d1 : std_logic_vector(65 downto 0);
signal expX, expX_d1, expX_d2, expX_d3, expX_d4, expX_d5 : std_logic_vector(10 downto 0);
signal excX : std_logic_vector(1 downto 0);
signal excY, excY_d1 : std_logic_vector(1 downto 0);
signal signX, signX_d1 : std_logic;
signal signY : std_logic;
signal EffSub, EffSub_d1, EffSub_d2, EffSub_d3, EffSub_d4, EffSub_d5, EffSub_d6, EffSub_d7, EffSub_d8, EffSub_d9, EffSub_d10, EffSub_d11, EffSub_d12, EffSub_d13 : std_logic;
signal sdsXsYExnXY, sdsXsYExnXY_d1 : std_logic_vector(5 downto 0);
signal sdExnXY : std_logic_vector(3 downto 0);
signal fracY : std_logic_vector(52 downto 0);
signal excRt, excRt_d1, excRt_d2, excRt_d3, excRt_d4, excRt_d5, excRt_d6, excRt_d7, excRt_d8, excRt_d9, excRt_d10, excRt_d11, excRt_d12 : std_logic_vector(1 downto 0);
signal signR, signR_d1, signR_d2, signR_d3, signR_d4, signR_d5, signR_d6, signR_d7, signR_d8, signR_d9, signR_d10, signR_d11, signR_d12 : std_logic;
signal expDiff : std_logic_vector(11 downto 0);
signal shiftedOut : std_logic;
signal shiftVal, shiftVal_d1 : std_logic_vector(5 downto 0);
signal shiftedFracY, shiftedFracY_d1 : std_logic_vector(107 downto 0);
signal sticky, sticky_d1, sticky_d2 : std_logic;
signal fracYfar : std_logic_vector(55 downto 0);
signal fracYfarXorOp : std_logic_vector(55 downto 0);
signal fracXfar : std_logic_vector(55 downto 0);
signal cInAddFar : std_logic;
signal fracAddResult : std_logic_vector(55 downto 0);
signal fracGRS : std_logic_vector(56 downto 0);
signal extendedExpInc, extendedExpInc_d1, extendedExpInc_d2, extendedExpInc_d3, extendedExpInc_d4, extendedExpInc_d5, extendedExpInc_d6 : std_logic_vector(12 downto 0);
signal nZerosNew, nZerosNew_d1 : std_logic_vector(5 downto 0);
signal shiftedFrac, shiftedFrac_d1 : std_logic_vector(56 downto 0);
signal updatedExp : std_logic_vector(12 downto 0);
signal eqdiffsign, eqdiffsign_d1, eqdiffsign_d2 : std_logic;
signal expFrac : std_logic_vector(65 downto 0);
signal stk, stk_d1 : std_logic;
signal rnd, rnd_d1 : std_logic;
signal grd, grd_d1 : std_logic;
signal lsb, lsb_d1 : std_logic;
signal addToRoundBit : std_logic;
signal RoundedExpFrac : std_logic_vector(65 downto 0);
signal upExc : std_logic_vector(1 downto 0);
signal fracR : std_logic_vector(51 downto 0);
signal expR : std_logic_vector(10 downto 0);
signal exExpExc : std_logic_vector(3 downto 0);
signal excRt2 : std_logic_vector(1 downto 0);
signal excR : std_logic_vector(1 downto 0);
signal computedR : std_logic_vector(65 downto 0);
signal X_d1 : std_logic_vector(11+52+2 downto 0);
signal Y_d1 : std_logic_vector(11+52+2 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
eXmeY_d1 <= eXmeY;
eYmeX_d1 <= eYmeX;
newX_d1 <= newX;
newX_d2 <= newX_d1;
newX_d3 <= newX_d2;
newY_d1 <= newY;
expX_d1 <= expX;
expX_d2 <= expX_d1;
expX_d3 <= expX_d2;
expX_d4 <= expX_d3;
expX_d5 <= expX_d4;
excY_d1 <= excY;
signX_d1 <= signX;
EffSub_d1 <= EffSub;
EffSub_d2 <= EffSub_d1;
EffSub_d3 <= EffSub_d2;
EffSub_d4 <= EffSub_d3;
EffSub_d5 <= EffSub_d4;
EffSub_d6 <= EffSub_d5;
EffSub_d7 <= EffSub_d6;
EffSub_d8 <= EffSub_d7;
EffSub_d9 <= EffSub_d8;
EffSub_d10 <= EffSub_d9;
EffSub_d11 <= EffSub_d10;
EffSub_d12 <= EffSub_d11;
EffSub_d13 <= EffSub_d12;
sdsXsYExnXY_d1 <= sdsXsYExnXY;
excRt_d1 <= excRt;
excRt_d2 <= excRt_d1;
excRt_d3 <= excRt_d2;
excRt_d4 <= excRt_d3;
excRt_d5 <= excRt_d4;
excRt_d6 <= excRt_d5;
excRt_d7 <= excRt_d6;
excRt_d8 <= excRt_d7;
excRt_d9 <= excRt_d8;
excRt_d10 <= excRt_d9;
excRt_d11 <= excRt_d10;
excRt_d12 <= excRt_d11;
signR_d1 <= signR;
signR_d2 <= signR_d1;
signR_d3 <= signR_d2;
signR_d4 <= signR_d3;
signR_d5 <= signR_d4;
signR_d6 <= signR_d5;
signR_d7 <= signR_d6;
signR_d8 <= signR_d7;
signR_d9 <= signR_d8;
signR_d10 <= signR_d9;
signR_d11 <= signR_d10;
signR_d12 <= signR_d11;
shiftVal_d1 <= shiftVal;
shiftedFracY_d1 <= shiftedFracY;
sticky_d1 <= sticky;
sticky_d2 <= sticky_d1;
extendedExpInc_d1 <= extendedExpInc;
extendedExpInc_d2 <= extendedExpInc_d1;
extendedExpInc_d3 <= extendedExpInc_d2;
extendedExpInc_d4 <= extendedExpInc_d3;
extendedExpInc_d5 <= extendedExpInc_d4;
extendedExpInc_d6 <= extendedExpInc_d5;
nZerosNew_d1 <= nZerosNew;
shiftedFrac_d1 <= shiftedFrac;
eqdiffsign_d1 <= eqdiffsign;
eqdiffsign_d2 <= eqdiffsign_d1;
stk_d1 <= stk;
rnd_d1 <= rnd;
grd_d1 <= grd;
lsb_d1 <= lsb;
X_d1 <= X;
Y_d1 <= Y;
end if;
end process;
-- Exponent difference and swap --
excExpFracX <= X(65 downto 64) & X(62 downto 0);
excExpFracY <= Y(65 downto 64) & Y(62 downto 0);
eXmeY <= ("0" & X(62 downto 52)) - ("0" & Y(62 downto 52));
eYmeX <= ("0" & Y(62 downto 52)) - ("0" & X(62 downto 52));
addCmpOp1<= "0" & excExpFracX;
addCmpOp2<= "1" & not(excExpFracY);
cmpAdder: IntAdder_66_f400_uid4 -- pipelineDepth=1 maxInDelay=0
port map ( clk => clk,
rst => rst,
Cin => '1',
R => cmpRes,
X => addCmpOp1,
Y => addCmpOp2);
----------------Synchro barrier, entering cycle 1----------------
swap <= cmpRes(65);
newX <= X_d1 when swap = '0' else Y_d1;
newY <= Y_d1 when swap = '0' else X_d1;
expX<= newX(62 downto 52);
excX<= newX(65 downto 64);
excY<= newY(65 downto 64);
signX<= newX(63);
signY<= newY(63);
EffSub <= signX xor signY;
sdsXsYExnXY <= signX & signY & excX & excY;
sdExnXY <= excX & excY;
----------------Synchro barrier, entering cycle 2----------------
fracY <= "00000000000000000000000000000000000000000000000000000" when excY_d1="00" else ('1' & newY_d1(51 downto 0));
with sdsXsYExnXY_d1 select
excRt <= "00" when "000000"|"010000"|"100000"|"110000",
"01" when "000101"|"010101"|"100101"|"110101"|"000100"|"010100"|"100100"|"110100"|"000001"|"010001"|"100001"|"110001",
"10" when "111010"|"001010"|"001000"|"011000"|"101000"|"111000"|"000010"|"010010"|"100010"|"110010"|"001001"|"011001"|"101001"|"111001"|"000110"|"010110"|"100110"|"110110",
"11" when others;
signR<= '0' when (sdsXsYExnXY_d1="100000" or sdsXsYExnXY_d1="010000") else signX_d1;
---------------- cycle 1----------------
expDiff <= eXmeY_d1 when swap = '0' else eYmeX_d1;
shiftedOut <= '1' when (expDiff >= 54) else '0';
shiftVal <= expDiff(5 downto 0) when shiftedOut='0' else CONV_STD_LOGIC_VECTOR(55,6) ;
----------------Synchro barrier, entering cycle 2----------------
RightShifterComponent: FPAdder_11_52_uid2_RightShifter -- pipelineDepth=1 maxInDelay=5.3072e-10
port map ( clk => clk,
rst => rst,
R => shiftedFracY,
S => shiftVal_d1,
X => fracY);
----------------Synchro barrier, entering cycle 3----------------
----------------Synchro barrier, entering cycle 4----------------
sticky <= '0' when (shiftedFracY_d1(52 downto 0)=CONV_STD_LOGIC_VECTOR(0,52)) else '1';
---------------- cycle 3----------------
----------------Synchro barrier, entering cycle 4----------------
fracYfar <= "0" & shiftedFracY_d1(107 downto 53);
fracYfarXorOp <= fracYfar xor (55 downto 0 => EffSub_d3);
fracXfar <= "01" & (newX_d3(51 downto 0)) & "00";
cInAddFar <= EffSub_d3 and not sticky;
fracAdder: IntAdder_56_f400_uid12 -- pipelineDepth=2 maxInDelay=1.57344e-09
port map ( clk => clk,
rst => rst,
Cin => cInAddFar,
R => fracAddResult,
X => fracXfar,
Y => fracYfarXorOp);
----------------Synchro barrier, entering cycle 6----------------
fracGRS<= fracAddResult & sticky_d2;
extendedExpInc<= ("00" & expX_d5) + '1';
LZC_component: LZCShifter_57_to_57_counting_64_uid18 -- pipelineDepth=5 maxInDelay=7.37e-10
port map ( clk => clk,
rst => rst,
Count => nZerosNew,
I => fracGRS,
O => shiftedFrac);
----------------Synchro barrier, entering cycle 11----------------
----------------Synchro barrier, entering cycle 12----------------
updatedExp <= extendedExpInc_d6 - ("0000000" & nZerosNew_d1);
eqdiffsign <= '1' when nZerosNew_d1="111111" else '0';
expFrac<= updatedExp & shiftedFrac_d1(55 downto 3);
---------------- cycle 11----------------
stk<= shiftedFrac(1) or shiftedFrac(0);
rnd<= shiftedFrac(2);
grd<= shiftedFrac(3);
lsb<= shiftedFrac(4);
----------------Synchro barrier, entering cycle 12----------------
addToRoundBit<= '0' when (lsb_d1='0' and grd_d1='1' and rnd_d1='0' and stk_d1='0') else '1';
roundingAdder: IntAdder_66_f400_uid20 -- pipelineDepth=2 maxInDelay=1.41172e-09
port map ( clk => clk,
rst => rst,
Cin => addToRoundBit,
R => RoundedExpFrac,
X => expFrac,
Y => "000000000000000000000000000000000000000000000000000000000000000000");
---------------- cycle 14----------------
upExc <= RoundedExpFrac(65 downto 64);
fracR <= RoundedExpFrac(52 downto 1);
expR <= RoundedExpFrac(63 downto 53);
exExpExc <= upExc & excRt_d12;
with (exExpExc) select
excRt2<= "00" when "0000"|"0100"|"1000"|"1100"|"1001"|"1101",
"01" when "0001",
"10" when "0010"|"0110"|"0101",
"11" when others;
excR <= "00" when (eqdiffsign_d2='1' and EffSub_d13='1') else excRt2;
computedR <= excR & signR_d12 & expR & fracR;
R <= computedR;
end architecture;
|
-------------------------------------------------------------------------------
--! @file statusControlReg.vhd
--
--! @brief Host interface Status-/Control Registers
--
--! @details The host interface status/control registers provide memory mapped
--! control of the interrupt generator (irqGen) and bridge (magicBridge).
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity statusControlReg is
generic (
--! Magic
gMagic : natural := 16#504C4B00#;
-- Version
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count pattern
gVersionCount : natural := 0;
-- BaseSets
--! BaseSets by Host
gHostBaseSet : natural := 2;
--! BaseSets by Pcp
gPcpBaseSet : natural := 10;
--! Interrupt source number
gIrqSourceCount : natural range 1 to 15 := 3
);
port (
-- Global
--! component wide clock signal
iClk : in std_logic;
--! component wide reset signal
iRst : in std_logic;
-- slave Host interface
--! host read
iHostRead : in std_logic;
--! host write
iHostWrite : in std_logic;
--! host byteenable
iHostByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! host address
iHostAddress : in std_logic_vector(10 downto 2);
--! host readdata
oHostReaddata : out std_logic_vector(cDword-1 downto 0);
--! host writedata
iHostWritedata : in std_logic_vector(cDword-1 downto 0);
--! host waitrequest
oHostWaitrequest : out std_logic;
-- slave PCP interface
--! pcp read
iPcpRead : in std_logic;
--! pcp write
iPcpWrite : in std_logic;
--! pcp byteenable
iPcpByteenable : in std_logic_vector(cDword/8-1 downto 0);
--! pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! pcp readdata
oPcpReaddata : out std_logic_vector(cDword-1 downto 0);
--! pcp writedata
iPcpWritedata : in std_logic_vector(cDword-1 downto 0);
--! pcp waitrequest
oPcpWaitrequest : out std_logic;
-- BaseSet link
--! BaseSet write strobe
oBaseSetWrite : out std_logic;
--! BaseSet read strobe
oBaseSetRead : out std_logic;
--! BaseSet byteenable
oBaseSetByteenable : out std_logic_vector;
--! BaseSet address bus
oBaseSetAddress : out std_logic_vector(LogDualis(gHostBaseSet+gPcpBaseSet)+2-1 downto 2);
--! BaseSet read data bus
iBaseSetData : in std_logic_vector;
--! BaseSet write data bus
oBaseSetData : out std_logic_vector;
--! BaseSet acknowledge
iBaseSetAck : in std_logic;
-- Interrupt control
--! master enable
oIrqMasterEnable : out std_logic;
--! interrupt source enable vector ('right is sync)
oIrqSourceEnable : out std_logic_vector(gIrqSourceCount downto 0);
--! interrupt acknowledge (pulse, 'right is sync)
oIrqAcknowledge : out std_logic_vector(gIrqSourceCount downto 0);
--! interrup set (pulse, no sync!)
oIrqSet : out std_logic_vector(gIrqSourceCount downto 1);
--! interrupt source pending
iIrqPending : in std_logic_vector(gIrqSourceCount downto 0);
--! external sync source enable
oExtSyncEnable : out std_logic;
--! external sync source config
oExtSyncConfig : out std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
-- miscellaneous
--! bridge activates
oBridgeEnable : out std_logic
);
end statusControlReg;
architecture Rtl of statusControlReg is
-- base for register content
--! magic base
constant cBaseMagic : natural := 16#0000#;
--! version base
constant cBaseVersion : natural := 16#0004#;
--! boot base
constant cBaseBootBase : natural := 16#0008#;
--! init base
constant cBaseInitBase : natural := 16#000C#;
--! bridge enable base
constant cBaseBridgeEnable : natural := 16#0200#;
--! command base
constant cBaseCommand : natural := 16#0204#;
--! state base
constant cBaseState : natural := 16#0206#;
--! error base
constant cBaseError : natural := 16#0208#;
--! heart beat
constant cBaseHeartBeat : natural := 16#020A#;
--! irq enable base
constant cBaseIrqEnable : natural := 16#0300#;
--! irq pending base
constant cBaseIrqPending : natural := 16#0302#;
--! irq master enable base
constant cBaseIrqMasterEnable : natural := 16#0304#;
--! irq ack base (host only)
constant cBaseIrqAck : natural := 16#0306#;
--! irq set base (pcp only)
constant cBaseIrqSet : natural := 16#0306#;
--! sync config base
constant cBaseSyncConfig : natural := 16#030C#;
--! base for base set
constant cBaseBaseSet : natural := 16#0400#;
--! base reserved
constant cBaseReserved : natural := 16#0500#;
--! type base registers (stored content)
type tRegisterInfo is record
--magic
--version
bootBase : std_logic_vector(cDword-1 downto 0);
initBase : std_logic_vector(cDword-1 downto 0);
end record;
--! type control register (stored content)
type tRegisterControl is record
bridgeEnable : std_logic;
command : std_logic_vector(cWord-1 downto 0);
state : std_logic_vector(cWord-1 downto 0);
error : std_logic_vector(cWord-1 downto 0);
heartBeat : std_logic_vector(cWord-1 downto 0);
end record;
--! type synchronization register (stored content)
type tRegisterSynchronization is record
irqSrcEnableHost : std_logic_vector(gIrqSourceCount downto 0);
irqSrcEnablePcp : std_logic_vector(gIrqSourceCount downto 0);
irqMasterEnable : std_logic;
syncConfig : std_logic_vector(cExtSyncConfigWidth-1 downto 0);
end record;
--! info register
signal regInfo, regInfo_next : tRegisterInfo;
--! info register initialisation
constant cRegInfoInit : tRegisterInfo := (
bootBase => (others => cInactivated),
initBase => (others => cInactivated)
);
--! control register
signal regControl : tRegisterControl;
--! control register next
signal regControl_next : tRegisterControl;
--! control register initialisation
constant cRegControlInit : tRegisterControl := (
bridgeEnable => cInactivated,
command => (others => cInactivated),
state => (others => cInactivated),
error => (others => cInactivated),
heartBeat => (others => cInactivated)
);
--! synchronization register
signal regSynchron : tRegisterSynchronization;
--! synchronization register next
signal regSynchron_next : tRegisterSynchronization;
--! synchronization register initialisation
constant cRegSynchronInit : tRegisterSynchronization := (
irqSrcEnableHost => (others => cInactivated),
irqSrcEnablePcp => (others => cInactivated),
irqMasterEnable => cInactivated,
syncConfig => (others => cInactivated)
);
--! host base writedata
signal hostBaseSetData : std_logic_vector(iBaseSetData'range);
--! host base write
signal hostBaseSetWrite : std_logic;
--! host base read
signal hostBaseSetRead : std_logic;
--! pcp base writedata
signal pcpBaseSetData : std_logic_vector(iBaseSetData'range);
--! pcp base write
signal pcpBaseSetWrite : std_logic;
--! pcp base read
signal pcpBaseSetRead : std_logic;
begin
--! register process creates storage of values
regClk : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
regInfo <= cRegInfoInit;
regControl <= cRegControlInit;
regSynchron <= cRegSynchronInit;
else
regInfo <= regInfo_next;
regControl <= regControl_next;
regSynchron <= regSynchron_next;
end if;
end if;
end process;
oHostWaitrequest <= not iBaseSetAck when (hostBaseSetRead = cActivated or
hostBaseSetWrite = cActivated) else
not(iHostWrite or iHostRead);
oPcpWaitrequest <= not iBaseSetAck when (pcpBaseSetRead = cActivated or
pcpBaseSetWrite = cActivated) else
not(iPcpWrite or iPcpRead);
oIrqMasterEnable <= regSynchron.irqMasterEnable;
oIrqSourceEnable <= regSynchron.irqSrcEnableHost and regSynchron.irqSrcEnablePcp;
oExtSyncEnable <= regSynchron.syncConfig(0);
oExtSyncConfig <= regSynchron.syncConfig(2 downto 1);
oBridgeEnable <= regControl.bridgeEnable;
-- pcp overrules host!
oBaseSetData <= pcpBaseSetData when pcpBaseSetWrite = cActivated else
pcpBaseSetData when pcpBaseSetRead = cActivated else
hostBaseSetData;
oBaseSetByteenable <= iPcpByteenable when pcpBaseSetWrite = cActivated else
iPcpByteenable when pcpBaseSetRead = cActivated else
iHostByteenable;
oBaseSetAddress <= std_logic_vector(unsigned(iPcpAddress(oBaseSetAddress'range))+gHostBaseSet)
when pcpBaseSetRead = cActivated or pcpBaseSetWrite = cActivated else
iHostAddress(oBaseSetAddress'range);
oBaseSetWrite <= pcpBaseSetWrite or hostBaseSetWrite;
oBaseSetRead <= pcpBaseSetRead or hostBaseSetRead;
--! register access
regAcc : process (
iHostWrite,
iHostRead,
iHostByteenable,
iHostAddress,
iHostWritedata,
iPcpWrite,
iPcpRead,
iPcpByteenable,
iPcpAddress,
iPcpWritedata,
regInfo,
regControl,
regSynchron,
iIrqPending,
iBaseSetData
)
variable vHostSelAddr : natural;
variable vPcpSelAddr : natural;
begin
-- default
-- registers
regInfo_next <= regInfo;
regControl_next <= regControl;
regSynchron_next <= regSynchron;
-- outputs
oHostReaddata <= (others => cInactivated);
oIrqAcknowledge <= (others => cInactivated);
hostBaseSetData <= (others => cInactivated);
hostBaseSetWrite <= cInactivated;
hostBaseSetRead <= cInactivated;
oIrqSet <= (others => cInactivated);
oPcpReaddata <= (others => cInactivated);
pcpBaseSetData <= (others => cInactivated);
pcpBaseSetWrite <= cInactivated;
pcpBaseSetRead <= cInactivated;
-- HOST
-- select content
-- write to content
-- and read from content
vHostSelAddr := to_integer(unsigned(iHostAddress))*4;
case vHostSelAddr is
when cBaseMagic =>
oHostReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oHostReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oHostReaddata <= regInfo.bootBase;
--bootBase is RO
when cBaseInitBase =>
oHostReaddata <= regInfo.initBase;
--initBase is RO
when cBaseBridgeEnable =>
oHostReaddata(0) <= regControl.bridgeEnable;
--bridge enable is RO
when cBaseState | cBaseCommand =>
oHostReaddata <= regControl.state & regControl.command;
if iHostWrite = cActivated then
--state is RO
if iHostByteenable(1) = cActivated then
regControl_next.command(cWord-1 downto cByte) <= iHostWritedata(cWord-1 downto cByte);
end if;
if iHostByteenable(0) = cActivated then
regControl_next.command(cByte-1 downto 0) <= iHostWritedata(cByte-1 downto 0);
end if;
end if;
when cBaseHeartBeat | cBaseError =>
oHostReaddata <= regControl.heartBeat & regControl.error;
--heartbeat and error are RO
when cBaseIrqPending | cBaseIrqEnable =>
oHostReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oHostReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnableHost;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnableHost(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseIrqAck | cBaseIrqMasterEnable =>
-- irq ack is SC
oHostReaddata(0) <= regSynchron.irqMasterEnable;
if iHostWrite = cActivated then
if iHostByteenable(0) = cActivated then
regSynchron_next.irqMasterEnable <= iHostWritedata(0);
end if;
for i in cDword-1 downto cWord loop
if iHostByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqAcknowledge(i-cWord) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oHostReaddata(cExtSyncConfigWidth-1 downto 0) <= regSynchron.syncConfig;
if iHostWrite = cActivated then
for i in cWord-1 downto 0 loop
if iHostByteenable(i/cByte) = cActivated and
i < cExtSyncConfigWidth then
regSynchron_next.syncConfig(i) <= iHostWritedata(i);
end if;
end loop;
end if;
when cBaseBaseSet to cBaseReserved-1 =>
if vHostSelAddr < cBaseBaseSet+gHostBaseSet*cDword/cByte then
oHostReaddata(iBaseSetData'range) <= iBaseSetData;
if iHostWrite = cActivated then
hostBaseSetData <= iHostWritedata(hostBaseSetData'range);
hostBaseSetWrite <= cActivated;
hostBaseSetRead <= cInactivated;
elsif iHostRead = cActivated then
hostBaseSetRead <= cActivated;
hostBaseSetWrite <= cInactivated;
else
hostBaseSetWrite <= cInactivated;
hostBaseSetRead <= cInactivated;
end if;
end if;
when others => null;
end case;
-- PCP
-- select content
-- write to content
-- and read from content
vPcpSelAddr := to_integer(unsigned(iPcpAddress)) * 4;
case vPcpSelAddr is
when cBaseMagic =>
oPcpReaddata <= std_logic_vector(to_unsigned(gMagic, cDword));
--magic is RO
when cBaseVersion =>
oPcpReaddata <=
std_logic_vector(to_unsigned(gVersionMajor, cByte)) &
std_logic_vector(to_unsigned(gVersionMinor, cByte)) &
std_logic_vector(to_unsigned(gVersionRevision, cByte)) &
std_logic_vector(to_unsigned(gVersionCount, cByte));
--version is RO
when cBaseBootBase =>
oPcpReaddata <= regInfo.bootBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.bootBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseInitBase =>
oPcpReaddata <= regInfo.initBase;
if iPcpWrite = cActivated then
for i in cDword-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regInfo_next.initBase(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseBridgeEnable =>
oPcpReaddata(0) <= regControl.bridgeEnable;
if iPcpWrite = cActivated then
regControl_next.bridgeEnable <= iPcpWritedata(0);
end if;
when cBaseState | cBaseCommand =>
oPcpReaddata <= regControl.state & regControl.command;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.state(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.command(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseHeartBeat | cBaseError =>
oPcpReaddata <= regControl.heartBeat & regControl.error;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.heartBeat(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated then
regControl_next.error(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseIrqPending | cBaseIrqEnable =>
oPcpReaddata(cWord+gIrqSourceCount downto cWord) <= iIrqPending;
oPcpReaddata(gIrqSourceCount downto 0) <= regSynchron.irqSrcEnablePcp;
if iPcpWrite = cActivated then
for i in cWord-1 downto 0 loop
if iPcpByteenable(i/cByte) = cActivated and
i <= gIrqSourceCount then
regSynchron_next.irqSrcEnablePcp(i) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseIrqSet | cBaseIrqMasterEnable =>
-- irq set is self-clearing
oPcpReaddata(0) <= regSynchron.irqMasterEnable;
if iPcpWrite = cActivated then
for i in cDword-1 downto cWord+1 loop
if iPcpByteenable(i/cByte) = cActivated and
(i-cWord) <= gIrqSourceCount then
oIrqSet(i-cWord) <= iPcpWritedata(i);
end if;
end loop;
end if;
when cBaseSyncConfig =>
oPcpReaddata(cExtSyncConfigWidth-1 downto 0) <=
regSynchron.syncConfig;
when cBaseBaseSet to cBaseReserved-1 =>
if vPcpSelAddr < cBaseBaseSet+gPcpBaseSet*cDword/cByte then
oPcpReaddata(iBaseSetData'range) <= iBaseSetData;
if iPcpWrite = cActivated then
pcpBaseSetData <= iPcpWritedata(pcpBaseSetData'range);
pcpBaseSetWrite <= cActivated;
pcpBaseSetRead <= cInactivated;
elsif iPcpRead = cActivated then
pcpBaseSetRead <= cActivated;
pcpBaseSetWrite <= cInactivated;
else
pcpBaseSetRead <= cInactivated;
pcpBaseSetWrite <= cInactivated;
end if;
end if;
when others => null;
end case;
end process;
end Rtl;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: bv_arithmetic-body.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:50:39 $
--
--------------------------------------------------------------------------
--
-- Bit vector arithmetic package body.
--
-- Does arithmetic and logical operations on bit vectors, treating them
-- as either unsigned or signed (2's complement) integers. Leftmost bit
-- is most significant or sign bit, rightmost bit is least significant
-- bit. Dyadic operations need the two arguments to be of the same
-- length, however their index ranges and directions may differ. Results
-- must be of the same length as the operands.
--
--------------------------------------------------------------------------
package body bv_arithmetic is
----------------------------------------------------------------
-- Type conversions
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_to_natural
--
-- Convert bit vector encoded unsigned integer to natural.
----------------------------------------------------------------
function bv_to_natural(bv : in bit_vector) return natural is
variable result : natural := 0;
begin
for index in bv'range loop
result := result * 2 + bit'pos(bv(index));
end loop;
return result;
end bv_to_natural;
----------------------------------------------------------------
-- natural_to_bv
--
-- Convert natural to bit vector encoded unsigned integer.
-- (length is used as the size of the result.)
----------------------------------------------------------------
function natural_to_bv(nat : in natural;
length : in natural) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length-1);
begin
for index in result'reverse_range loop
result(index) := bit'val(temp rem 2);
temp := temp / 2;
end loop;
return result;
end natural_to_bv;
----------------------------------------------------------------
-- bv_to_integer
--
-- Convert bit vector encoded signed integer to integer
----------------------------------------------------------------
function bv_to_integer(bv : in bit_vector) return integer is
variable temp : bit_vector(bv'range);
variable result : integer := 0;
begin
if bv(bv'left) = '1' then -- negative number
temp := not bv;
else
temp := bv;
end if;
for index in bv'range loop -- sign bit of temp = '0'
result := result * 2 + bit'pos(temp(index));
end loop;
if bv(bv'left) = '1' then
result := (-result) - 1;
end if;
return result;
end bv_to_integer;
----------------------------------------------------------------
-- integer_to_bv
--
-- Convert integer to bit vector encoded signed integer.
-- (length is used as the size of the result.)
----------------------------------------------------------------
function integer_to_bv(int : in integer;
length : in natural) return bit_vector is
variable temp : integer;
variable result : bit_vector(0 to length-1);
begin
if int < 0 then
temp := -(int+1);
else
temp := int;
end if;
for index in result'reverse_range loop
result(index) := bit'val(temp rem 2);
temp := temp / 2;
end loop;
if int < 0 then
result := not result;
result(result'left) := '1';
end if;
return result;
end integer_to_bv;
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add
--
-- Signed addition with overflow detection
----------------------------------------------------------------
procedure bv_add (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_add: operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end bv_add;
----------------------------------------------------------------
-- "+"
--
-- Signed addition without overflow detection
----------------------------------------------------------------
function "+" (bv1, bv2 : in bit_vector) return bit_vector is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '+' & '"' & ": operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
return result;
end "+";
----------------------------------------------------------------
-- bv_sub
--
-- Signed subtraction with overflow detection
----------------------------------------------------------------
procedure bv_sub (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_sub: operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end bv_sub;
----------------------------------------------------------------
-- "-"
--
-- Signed subtraction without overflow detection
----------------------------------------------------------------
function "-" (bv1, bv2 : in bit_vector) return bit_vector is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '-' & '"' & ": operands of different lengths"
severity failure;
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
return result;
end "-";
----------------------------------------------------------------
-- bv_addu
--
-- Unsigned addition with overflow detection
----------------------------------------------------------------
procedure bv_addu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_addu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry = '1';
end bv_addu;
----------------------------------------------------------------
-- bv_addu
--
-- Unsigned addition without overflow detection
----------------------------------------------------------------
procedure bv_addu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable carry : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_addu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
bv_result := result;
end bv_addu;
----------------------------------------------------------------
-- bv_subu
--
-- Unsigned subtraction with overflow detection
----------------------------------------------------------------
procedure bv_subu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable borrow : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_subu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := borrow = '1';
end bv_subu;
----------------------------------------------------------------
-- bv_subu
--
-- Unsigned subtraction without overflow detection
----------------------------------------------------------------
procedure bv_subu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv_result'length);
variable borrow : bit := '0';
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_subu: operands of different lengths"
severity failure;
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
bv_result := result;
end bv_subu;
----------------------------------------------------------------
-- bv_neg
--
-- Signed negation with overflow detection
----------------------------------------------------------------
procedure bv_neg (bv : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
CONSTANT zero : bit_vector(bv'range) := (others => '0');
begin
bv_sub( zero, bv, bv_result, overflow );
end bv_neg;
----------------------------------------------------------------
-- "-"
--
-- Signed negation without overflow detection
----------------------------------------------------------------
function "-" (bv : in bit_vector) return bit_vector is
CONSTANT zero : bit_vector(bv'range) := (others => '0');
begin
return zero - bv;
end "-";
----------------------------------------------------------------
-- bv_mult
--
-- Signed multiplication with overflow detection
----------------------------------------------------------------
procedure bv_mult (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable multu_result : bit_vector(bv1'range);
variable multu_overflow : boolean;
-- constant abs_min_int : bit_vector(bv1'range)
-- := (bv1'left => '1', others => '0');
-- causes Synthesia MINT code generator to prang. Work around:
variable abs_min_int : bit_vector(bv1'range) := (others => '0');
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_mult: operands of different lengths"
severity failure;
abs_min_int(bv1'left) := '1'; -- Synthesia work around
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_multu(op1, op2, multu_result, multu_overflow);
if (negative_result) then
overflow := multu_overflow or (multu_result > abs_min_int);
bv_result := - multu_result;
else
overflow := multu_overflow or (multu_result(multu_result'left) = '1');
bv_result := multu_result;
end if;
end bv_mult;
----------------------------------------------------------------
-- "*"
--
-- Signed multiplication without overflow detection
----------------------------------------------------------------
function "*" (bv1, bv2 : in bit_vector) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '*' & '"' & ": operands of different lengths"
severity failure;
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_multu(op1, op2, result);
if (negative_result) then
result := - result;
end if;
return result;
end "*";
----------------------------------------------------------------
-- bv_multu
--
-- Unsigned multiplication with overflow detection
----------------------------------------------------------------
procedure bv_multu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean) is
-- Based on shift&add multiplier in Appendix A of Hennessy & Patterson
constant bv_length : natural := bv1'length;
constant accum_length : natural := bv_length * 2;
constant zero : bit_vector(accum_length-1 downto bv_length)
:= (others => '0');
variable accum : bit_vector(accum_length-1 downto 0);
variable addu_overflow : boolean;
variable carry : bit;
begin
assert bv1'length = bv2'length and bv1'length = bv_result'length
report "bv_multu: operands of different lengths"
severity failure;
accum(bv_length-1 downto 0) := bv1;
accum(accum_length-1 downto bv_length) := zero;
for count in 1 to bv_length loop
if (accum(0) = '1') then
bv_addu( accum(accum_length-1 downto bv_length), bv2,
accum(accum_length-1 downto bv_length), addu_overflow);
carry := bit'val(boolean'pos(addu_overflow));
else
carry := '0';
end if;
accum := carry & accum(accum_length-1 downto 1);
end loop;
bv_result := accum(bv_length-1 downto 0);
overflow := accum(accum_length-1 downto bv_length) /= zero;
end bv_multu;
----------------------------------------------------------------
-- bv_multu
--
-- Unsigned multiplication without overflow detection
----------------------------------------------------------------
procedure bv_multu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
-- Use bv_multu with overflow detection, but ignore overflow flag
variable tmp_overflow : boolean;
begin
-- following procedure asserts bv1'length = bv2'length
bv_multu(bv1, bv2, bv_result, tmp_overflow);
end bv_multu;
----------------------------------------------------------------
-- bv_div
--
-- Signed division with divide by zero and overflow detection
----------------------------------------------------------------
procedure bv_div (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean;
overflow : out boolean) is
-- Need overflow, in case divide b"10...0" (min_int) by -1
-- Don't use bv_to_int, in case size bigger than host machine!
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable divu_result : bit_vector(bv1'range);
begin
assert bv1'length = bv2'length
report "bv_div: operands of different lengths"
severity failure;
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_divu(op1, op2, divu_result, div_by_zero);
if (negative_result) then
overflow := false;
bv_result := - divu_result;
else
overflow := divu_result(divu_result'left) = '1';
bv_result := divu_result;
end if;
end bv_div;
----------------------------------------------------------------
-- "/"
--
-- Signed division without divide by zero and overflow detection
----------------------------------------------------------------
function "/" (bv1, bv2 : in bit_vector) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
assert bv1'length = bv2'length
-- use concatenation to work around Synthesia MINT code gen bug
report '"' & '/' & '"' & ": operands of different lengths"
severity failure;
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if (op1(op1'left) = '1') then
op1 := - bv1;
end if;
if (op2(op2'left) = '1') then
op2 := - bv2;
end if;
bv_divu(op1, op2, result);
if (negative_result) then
result := - result;
end if;
return result;
end "/";
----------------------------------------------------------------
-- bv_divu
--
-- Unsigned division with divide by zero detection
----------------------------------------------------------------
procedure bv_divu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean) is
-- based on algorithm in Sun Sparc architecture manual
constant len : natural := bv1'length;
variable zero, one,
big_value : bit_vector(len-1 downto 0)
:= (others => '0');
variable dividend : bit_vector(bv1'length-1 downto 0) := bv1;
variable divisor : bit_vector(bv2'length-1 downto 0) := bv2;
variable quotient : bit_vector(len-1 downto 0); -- unsigned
variable remainder : bit_vector(len-1 downto 0); -- signed
variable shifted_divisor,
shifted_1 : bit_vector(len-1 downto 0);
variable log_quotient : natural;
variable ignore_overflow : boolean;
begin
assert bv1'length = bv2'length
report "bv_divu: operands of different lengths"
severity failure;
one(0) := '1';
big_value(len-2) := '1';
--
-- check for zero divisor
--
if (divisor = zero) then
div_by_zero := true;
return;
end if;
--
-- estimate log of quotient
--
log_quotient := 0;
shifted_divisor := divisor;
loop
exit when (log_quotient >= len)
or (shifted_divisor > big_value)
or (shifted_divisor >= dividend);
log_quotient := log_quotient + 1;
shifted_divisor := bv_sll(shifted_divisor, 1);
end loop;
--
-- perform division
--
remainder := dividend;
quotient := zero;
shifted_divisor := bv_sll(divisor, log_quotient);
shifted_1 := bv_sll(one, log_quotient);
for iter in log_quotient downto 0 loop
if bv_ge(remainder, zero) then
bv_sub(remainder, shifted_divisor, remainder, ignore_overflow);
bv_addu(quotient, shifted_1, quotient, ignore_overflow);
else
bv_add(remainder, shifted_divisor, remainder, ignore_overflow);
bv_subu(quotient, shifted_1, quotient, ignore_overflow);
end if;
shifted_divisor := '0' & shifted_divisor(len-1 downto 1);
shifted_1 := '0' & shifted_1(len-1 downto 1);
end loop;
if (bv_lt(remainder, zero)) then
bv_add(remainder, divisor, remainder, ignore_overflow);
bv_subu(quotient, one, quotient, ignore_overflow);
end if;
bv_result := quotient;
end bv_divu;
----------------------------------------------------------------
-- bv_divu
--
-- Unsigned division without divide by zero detection
----------------------------------------------------------------
procedure bv_divu (bv1, bv2 : in bit_vector;
bv_result : out bit_vector) is
-- Use bv_divu with divide by zero detection,
-- but ignore div_by_zero flag
variable tmp_div_by_zero : boolean;
begin
-- following procedure asserts bv1'length = bv2'length
bv_divu(bv1, bv2, bv_result, tmp_div_by_zero);
end bv_divu;
----------------------------------------------------------------
-- Logical operators
-- (Provided for VHDL-87, built in for VHDL-93)
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sll
--
-- Shift left logical (fill with '0' bits)
----------------------------------------------------------------
function bv_sll (bv : in bit_vector;
shift_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_shift_count : natural := shift_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length) := (others => '0');
begin
result(1 to bv_length - actual_shift_count)
:= bv_norm(actual_shift_count + 1 to bv_length);
return result;
end bv_sll;
----------------------------------------------------------------
-- bv_srl
--
-- Shift right logical (fill with '0' bits)
----------------------------------------------------------------
function bv_srl (bv : in bit_vector;
shift_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_shift_count : natural := shift_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length) := (others => '0');
begin
result(actual_shift_count + 1 to bv_length)
:= bv_norm(1 to bv_length - actual_shift_count);
return result;
end bv_srl;
----------------------------------------------------------------
-- bv_sra
--
-- Shift right arithmetic (fill with copy of sign bit)
----------------------------------------------------------------
function bv_sra (bv : in bit_vector;
shift_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_shift_count : natural := shift_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length) := (others => bv(bv'left));
begin
result(actual_shift_count + 1 to bv_length)
:= bv_norm(1 to bv_length - actual_shift_count);
return result;
end bv_sra;
----------------------------------------------------------------
-- bv_rol
--
-- Rotate left
----------------------------------------------------------------
function bv_rol (bv : in bit_vector;
rotate_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_rotate_count : natural := rotate_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length);
begin
result(1 to bv_length - actual_rotate_count)
:= bv_norm(actual_rotate_count + 1 to bv_length);
result(bv_length - actual_rotate_count + 1 to bv_length)
:= bv_norm(1 to actual_rotate_count);
return result;
end bv_rol;
----------------------------------------------------------------
-- bv_ror
--
-- Rotate right
----------------------------------------------------------------
function bv_ror (bv : in bit_vector;
rotate_count : in natural) return bit_vector is
constant bv_length : natural := bv'length;
constant actual_rotate_count : natural := rotate_count mod bv_length;
alias bv_norm : bit_vector(1 to bv_length) is bv;
variable result : bit_vector(1 to bv_length);
begin
result(actual_rotate_count + 1 to bv_length)
:= bv_norm(1 to bv_length - actual_rotate_count);
result(1 to actual_rotate_count)
:= bv_norm(bv_length - actual_rotate_count + 1 to bv_length);
return result;
end bv_ror;
----------------------------------------------------------------
-- Arithmetic comparison operators.
-- Perform comparisons on bit vector encoded signed integers.
-- (For unsigned integers, built in lexical comparison does
-- the required operation.)
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt
--
-- Signed less than comparison
----------------------------------------------------------------
function bv_lt (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_lt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 < tmp2;
end bv_lt;
----------------------------------------------------------------
-- bv_le
--
-- Signed less than or equal comparison
----------------------------------------------------------------
function bv_le (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_le: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 <= tmp2;
end bv_le;
----------------------------------------------------------------
-- bv_gt
--
-- Signed greater than comparison
----------------------------------------------------------------
function bv_gt (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_gt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 > tmp2;
end bv_gt;
----------------------------------------------------------------
-- bv_ge
--
-- Signed greater than or equal comparison
----------------------------------------------------------------
function bv_ge (bv1, bv2 : in bit_vector) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_ged: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 >= tmp2;
end bv_ge;
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext
--
-- Sign extension - replicate the sign bit of the operand into
-- the most significant bits of the result. Length parameter
-- determines size of result. If length < bv'length, result is
-- rightmost length bits of bv.
----------------------------------------------------------------
function bv_sext (bv : in bit_vector;
length : in natural) return bit_vector is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : bit_vector(1 to length) := (others => bv(bv'left));
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(length - src_length + 1 to length)
:= bv_norm(bv'length - src_length + 1 to bv'length);
return result;
end bv_sext;
----------------------------------------------------------------
-- bv_zext
--
-- Zero extension - replicate zero bits into the most significant
-- bits of the result. Length parameter determines size of result.
-- If length < bv'length, result is rightmost length bits of bv.
----------------------------------------------------------------
function bv_zext (bv : in bit_vector;
length : in natural) return bit_vector is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : bit_vector(1 to length) := (others => '0');
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(length - src_length + 1 to length)
:= bv_norm(bv'length - src_length + 1 to bv'length);
return result;
end bv_zext;
end bv_arithmetic;
|
-------------------------------------------------------------------------------
-- Title : Numerically controlled oscillator - NCO
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2015-08-24
-------------------------------------------------------------------------------
-- Copyright (c) 2015, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reset_pkg.all;
package nco_pkg is
component nco is
generic (
ACCU_WIDTH : natural;
PHASE_WIDTH : natural;
RESET_IMPL : reset_type);
port (
en : in std_logic;
phase_increment : in std_logic_vector(ACCU_WIDTH-1 downto 0);
phase : out std_logic_vector(PHASE_WIDTH-1 downto 0);
load : in std_logic;
accu_load : in std_logic_vector(ACCU_WIDTH-1 downto 0);
reset : in std_logic;
clk : in std_logic);
end component nco;
end package nco_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity control_processor is
generic ( Tpd : delay_length := 3 ns );
end entity control_processor;
-- end not in book
architecture rtl of control_processor is
type func_code is (add, subtract);
signal op1, op2, dest : integer;
signal Z_flag : boolean;
signal func : func_code;
-- . . .
begin
alu : process is
procedure do_arith_op is
variable result : integer;
begin
case func is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
begin
-- . . .
do_arith_op;
-- . . .
-- not in book
wait on op1, op2, func;
-- end not in book
end process alu;
-- . . .
-- not in book
stimulus : process is
begin
op1 <= 0; op2 <= 0; wait for 10 ns;
op1 <= 10; op2 <= 3; wait for 10 ns;
func <= subtract; wait for 10 ns;
op2 <= 10; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity control_processor is
generic ( Tpd : delay_length := 3 ns );
end entity control_processor;
-- end not in book
architecture rtl of control_processor is
type func_code is (add, subtract);
signal op1, op2, dest : integer;
signal Z_flag : boolean;
signal func : func_code;
-- . . .
begin
alu : process is
procedure do_arith_op is
variable result : integer;
begin
case func is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
begin
-- . . .
do_arith_op;
-- . . .
-- not in book
wait on op1, op2, func;
-- end not in book
end process alu;
-- . . .
-- not in book
stimulus : process is
begin
op1 <= 0; op2 <= 0; wait for 10 ns;
op1 <= 10; op2 <= 3; wait for 10 ns;
func <= subtract; wait for 10 ns;
op2 <= 10; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity control_processor is
generic ( Tpd : delay_length := 3 ns );
end entity control_processor;
-- end not in book
architecture rtl of control_processor is
type func_code is (add, subtract);
signal op1, op2, dest : integer;
signal Z_flag : boolean;
signal func : func_code;
-- . . .
begin
alu : process is
procedure do_arith_op is
variable result : integer;
begin
case func is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
begin
-- . . .
do_arith_op;
-- . . .
-- not in book
wait on op1, op2, func;
-- end not in book
end process alu;
-- . . .
-- not in book
stimulus : process is
begin
op1 <= 0; op2 <= 0; wait for 10 ns;
op1 <= 10; op2 <= 3; wait for 10 ns;
func <= subtract; wait for 10 ns;
op2 <= 10; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture rtl;
|
entity repropoc is
end ;
library IEEE;
use IEEE.std_logic_1164.all;
package config_private is
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is STRING(1 to 16);
subtype T_BOARD_CONFIG_STRING is STRING(1 to 64);
subtype T_DEVICE_STRING is STRING(1 to 32);
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING;
RS_DataInterface : T_BOARD_CONFIG_STRING;
PHY_Device : T_BOARD_CONFIG_STRING;
PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
BoardName : T_BOARD_CONFIG_STRING;
FPGADevice : T_BOARD_CONFIG_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO;
constant C_POC_NUL : CHARACTER;
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR;
end package;
package body config_private is
constant C_POC_NUL : CHARACTER := '~';
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
function conf(str : string) return T_BOARD_CONFIG_STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to T_BOARD_CONFIG_STRING'length);
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then
Result(1 to str'length) := str;
end if;
return Result;
end function;
constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := (
IPStyle => C_BOARD_CONFIG_STRING_EMPTY,
RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_Device => C_BOARD_CONFIG_STRING_EMPTY,
PHY_DeviceAddress => x"00",
PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY
);
-- predefined UART descriptions
function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf(FlowControl);
Result.BaudRate := conf(BaudRate);
Result.BaudRate_Max := conf(BaudRate);
return Result;
end function;
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC :=
brd_CreateUART(TRUE, "NONE", "0 Bd");
function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING;
PHY_Device : STRING;
PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0);
PHY_DataInt : STRING;
PHY_MgntInt : STRING)
return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf(IPStyle);
Result.RS_DataInterface := conf(RS_DataInt);
Result.PHY_Device := conf(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf(PHY_DataInt);
Result.PHY_ManagementInterface := conf(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC :=
brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- Board Descriptions
-- =========================================================================
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
-- Custom Board (MUST BE LAST ONE)
-- ======================================================================
1 => (
BoardName => conf("Custom"),
FPGADevice => conf("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
end package body;
use work.config_private.all;
architecture behav of repropoc is
begin
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KeyboardController is
Port ( Clock : in STD_LOGIC;
KeyboardClock : in STD_LOGIC;
KeyboardData : in STD_LOGIC;
LeftPaddleDirection : inout integer;
RightPaddleDirection : inout integer
);
end KeyboardController;
architecture Behavioral of KeyboardController is
signal bitCount : integer range 0 to 100 := 0;
signal scancodeReady : STD_LOGIC := '0';
signal scancode : STD_LOGIC_VECTOR(7 downto 0);
signal breakReceived : STD_LOGIC := '0';
constant keyboardA : STD_LOGIC_VECTOR(7 downto 0) := "00011100";
constant keyboardZ : STD_LOGIC_VECTOR(7 downto 0) := "00011010";
constant keyboardK : STD_LOGIC_VECTOR(7 downto 0) := "01000010";
constant keyboardM : STD_LOGIC_VECTOR(7 downto 0) := "00111010";
begin
keyboard_scan_ready_enable : process(KeyboardClock)
begin
if falling_edge(KeyboardClock) then
if bitCount = 0 and KeyboardData = '0' then --keyboard wants to send data
scancodeReady <= '0';
bitCount <= bitCount + 1;
elsif bitCount > 0 and bitCount < 9 then -- shift one bit into the scancode from the left
scancode <= KeyboardData & scancode(7 downto 1);
bitCount <= bitCount + 1;
elsif bitCount = 9 then -- parity bit
bitCount <= bitCount + 1;
elsif bitCount = 10 then -- end of message
scancodeReady <= '1';
bitCount <= 0;
end if;
end if;
end process keyboard_scan_ready_enable;
scan_keyboard : process(scancodeReady, scancode)
begin
if scancodeReady'event and scancodeReady = '1' then
-- breakcode breaks the current scancode
if breakReceived = '1' then
breakReceived <= '0';
if scancode = keyboardA or scancode = keyboardY then
LeftPaddleDirection <= 0;
elsif scancode = keyboardK or scancode = keyboardM then
RightPaddleDirection <= 0;
end if;
elsif breakReceived = '0' then
-- scancode processing
if scancode = "11110000" then
-- mark break for next scancode
breakReceived <= '1';
end if;
if scancode = keyboardA then
LeftPaddleDirection <= -1;
elsif scancode = keyboardY then
LeftPaddleDirection <= 1;
elsif scancode = keyboardK then
RightPaddleDirection <= -1;
elsif scancode = keyboardM then
RightPaddleDirection <= 1;
end if;
end if;
end if;
end process scan_keyboard;
end Behavioral;
|
-- $Id: tb_w11a_b3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_b3
-- Description: Configuration for tb_w11a_b3 for tb_basys3
--
-- Dependencies: sys_w11a_b3
--
-- To test: sys_w11a_b3
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-21 649 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_w11a_b3 of tb_basys3 is
for sim
for all : basys3_aif
use entity work.sys_w11a_b3;
end for;
end for;
end tb_w11a_b3;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity twi_master is
port (
rst : in std_logic;
clk : in std_logic;
-- Avalon-MM 32-bits slave
addr : in std_logic_vector(1 downto 0);
byte_en : in std_logic_vector(1 downto 0) := (others => '1');
in_data : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
out_data : out std_logic_vector(15 downto 0);
--
source_irq : in std_logic;
sink_irq : in std_logic;
irq : out std_logic;
-- DATA source
in_octet : in std_logic_vector(7 downto 0);
in_valid : in std_logic;
in_ready : out std_logic;
-- DATA sink
out_octet : out std_logic_vector(7 downto 0);
out_valid : out std_logic;
out_ready : in std_logic;
-- TWI bus (export)
scl_in : in std_logic;
scl_act : out std_logic;
sda_in : in std_logic;
sda_act : out std_logic
);
end entity;
architecture RTL of twi_master is
-- registers addresses
constant REG_PRESC : std_logic_vector(1 downto 0) := "00";
constant REG_INT_CTRLSTAT : std_logic_vector(1 downto 0) := "01";
constant REG_TWI_CTRL : std_logic_vector(1 downto 0) := "10";
constant REG_DATA_LEN : std_logic_vector(1 downto 0) := "11";
-- int control register bits
constant TWI_COMPL_MASK : natural := 0;
constant TWI_ANACK_MASK : natural := 1;
constant TWI_DNACK_MASK : natural := 2;
-- int status register bits
constant TWI_COMPL : natural := 8;
constant TWI_ANACK : natural := 9;
constant TWI_DNACK : natural := 10;
constant TWI_SOURCE_REQ : natural := 11;
constant TWI_SINK_REQ : natural := 12;
constant TWI_SDA_SENSE : natural := 14;
constant TWI_SCL_SENSE : natural := 15;
-- TWI control register bits
constant TWI_TRANSFER : natural := 8;
constant TWI_NOSTOP : natural := 9;
constant TWI_NOSTART : natural := 10;
constant TWI_SOFT_RESET : natural := 13;
constant TWI_SDA_OVERRIDE : natural := 14;
constant TWI_SCL_OVERRIDE : natural := 15;
signal int_ctrlstat_reg : std_logic_vector(15 downto 0);
signal twi_control_reg : std_logic_vector(15 downto 8);
signal presc_div : unsigned(15 downto 0);
signal compl_mask : std_logic;
signal anack_mask : std_logic;
signal dnack_mask : std_logic;
signal compl : std_logic;
signal anack : std_logic;
signal dnack : std_logic;
signal slave_addr : std_logic_vector(7 downto 0);
signal transfer : std_logic;
signal nostop : std_logic;
signal nostart : std_logic;
signal sda_ovr : std_logic;
signal scl_ovr : std_logic;
signal scl_sen_meta : std_logic;
signal scl_sen : std_logic;
signal sda_sen_meta : std_logic;
signal sda_sen : std_logic;
signal data_len : unsigned(15 downto 0);
signal prescl_wren : std_logic;
signal presch_wren : std_logic;
signal int_ctrl_wren : std_logic;
signal int_stat_wren : std_logic;
signal twi_ctrl_wren : std_logic;
signal slave_addr_wren : std_logic;
signal dlenl_wren : std_logic;
signal dlenh_wren : std_logic;
signal soft_reset : std_logic;
signal start_transfer : std_logic;
signal end_transfer : std_logic;
signal presc_cntr : unsigned(15 downto 0);
signal tick_en : std_logic;
signal phase_tick_en : std_logic;
signal bit_tick_en : std_logic;
signal symbol_tick_en : std_logic;
signal state_tick_en : std_logic;
signal scl_tick_en : std_logic;
signal symbol_pending : std_logic;
signal bit_cntr_en : std_logic;
signal shift_reg : std_logic_vector(8 downto 0);
signal shift_reg_ld_addr : std_logic;
signal shift_reg_ld_data : std_logic;
signal shift_reg_ld_dummy : std_logic;
signal shift_reg_ack_bit : std_logic;
signal bit_phase : unsigned(1 downto 0);
signal bit_cntr : unsigned(3 downto 0);
type twi_state_t is (twi_st_idle, twi_st_start, twi_st_addr, twi_st_data, twi_st_stop, twi_st_end);
signal twi_state : twi_state_t;
signal twi_next_state : twi_state_t;
signal slave_nack : std_logic;
signal anack_i : std_logic;
signal dnack_i : std_logic;
signal scl_i : std_logic;
signal sda_i : std_logic;
signal in_ready_i : std_logic;
signal out_valid_i : std_logic;
signal in_stall : std_logic;
signal out_stall : std_logic;
begin
int_ctrlstat_reg <= (
TWI_COMPL_MASK => compl_mask,
TWI_ANACK_MASK => anack_mask,
TWI_DNACK_MASK => dnack_mask,
--
TWI_COMPL => compl,
TWI_ANACK => anack,
TWI_DNACK => dnack,
TWI_SOURCE_REQ => source_irq,
TWI_SINK_REQ => sink_irq,
TWI_SDA_SENSE => not sda_sen,
TWI_SCL_SENSE => not scl_sen,
--
others => '0'
);
twi_control_reg <= (
TWI_SCL_OVERRIDE => scl_ovr,
TWI_SDA_OVERRIDE => sda_ovr,
TWI_NOSTOP => nostop,
TWI_NOSTART => nostart,
TWI_TRANSFER => transfer,
--
others => '0'
);
with addr select
out_data <= std_logic_vector(presc_div) when REG_PRESC,
int_ctrlstat_reg when REG_INT_CTRLSTAT,
twi_control_reg & slave_addr when REG_TWI_CTRL,
std_logic_vector(data_len) when REG_DATA_LEN,
(others => '0') when others;
prescl_wren <= wr_en and byte_en(0) and not transfer when addr = REG_PRESC else '0';
presch_wren <= wr_en and byte_en(1) and not transfer when addr = REG_PRESC else '0';
int_ctrl_wren <= wr_en and byte_en(0) when addr = REG_INT_CTRLSTAT else '0';
int_stat_wren <= wr_en and byte_en(1) when addr = REG_INT_CTRLSTAT else '0';
slave_addr_wren <= wr_en and byte_en(0) and not transfer when addr = REG_TWI_CTRL else '0';
twi_ctrl_wren <= wr_en and byte_en(1) when addr = REG_TWI_CTRL else '0';
dlenl_wren <= wr_en and byte_en(0) when addr = REG_DATA_LEN else '0';
dlenh_wren <= wr_en and byte_en(1) when addr = REG_DATA_LEN else '0';
soft_reset <= twi_ctrl_wren and in_data(TWI_SOFT_RESET);
start_transfer <= twi_ctrl_wren and in_data(TWI_TRANSFER) and not transfer;
tick_en <= '1' when presc_div = presc_cntr else '0';
process (rst, clk)
begin
if rising_edge(clk) then
-- resync input pins
scl_sen_meta <= scl_in;
scl_sen <= scl_sen_meta;
sda_sen_meta <= sda_in;
sda_sen <= sda_sen_meta;
-- clock divider register
if prescl_wren = '1' then
presc_div(7 downto 0) <= unsigned(in_data(7 downto 0));
end if;
if presch_wren = '1' then
presc_div(15 downto 8) <= unsigned(in_data(15 downto 8));
end if;
-- slave address register
if slave_addr_wren = '1' then
slave_addr <= in_data(7 downto 0);
end if;
-- TWI control register
if twi_ctrl_wren = '1' then
scl_ovr <= in_data(TWI_SCL_OVERRIDE);
sda_ovr <= in_data(TWI_SDA_OVERRIDE);
end if;
if (twi_ctrl_wren and not transfer) = '1' then
nostop <= in_data(TWI_NOSTOP);
nostart <= in_data(TWI_NOSTART);
end if;
if (soft_reset or end_transfer) = '1' then
transfer <= '0';
elsif start_transfer = '1' then
transfer <= '1';
end if;
-- int control register
if int_ctrl_wren = '1' then
compl_mask <= in_data(TWI_COMPL_MASK);
anack_mask <= in_data(TWI_ANACK_MASK);
dnack_mask <= in_data(TWI_DNACK_MASK);
end if;
-- int status register
if ((int_stat_wren and in_data(TWI_COMPL)) or start_transfer or soft_reset) = '1' then
compl <= '0';
elsif end_transfer = '1' then
compl <= anack_i nor dnack_i;
end if;
if ((int_stat_wren and in_data(TWI_ANACK)) or start_transfer or soft_reset) = '1' then
anack <= '0';
elsif end_transfer = '1' then
anack <= anack_i;
end if;
if ((int_stat_wren and in_data(TWI_DNACK)) or start_transfer or soft_reset) = '1' then
dnack <= '0';
elsif end_transfer = '1' then
dnack <= dnack_i;
end if;
-- data length register
if (transfer and (shift_reg_ld_data or shift_reg_ld_dummy)) = '1' then
data_len <= data_len - 1;
else
if dlenl_wren = '1' then
data_len(7 downto 0) <= unsigned(in_data(7 downto 0));
end if;
if dlenh_wren = '1' then
data_len(15 downto 8) <= unsigned(in_data(15 downto 8));
end if;
end if;
-- clock_processing
if (tick_en or prescl_wren or presch_wren) = '1' then
presc_cntr <= (others => '0');
else
presc_cntr <= presc_cntr + 1;
end if;
end if;
if rst = '1' then
scl_sen_meta <= '0';
scl_sen <= '0';
sda_sen_meta <= '0';
sda_sen <= '0';
scl_ovr <= '0';
sda_ovr <= '0';
transfer <= '0';
nostart <= '0';
nostop <= '0';
compl <= '0';
anack <= '0';
dnack <= '0';
compl_mask <= '0';
anack_mask <= '0';
dnack_mask <= '0';
data_len <= (others => '0');
presc_div <= (others => '0');
presc_cntr <= (others => '0');
slave_addr <= (others => '0');
end if;
end process;
slave_nack <= (sda_sen and symbol_tick_en) when twi_state = twi_st_addr else (sda_sen and symbol_tick_en and not slave_addr(0));
shift_reg_ld_addr <= bit_tick_en when twi_state = twi_st_start else '0';
shift_reg_ld_data <= state_tick_en and not slave_addr(0) and in_valid when twi_next_state = twi_st_data else '0';
shift_reg_ld_dummy <= state_tick_en and slave_addr(0) when twi_next_state = twi_st_data else '0';
shift_reg_ack_bit <= not nostop when data_len = 1 else '0';
in_ready_i <= tick_en and not slave_addr(0) when bit_phase = 0 and bit_cntr = 8 and data_len /= 0 else '0';
out_stall <= out_valid_i and not out_ready;
in_stall <= in_ready_i and not in_valid;
phase_tick_en <= tick_en and (out_stall nor in_stall) when bit_phase /= 3 or scl_sen = '1' else '0';
bit_tick_en <= phase_tick_en when bit_phase = 0 else '0';
symbol_tick_en <= bit_tick_en when bit_cntr = 8 else '0';
with twi_state select
state_tick_en <= bit_tick_en when twi_st_idle | twi_st_start | twi_st_stop,
symbol_tick_en when twi_st_addr | twi_st_data,
'0' when others;
scl_tick_en <= '0' when bit_phase = 1 else phase_tick_en;
bit_cntr_en <= bit_tick_en when twi_state = twi_st_addr or twi_state = twi_st_data else '0';
symbol_pending <= slave_addr(0) and bit_tick_en when twi_state = twi_st_data and bit_cntr = 7 else '0';
end_transfer <= phase_tick_en when twi_state = twi_st_end else '0';
process (rst, transfer, clk)
begin
if rising_edge(clk) then
-- upstream state machine
if (out_valid_i and out_ready) = '1' then
out_valid_i <= '0';
elsif symbol_pending = '1' then
out_valid_i <= '1';
end if;
-- bit phase processing
if phase_tick_en = '1' then
bit_phase <= bit_phase + 1;
end if;
-- SDA state machine
if soft_reset = '1' then
sda_i <= '0';
elsif phase_tick_en = '1' then
case twi_state is
when twi_st_start =>
sda_i <= bit_phase(0) xnor bit_phase(1);
when twi_st_data | twi_st_addr =>
sda_i <= not shift_reg(8);
when twi_st_stop =>
sda_i <= bit_phase(0) xor bit_phase(1);
when others =>
null;
end case;
end if;
-- SCL state machine
if soft_reset = '1' then
scl_i <= '0';
elsif scl_tick_en = '1' then
case twi_state is
when twi_st_start | twi_st_addr | twi_st_data =>
scl_i <= not bit_phase(1);
when twi_st_stop =>
scl_i <= '0';
when others =>
null;
end case;
end if;
-- bit counter
if bit_cntr_en = '1' then
if symbol_tick_en = '1' then
bit_cntr <= (others => '0');
else
bit_cntr <= bit_cntr + 1;
end if;
end if;
-- TWI state machine
if state_tick_en = '1' then
twi_state <= twi_next_state;
end if;
-- shift register process
if shift_reg_ld_addr = '1' then -- load shift register with slave address
shift_reg <= slave_addr & '1';
elsif shift_reg_ld_data = '1' then -- load shift register with next data octet
shift_reg <= in_octet & '1';
elsif shift_reg_ld_dummy = '1' then -- load shift register with dummy value
shift_reg <= (0 => shift_reg_ack_bit, others => '1');
elsif bit_tick_en = '1' then -- shift register and load next bit
shift_reg <= shift_reg(7 downto 0) & sda_sen;
end if;
-- remember ack bit
if symbol_tick_en = '1' and twi_state = twi_st_addr then
anack_i <= sda_sen;
end if;
if symbol_tick_en = '1' and twi_state = twi_st_data then
dnack_i <= sda_sen and not slave_addr(0);
end if;
end if;
if transfer = '0' then
twi_state <= twi_st_idle;
out_valid_i <= '0';
anack_i <= '0';
dnack_i <= '0';
bit_phase <= (others => '0');
bit_cntr <= (others => '0');
shift_reg <= (others => '0');
end if;
if rst = '1' then
scl_i <= '0';
sda_i <= '0';
end if;
end process;
twi_next_state <= twi_st_start when twi_state = twi_st_idle and nostart = '0' else
twi_st_addr when twi_state = twi_st_start else
twi_st_data when twi_state /= twi_st_stop and data_len /= 0 and slave_nack = '0' else
twi_st_stop when twi_state /= twi_st_stop and twi_state /= twi_st_end and nostop = '0' else
twi_st_end;
scl_act <= scl_i or scl_ovr;
sda_act <= sda_i or scl_ovr;
in_ready <= in_ready_i;
out_valid <= out_valid_i;
out_octet <= shift_reg(7 downto 0);
irq <= source_irq or sink_irq or (compl and compl_mask) or (anack and anack_mask) or (dnack and dnack_mask);
end architecture;
|
entity array5 is
end entity;
architecture test of array5 is
type int_vec is array (integer range <>) of integer;
procedure negative_range (x : out int_vec;
y : in int_vec) is
begin
x(0 downto -x'length + 1) := y;
end procedure;
begin
main: process is
variable a : int_vec(0 downto -3);
variable b : int_vec(0 to 3);
begin
b := (1, 2, 3, 4);
negative_range(a, b);
assert a = (1, 2, 3, 4);
wait;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: EventMem
-- Date:2011-11-11
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity EventMem is
port (
reset : std_logic;
-- event occured
occured : in std_logic;
-- event approved
approved : in std_logic;
-- output
output : out std_logic
);
end EventMem;
architecture arch of EventMem is
begin
process(reset, occured, approved) begin
if reset = '1' or approved = '1' then
output <= '0';
elsif rising_edge(occured) then
output <= '1';
end if;
end process;
end arch;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity AtomVGAWing is
Port (
clock32 : in std_logic;
rst : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (1 downto 0);
hsync : out std_logic;
vsync : out std_logic;
clamp : out std_logic;
led : out std_logic_vector (4 downto 1);
test : out std_logic_vector (6 downto 1);
switch : in std_logic_vector (8 downto 1);
unused : in std_logic;
AL_P : in std_logic;
AL_N : in std_logic;
AH_P : in std_logic;
AH_N : in std_logic;
BL_P : in std_logic;
BL_N : in std_logic;
BH_P : in std_logic;
BH_N : in std_logic;
LUM_P : in std_logic;
LUM_N : in std_logic;
HS_N : in std_logic;
FS_N : in std_logic
);
end;
architecture Behavioral of AtomVGAWing is
constant atomClampStart : unsigned(10 downto 0) := to_unsigned(2048 - 59 * 4 - 110, 11);
constant atomClampEnd : unsigned(10 downto 0) := to_unsigned(2048 - 59 * 4 - 10, 11);
constant atomhInit : unsigned(10 downto 0) := to_unsigned(2048 - 370, 11);
constant atomvInit : unsigned(8 downto 0) := to_unsigned(512 - 39, 9);
constant atomhBorder : unsigned(10 downto 0) := to_unsigned(2048 - 16 + 3, 11);
constant atomvBorder : unsigned(8 downto 0) := to_unsigned(512 - 25, 11);
signal atomhCounter : unsigned(10 downto 0) := (others => '0');
signal atomvCounter : unsigned(8 downto 0) := (others => '0');
signal AL0: std_logic;
signal AL1: std_logic;
signal AL2: std_logic;
signal AL3: std_logic;
signal AL4: std_logic;
signal AL5: std_logic;
signal AH0: std_logic;
signal AH1: std_logic;
signal AH2: std_logic;
signal AH3: std_logic;
signal AH4: std_logic;
signal AH5: std_logic;
signal BL0: std_logic;
signal BL1: std_logic;
signal BL2: std_logic;
signal BL3: std_logic;
signal BL4: std_logic;
signal BL5: std_logic;
signal BH0: std_logic;
signal BH1: std_logic;
signal BH2: std_logic;
signal BH3: std_logic;
signal BH4: std_logic;
signal BH5: std_logic;
signal L0: std_logic;
signal L1: std_logic;
signal L2: std_logic;
signal L3: std_logic;
signal L4: std_logic;
signal L5: std_logic;
signal AL: std_logic;
signal AH: std_logic;
signal BL: std_logic;
signal BH: std_logic;
signal L: std_logic;
signal R: std_logic;
signal G1: std_logic;
signal G2: std_logic;
signal B: std_logic;
signal atomhSync0: std_logic := '0';
signal atomhSync1: std_logic := '0';
signal atomhSync2: std_logic := '0';
signal atomhSync3: std_logic := '0';
signal atomhSync4: std_logic := '0';
signal atomhSync5: std_logic := '0';
signal atomvSync0: std_logic := '0';
signal atomvSync1: std_logic := '0';
signal atomvSync2: std_logic := '0';
signal atomvSync3: std_logic := '0';
signal atomvSync4: std_logic := '0';
signal atomvSync5: std_logic := '0';
signal atomhSync: std_logic := '0';
signal atomvSync: std_logic := '0';
signal atomvSyncToggle: std_logic := '0';
signal atomhSyncToggle: std_logic := '0';
signal clock32out : std_logic;
signal pixelClock : std_logic;
signal atomClock : std_logic;
signal tmpClock : std_logic;
signal tmpVgaClock : std_logic;
signal lockeda1 : std_logic;
signal lockeda2 : std_logic;
signal lockedb1 : std_logic;
signal lockedb2 : std_logic;
signal ramWE : std_logic := '0';
signal ramAddrA : std_logic_vector (15 downto 0) := (others => '0');
signal ramAddrB : std_logic_vector (15 downto 0) := (others => '0');
signal ramDataIn : std_logic_vector (3 downto 0) := (others => '0');
signal ramDataOut : std_logic_vector (3 downto 0) := (others => '0');
signal border : std_logic_vector (3 downto 0) := (others => '0');
signal hCounter : unsigned(10 downto 0):= (others => '0');
signal vCounter : unsigned(9 downto 0) := (others => '0');
signal hCounter1 : unsigned(10 downto 0):= (others => '0');
signal vCounter1 : unsigned(9 downto 0) := (others => '0');
-- VGA Timing constants
constant hMaxCount : natural := 800;
constant hStartData : natural := 0;
constant hEndData : natural := 512;
constant hStartBlank : natural := 576;
constant hStartSync : natural := 592;
constant hEndSync : natural := 688;
constant hEndBlank : natural := 736;
constant vMaxCount : natural := 524;
constant vStartData : natural := 0;
constant vEndData : natural := 384;
constant vStartBlank : natural := 432;
constant vStartSync : natural := 444;
constant vEndSync : natural := 446;
constant vEndBlank : natural := 476;
begin
led(1) <= NOT lockeda1;
led(2) <= NOT lockeda2;
led(3) <= NOT lockedb1;
led(4) <= NOT lockedb2;
test(1) <= atomClock;
test(2) <= atomhSync;
test(3) <= unused;
test(4) <= rst;
test(5) <= atomhSyncToggle;
test(6) <= atomvSyncToggle;
BUFG_1 : BUFG port map (
O => clock32out,
I => clock32
);
Inst_DCM_A: entity work.DCM_A port map (
CLKIN_IN => clock32out,
CLKFX_OUT => tmpVgaClock,
LOCKED_OUT => lockeda1
);
Inst_DCM_A2: entity work.DCM_A2 port map (
CLKIN_IN => tmpVgaClock,
RST_IN => NOT lockeda1,
CLKFX_OUT => pixelClock,
LOCKED_OUT => lockeda2
);
Inst_DCM_B: entity work.DCM_B port map (
CLKIN_IN => clock32out,
CLKFX_OUT => tmpClock,
LOCKED_OUT => lockedb1
);
Inst_DCM_C: entity work.DCM_C port map (
CLKIN_IN => tmpClock,
RST_IN => NOT lockedb1,
CLKFX_OUT => atomClock,
LOCKED_OUT => lockedb2
);
Inst_VideoRam: entity work.VideoRam port map (
clka => atomClock,
wea => ramWE,
addra => ramAddrA,
dina => ramDataIn,
clkb => pixelClock,
addrb => ramAddrB,
doutb => ramDataOut
);
IBUFDS_1 : IBUFDS port map (
O => AL0, -- Buffer output
I => AL_P, -- Diff_p buffer input (connect directly to top-level port)
IB => AL_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_2 : IBUFDS port map (
O => AH0, -- Buffer output
I => AH_P, -- Diff_p buffer input (connect directly to top-level port)
IB => AH_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_3 : IBUFDS port map (
O => BL0, -- Buffer output
I => BL_P, -- Diff_p buffer input (connect directly to top-level port)
IB => BL_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_4 : IBUFDS port map (
O => BH0, -- Buffer output
I => BH_P, -- Diff_p buffer input (connect directly to top-level port)
IB => BH_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_5 : IBUFDS port map (
O => L0, -- Buffer output
I => LUM_P, -- Diff_p buffer input (connect directly to top-level port)
IB => LUM_N -- Diff_n buffer input (connect directly to top-level port)
);
process(atomClock)
begin
if rising_edge(atomClock) then
AL1 <= AL0;
AH1 <= AH0;
BL1 <= BL0;
BH1 <= BH0;
AL2 <= AL1;
AH2 <= AH1;
BL2 <= BL1;
BH2 <= BH1;
AL3 <= AL2;
AH3 <= AH2;
BL3 <= BL2;
BH3 <= BH2;
AL4 <= (AL1 AND AL2) OR (AL1 AND AL3) OR (AL2 AND AL3);
AH4 <= (AH1 AND AH2) OR (AH1 AND AH3) OR (AH2 AND AH3);
BL4 <= (BL1 AND BL2) OR (BL1 AND BL3) OR (BL2 AND BL3);
BH4 <= (BH1 AND BH2) OR (BH1 AND BH3) OR (BH2 AND BH3);
if (atomhcounter(2 downto 0) = unsigned(switch(7 downto 5))) then
AL5 <= AL4;
AH5 <= AH4;
BL5 <= BL4;
BH5 <= BH4;
end if;
L1 <= L0;
L2 <= L1;
L3 <= L2;
L4 <= (L1 AND L2) OR (L1 AND L3) OR (L2 AND L3);
if (atomhcounter(1 downto 0) = unsigned(switch(4 downto 3))) then
L5 <= L4;
end if;
AL <= AL5;
AH <= AH5;
BL <= BL5;
BH <= BH5;
L <= L5;
-- AL AH BL BH L R G1 G2 B
--YELLOW 1.5 1.0 0 0 1 0 X 1 1 1 0
--RED 2.0 1.5 0 1 0 0 X 1 0 1 0
--MAGENTA 2.0 2.0 0 1 0 1 X 1 0 1 1
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
R <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L) OR (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--YELLOW 1.5 1.0 0 0 1 0 X 1 1 1 0
--CYAN 1.0 1.5 1 0 0 0 X 0 1 1 1
--GREEN 1.0 1.0 1 0 1 0 1 0 1 1 0
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
G1 <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (AL AND NOT AH AND BL AND NOT BH AND L) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L) OR (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
G2 <= NOT (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--BLUE 1.5 2.0 0 0 0 1 X 0 0 1 1
--CYAN 1.0 1.5 1 0 0 0 X 0 1 1 1
--MAGENTA 2.0 2.0 0 1 0 1 X 1 0 1 1
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
B <= (NOT AL AND NOT AH AND NOT BL AND BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L);
ramDataIn <= R & G1 & G2 & B;
-- generate a 1 clock hSync signal from the falling edge of sync
atomhSync0 <= HS_N;
atomhSync1 <= NOT atomhSync0;
atomhSync2 <= atomhSync1;
atomhSync3 <= atomhSync2;
atomhSync4 <= atomhSync3;
atomhSync5 <= atomhSync4;
atomvSync0 <= FS_N;
atomvSync1 <= NOT atomvSync0;
atomvSync2 <= atomvSync1;
atomvSync3 <= atomvSync2;
atomvSync4 <= atomvSync3;
atomvSync5 <= atomvSync4;
if atomhSync5 = '1' AND atomhSync4 = '1' AND atomhSync3 = '0' AND atomhSync2 = '0' then
atomhSync <= '1';
else
atomhSync <= '0';
end if;
if atomvSync5 = '1' AND atomvSync4 = '1' AND atomvSync3 = '0' AND atomvSync2 = '0' then
atomvSync <= '1';
else
atomvSync <= '0';
end if;
-- generate
if (atomvSync = '1') then
atomvCounter <= atomvInit;
atomvSyncToggle <= NOT atomvSyncToggle;
elsif (atomhSync = '1') then
atomvCounter <= atomvCounter+1;
end if;
if (atomhSync = '1') then
atomhCounter <= atomhInit;
atomhSyncToggle <= NOT atomhSyncToggle;
else
atomhCounter <= atomhCounter+1;
end if;
ramAddrA <= std_logic_vector(atomvCounter(7 downto 0)) & std_logic_vector(atomhcounter(9 downto 2));
if (atomhcounter(1 downto 0) = unsigned(switch(2 downto 1)) AND atomhCounter < 1024 AND atomvCounter < 192) then
ramWE <= '1';
else
ramWE <= '0';
end if;
if (atomhcounter >= atomClampStart AND atomhCounter < atomClampEnd) then
clamp <= '1';
else
clamp <= '0';
end if;
if (atomhCounter = atomhBorder AND (switch(8) = '1' OR atomvCounter = atomvBorder)) then
border <= ramDataIn;
end if;
end if;
end process;
ramAddrB <= std_logic_vector(vCounter(8 downto 1)) & std_logic_vector(hcounter(8 downto 1));
process(pixelClock)
begin
if rising_edge(pixelClock) then
hsync <= '0';
vsync <= '0';
hCounter1 <= hCounter;
vCounter1 <= vCounter;
if (hCounter1 >= hStartData AND hCounter1 < hEndData AND vCounter1 >= vStartData AND vCounter1 < vEndData) then
red <= ramDataOut(3) & ramDataOut(3) & ramDataOut(3);
green <= ramDataOut(2) & (ramDataOut(2) AND ramDataOut(1)) & (ramDataOut(2) AND ramDataOut(1));
blue <= ramDataOut(0) & ramDataOut(0);
elsif (hCounter1 >= hStartBlank AND hCounter1 < hEndBlank) OR (vCounter1 >= vStartBlank AND vCounter1 < vEndBlank) then
red <= "000";
green <= "000";
blue <= "00";
else
red <= border(3) & border(3) & border(3);
green <= border(2) & (border(2) AND border(1)) & (border(2) AND border(1));
blue <= border(0) & border(0);
end if;
-- Count the lines and rows
if hCounter = (hMaxCount - 1) then
hCounter <= (others => '0');
if (vCounter = vMaxCount - 1) then
vCounter <= (others => '0');
else
vCounter <= vCounter+1;
end if;
else
hCounter <= hCounter+1;
end if;
-- Are we in the hSync pulse?
if hCounter >= hStartSync and hCounter < hEndSync then
hSync <= '1'; -- Positive hSync pulse
end if;
-- Are we in the vSync pulse?
if vCounter >= vStartSync and vCounter < vEndSync then
vSync <= '1'; -- Positive vSync pulse
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ae
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ae-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_ae-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ae_rtl_conf / ent_ae
--
configuration ent_ae_rtl_conf of ent_ae is
for rtl
-- Generated Configuration
end for;
end ent_ae_rtl_conf;
--
-- End of Generated Configuration ent_ae_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY somador_tb IS
GENERIC (DATA_WIDTH : natural := 32);
END somador_tb;
ARCHITECTURE somador_arch OF somador_tb IS
COMPONENT somador --componente que sera testado
port (dataIn1, dataIn2 : in std_logic_vector (DATA_WIDTH - 1 downto 0);
dataOut : out std_logic_vector (DATA_WIDTH - 1 downto 0));
END COMPONENT;
SIGNAL ent1, ent2, saida : std_logic_vector (DATA_WIDTH - 1 downto 0) := (others => '0');
BEGIN
SomadorTB : somador PORT MAP (ent1, ent2, saida);
Stimulus : PROCESS
BEGIN
wait for 5 ns;
ent1 <= x"00000000000000000000000000000101";
ent2 <= x"00000000000000000000000000000101";
wait for 10 ns;
ent1 <= x"00000000000000000000000000000101";
ent2 <= x"00000000000000000000000000001010";
wait for 10 ns;
ent1 <= x"00000000000000000000000000011001";
ent2 <= x"00000000000000000000000001001001";
wait for 10 ns;
ent1 <= x"00000000000010000000000000011001";
ent2 <= x"00000000000010000000000001001001";
END PROCESS Stimulus;
END somador_arch; --fim do testbench |
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY somador_tb IS
GENERIC (DATA_WIDTH : natural := 32);
END somador_tb;
ARCHITECTURE somador_arch OF somador_tb IS
COMPONENT somador --componente que sera testado
port (dataIn1, dataIn2 : in std_logic_vector (DATA_WIDTH - 1 downto 0);
dataOut : out std_logic_vector (DATA_WIDTH - 1 downto 0));
END COMPONENT;
SIGNAL ent1, ent2, saida : std_logic_vector (DATA_WIDTH - 1 downto 0) := (others => '0');
BEGIN
SomadorTB : somador PORT MAP (ent1, ent2, saida);
Stimulus : PROCESS
BEGIN
wait for 5 ns;
ent1 <= x"00000000000000000000000000000101";
ent2 <= x"00000000000000000000000000000101";
wait for 10 ns;
ent1 <= x"00000000000000000000000000000101";
ent2 <= x"00000000000000000000000000001010";
wait for 10 ns;
ent1 <= x"00000000000000000000000000011001";
ent2 <= x"00000000000000000000000001001001";
wait for 10 ns;
ent1 <= x"00000000000010000000000000011001";
ent2 <= x"00000000000010000000000001001001";
END PROCESS Stimulus;
END somador_arch; --fim do testbench |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMU5M7DX7 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMU5M7DX7 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 16,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMU5M7DX7 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMU5M7DX7 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 16,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMU5M7DX7 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMU5M7DX7 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 16,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMU5M7DX7 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMU5M7DX7 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 16,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity arr04 is
port (clk : in std_logic;
rst : std_logic;
sel_i : std_logic;
sel_o : std_logic;
v : std_logic;
res : out std_logic);
end arr04;
architecture behav of arr04 is
signal reg : std_logic_vector (0 to 1);
begin
-- Reader
process(clk)
begin
if rising_edge (clk) then
if sel_o = '0' then
res <= reg (0);
else
res <= reg (1);
end if;
end if;
end process;
-- Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg <= "00";
else
if sel_i = '0' then
reg (0) <= v;
else
reg (1) <= v;
end if;
end if;
end if;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- axi_vdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI VDMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
package axi_vdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer;
-- CALCULATE mm2s_tdata_width for axi_vdma
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer;
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth: integer)
return integer;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth: integer)
return integer;
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Converts string to interger
function string2int(strngbuf: string)
return integer;
-- Return number of registers
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return enable genlock bus
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL_SG : integer := 62;
constant NUM_REG_TOTAL_REGDIR : integer := 62;
----constant NUM_REG_TOTAL_SG : integer := 20;
----constant NUM_REG_TOTAL_REGDIR : integer := 59;
--constant NUM_REG_TOTAL_REGDIR : integer := 156;
--constant NUM_REG_TOTAL_REGDIR : integer := 123;
constant NUM_REG_PER_CHANNEL : integer := 8;
constant NUM_DIRECT_REG_PER_CHANNEL : integer := 19;
--constant NUM_DIRECT_REG_PER_CHANNEL : integer := 67;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Clock Domain Crossing Constants
constant CDC_TYPE_PULSE_P_S : integer := 0;
constant CDC_TYPE_LEVEL_P_S : integer := 1;
constant CDC_TYPE_PULSE_S_P : integer := 2;
constant CDC_TYPE_LEVEL_S_P : integer := 3;
constant CDC_TYPE_VECTR_P_S : integer := 4;
constant CDC_TYPE_VECTR_S_P : integer := 5;
constant CDC_TYPE_PULSE_P_S_NO_RST : integer := 6;
constant CDC_TYPE_LEVEL_P_S_NO_RST : integer := 7;
constant CDC_TYPE_PULSE_S_P_NO_RST : integer := 8;
constant CDC_TYPE_LEVEL_S_P_NO_RST : integer := 9;
constant CDC_TYPE_PULSE_P_S_LL : integer := 10;
constant CDC_TYPE_PULSE_S_P_LL : integer := 11;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED : integer := 12;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED : integer := 13;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST : integer := 14;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST : integer := 15;
constant MTBF_STAGES : integer := 4;
constant MTBF_STAGES_LITE : integer := 3;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Frame Store
constant NUM_FRM_STORE_WIDTH : integer := 6;
constant FRAME_NUMBER_WIDTH : integer := NUM_FRM_STORE_WIDTH - 1;
constant ZERO_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
constant ONE_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH));
constant MAX_FSTORES : integer := 32;
-- Line Buffer
constant LINEBUFFER_THRESH_WIDTH : integer := 17;
-- Video parameter constants
constant VSIZE_DWIDTH : integer := 13;
constant HSIZE_DWIDTH : integer := 16;
constant STRIDE_DWIDTH : integer := 16;
constant FRMDLY_DWIDTH : integer := FRAME_NUMBER_WIDTH;
constant FRMDLY_MSB : integer := 28;
constant FRMDLY_LSB : integer := 24;
constant RSVD_BITS_31TO29 : std_logic_vector(2 downto 0) := (others => '0');
constant RSVD_BITS_23TO16 : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_REG_IND : integer := 5;
constant MM2S_FRAME_STORE_INDEX : integer := 6;
constant MM2S_THRESHOLD_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant VDMA_GLPTR_INDEX : integer := 9;
constant VDMA_PARKPTR_INDEX : integer := 10;
constant VDMA_VERISON_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_DMA_IRQ_MASK : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_REG_IND : integer := 17;
constant S2MM_FRAME_STORE_INDEX : integer := 18;
constant S2MM_THRESHOLD_INDEX : integer := 19;
-- Register direct
constant MM2S_VSIZE_INDEX : integer := 20;
constant MM2S_HSIZE_INDEX : integer := 21;
constant MM2S_DLYSTRD_INDEX : integer := 22;
constant MM2S_STARTADDR1_INDEX : integer := 23;
constant MM2S_STARTADDR2_INDEX : integer := 24;
constant MM2S_STARTADDR3_INDEX : integer := 25;
constant MM2S_STARTADDR4_INDEX : integer := 26;
constant MM2S_STARTADDR5_INDEX : integer := 27;
constant MM2S_STARTADDR6_INDEX : integer := 28;
constant MM2S_STARTADDR7_INDEX : integer := 29;
constant MM2S_STARTADDR8_INDEX : integer := 30;
constant MM2S_STARTADDR9_INDEX : integer := 31;
constant MM2S_STARTADDR10_INDEX : integer := 32;
constant MM2S_STARTADDR11_INDEX : integer := 33;
constant MM2S_STARTADDR12_INDEX : integer := 34;
constant MM2S_STARTADDR13_INDEX : integer := 35;
constant MM2S_STARTADDR14_INDEX : integer := 36;
constant MM2S_STARTADDR15_INDEX : integer := 37;
constant MM2S_STARTADDR16_INDEX : integer := 38;
constant RESERVED_9C_INDEX : integer := 39;
constant S2MM_VSIZE_INDEX : integer := 40;
constant S2MM_HSIZE_INDEX : integer := 41;
constant S2MM_DLYSTRD_INDEX : integer := 42;
constant S2MM_STARTADDR1_INDEX : integer := 43;
constant S2MM_STARTADDR2_INDEX : integer := 44;
constant S2MM_STARTADDR3_INDEX : integer := 45;
constant S2MM_STARTADDR4_INDEX : integer := 46;
constant S2MM_STARTADDR5_INDEX : integer := 47;
constant S2MM_STARTADDR6_INDEX : integer := 48;
constant S2MM_STARTADDR7_INDEX : integer := 49;
constant S2MM_STARTADDR8_INDEX : integer := 50;
constant S2MM_STARTADDR9_INDEX : integer := 51;
constant S2MM_STARTADDR10_INDEX : integer := 52;
constant S2MM_STARTADDR11_INDEX : integer := 53;
constant S2MM_STARTADDR12_INDEX : integer := 54;
constant S2MM_STARTADDR13_INDEX : integer := 55;
constant S2MM_STARTADDR14_INDEX : integer := 56;
constant S2MM_STARTADDR15_INDEX : integer := 57;
constant S2MM_STARTADDR16_INDEX : integer := 58;
constant RESERVED_EC_INDEX : integer := 59;
--constant RESERVED_F0_INDEX : integer := 60;
constant HSIZE_AT_LLESS_ERR_F0_INDEX : integer := 60;
--constant RESERVED_F4_INDEX : integer := 61;
constant VSIZE_AT_FLESS_ERR_F4_INDEX : integer := 61;
constant RESERVED_F8_INDEX : integer := 62;
constant RESERVED_FC_INDEX : integer := 63;
constant RESERVED_100_INDEX : integer := 64;
constant RESERVED_104_INDEX : integer := 65;
constant RESERVED_108_INDEX : integer := 66;
constant RESERVED_10C_INDEX : integer := 67;
constant RESERVED_110_INDEX : integer := 68;
constant RESERVED_114_INDEX : integer := 69;
constant RESERVED_118_INDEX : integer := 70;
constant RESERVED_11C_INDEX : integer := 71;
constant RESERVED_120_INDEX : integer := 72;
constant RESERVED_124_INDEX : integer := 73;
constant RESERVED_128_INDEX : integer := 74;
constant RESERVED_12C_INDEX : integer := 75;
constant RESERVED_130_INDEX : integer := 76;
constant RESERVED_134_INDEX : integer := 77;
constant RESERVED_138_INDEX : integer := 78;
constant RESERVED_13C_INDEX : integer := 79;
constant RESERVED_140_INDEX : integer := 80;
constant RESERVED_144_INDEX : integer := 81;
constant RESERVED_148_INDEX : integer := 82;
constant RESERVED_14C_INDEX : integer := 83;
constant RESERVED_150_INDEX : integer := 84;
constant RESERVED_154_INDEX : integer := 85;
constant RESERVED_158_INDEX : integer := 86;
constant MM2S_STARTADDR17_INDEX : integer := 87;
constant MM2S_STARTADDR18_INDEX : integer := 88;
constant MM2S_STARTADDR19_INDEX : integer := 89;
constant MM2S_STARTADDR20_INDEX : integer := 90;
constant MM2S_STARTADDR21_INDEX : integer := 91;
constant MM2S_STARTADDR22_INDEX : integer := 92;
constant MM2S_STARTADDR23_INDEX : integer := 93;
constant MM2S_STARTADDR24_INDEX : integer := 94;
constant MM2S_STARTADDR25_INDEX : integer := 95;
constant MM2S_STARTADDR26_INDEX : integer := 96;
constant MM2S_STARTADDR27_INDEX : integer := 97;
constant MM2S_STARTADDR28_INDEX : integer := 98;
constant MM2S_STARTADDR29_INDEX : integer := 99;
constant MM2S_STARTADDR30_INDEX : integer := 100;
constant MM2S_STARTADDR31_INDEX : integer := 101;
constant MM2S_STARTADDR32_INDEX : integer := 102;
constant RESERVED_19C_INDEX : integer := 103;
constant RESERVED_1A0_INDEX : integer := 104;
constant RESERVED_1A4_INDEX : integer := 105;
constant RESERVED_1A8_INDEX : integer := 106;
constant S2MM_STARTADDR17_INDEX : integer := 107;
constant S2MM_STARTADDR18_INDEX : integer := 108;
constant S2MM_STARTADDR19_INDEX : integer := 109;
constant S2MM_STARTADDR20_INDEX : integer := 110;
constant S2MM_STARTADDR21_INDEX : integer := 111;
constant S2MM_STARTADDR22_INDEX : integer := 112;
constant S2MM_STARTADDR23_INDEX : integer := 113;
constant S2MM_STARTADDR24_INDEX : integer := 114;
constant S2MM_STARTADDR25_INDEX : integer := 115;
constant S2MM_STARTADDR26_INDEX : integer := 116;
constant S2MM_STARTADDR27_INDEX : integer := 117;
constant S2MM_STARTADDR28_INDEX : integer := 118;
constant S2MM_STARTADDR29_INDEX : integer := 119;
constant S2MM_STARTADDR30_INDEX : integer := 120;
constant S2MM_STARTADDR31_INDEX : integer := 121;
constant S2MM_STARTADDR32_INDEX : integer := 122;
-- READ MUX Offsets
constant MM2S_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
-- }
constant MM2S_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_SG : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_SG : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant VDMA_PARK_PTRREF_OFFSET_SG : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_SG : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_8 : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_8 : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET_8 : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_8 : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000000"; -- 000
constant MM2S_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000100"; -- 004
constant MM2S_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001000"; -- 008
constant MM2S_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001100"; -- 00C
constant MM2S_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010000"; -- 010
constant MM2S_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 014
constant MM2S_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "000011000"; -- 018
constant MM2S_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "000011100"; -- 01C
constant RESERVED_20_OFFSET_90 : std_logic_vector(8 downto 0) := "000100000"; -- 020
constant RESERVED_24_OFFSET_90 : std_logic_vector(8 downto 0) := "000100100"; -- 024
constant VDMA_PARK_PTRREF_OFFSET_90 : std_logic_vector(8 downto 0) := "000101000"; -- 028
constant VDMA_VERSION_OFFSET_90 : std_logic_vector(8 downto 0) := "000101100"; -- 02C
constant S2MM_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110000"; -- 030
constant S2MM_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110100"; -- 034
constant S2MM_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111000"; -- 038
constant S2MM_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_DMA_IRQ_MASK_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000000"; -- 040
constant S2MM_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 044
constant S2MM_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "001001000"; -- 048
constant S2MM_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "001001100"; -- 04C
------
constant MM2S_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant MM2S_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant MM2S_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant MM2S_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant MM2S_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant MM2S_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant MM2S_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant MM2S_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_20_OFFSET_91 : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_24_OFFSET_91 : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant VDMA_PARK_PTRREF_OFFSET_91 : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant VDMA_VERSION_OFFSET_91 : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant S2MM_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant S2MM_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant S2MM_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant S2MM_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_DMA_IRQ_MASK_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant S2MM_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant S2MM_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant S2MM_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "101001100"; -- 14C
------
-------- Register direct READ MUX Offsets
constant MM2S_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010000"; -- 50
constant MM2S_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010100"; -- 54
constant MM2S_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "01011000"; -- 58
constant MM2S_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010000"; -- 050
constant MM2S_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "001011000"; -- 058
constant MM2S_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010000"; -- 050
constant MM2S_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "101011000"; -- 058
constant MM2S_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "01011100"; -- 5C
constant MM2S_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "01100000"; -- 60
constant MM2S_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "01100100"; -- 64
constant MM2S_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "01101000"; -- 68
constant MM2S_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "01101100"; -- 6C
constant MM2S_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "01110000"; -- 70
constant MM2S_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "01110100"; -- 74
constant MM2S_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "01111000"; -- 78
constant MM2S_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "01111100"; -- 7C
constant MM2S_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "10000000"; -- 80
constant MM2S_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "10000100"; -- 84
constant MM2S_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "10001000"; -- 88
constant MM2S_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "10001100"; -- 8C
constant MM2S_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "10010000"; -- 90
constant MM2S_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "10010100"; -- 94
constant MM2S_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "10011000"; -- 98
constant MM2S_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "001011100"; -- 05C
constant MM2S_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "001100000"; -- 060
constant MM2S_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "001100100"; -- 064
constant MM2S_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "001101000"; -- 068
constant MM2S_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "001101100"; -- 06C
constant MM2S_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "001110000"; -- 070
constant MM2S_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "001110100"; -- 074
constant MM2S_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "001111000"; -- 078
constant MM2S_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "001111100"; -- 07C
constant MM2S_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "010000000"; -- 080
constant MM2S_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "010000100"; -- 084
constant MM2S_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "010001000"; -- 088
constant MM2S_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "010001100"; -- 08C
constant MM2S_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "010010000"; -- 090
constant MM2S_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "010010100"; -- 094
constant MM2S_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "010011000"; -- 098
constant MM2S_STARTADDR1_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR2_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR3_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR4_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR5_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR6_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR7_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR8_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR9_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR10_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR11_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR12_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR13_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR14_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR15_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR16_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_9C_OFFSET_90 : std_logic_vector(8 downto 0) := "010011100"; -- 9C
constant S2MM_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100000"; -- A0
constant S2MM_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "10101000"; -- A8
constant S2MM_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100000"; -- A0
constant S2MM_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "010101000"; -- A8
constant S2MM_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100000"; -- A0
constant S2MM_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "110101000"; -- A8
constant S2MM_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "10101100"; -- AC
constant S2MM_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "10110000"; -- B0
constant S2MM_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "10110100"; -- B4
constant S2MM_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "10111000"; -- B8
constant S2MM_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "10111100"; -- BC
constant S2MM_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "11000000"; -- C0
constant S2MM_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "11000100"; -- C4
constant S2MM_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "11001000"; -- C8
constant S2MM_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "11001100"; -- CC
constant S2MM_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "11010000"; -- D0
constant S2MM_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "11010100"; -- D4
constant S2MM_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "11011000"; -- D8
constant S2MM_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "11011100"; -- DC
constant S2MM_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "11100000"; -- E0
constant S2MM_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "11100100"; -- E4
constant S2MM_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "11101000"; -- E8
constant S2MM_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "010101100"; -- 0AC
constant S2MM_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "010110000"; -- 0B0
constant S2MM_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "010110100"; -- 0B4
constant S2MM_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "010111000"; -- 0B8
constant S2MM_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "010111100"; -- 0BC
constant S2MM_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "011000000"; -- 0C0
constant S2MM_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "011000100"; -- 0C4
constant S2MM_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "011001000"; -- 0C8
constant S2MM_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "011001100"; -- 0CC
constant S2MM_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "011010000"; -- 0D0
constant S2MM_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "011010100"; -- 0D4
constant S2MM_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "011011000"; -- 0D8
constant S2MM_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "011011100"; -- 0DC
constant S2MM_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "011100000"; -- 0E0
constant S2MM_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "011100100"; -- 0E4
constant S2MM_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "011101000"; -- 0E8
constant RESERVED_EC_OFFSET : std_logic_vector(8 downto 0) := "011101100"; -- 0EC
constant RESERVED_F0_OFFSET : std_logic_vector(8 downto 0) := "011110000"; -- 0F0
constant RESERVED_F4_OFFSET : std_logic_vector(8 downto 0) := "011110100"; -- 0F4
constant RESERVED_F8_OFFSET : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
constant RESERVED_FC_OFFSET : std_logic_vector(8 downto 0) := "011111100"; -- 0FC
constant RESERVED_100_OFFSET : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant RESERVED_104_OFFSET : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant RESERVED_108_OFFSET : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant RESERVED_10C_OFFSET : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant RESERVED_110_OFFSET : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant RESERVED_114_OFFSET : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant RESERVED_118_OFFSET : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant RESERVED_11C_OFFSET : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_120_OFFSET : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_124_OFFSET : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant RESERVED_128_OFFSET : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant RESERVED_12C_OFFSET : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant RESERVED_130_OFFSET : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant RESERVED_134_OFFSET : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant RESERVED_138_OFFSET : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant RESERVED_13C_OFFSET : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant RESERVED_140_OFFSET : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant RESERVED_144_OFFSET : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant RESERVED_148_OFFSET : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant RESERVED_14C_OFFSET : std_logic_vector(8 downto 0) := "101001100"; -- 14C
constant RESERVED_150_OFFSET : std_logic_vector(8 downto 0) := "101010000"; -- 150
constant RESERVED_154_OFFSET : std_logic_vector(8 downto 0) := "101010100"; -- 154
constant RESERVED_158_OFFSET : std_logic_vector(8 downto 0) := "101011000"; -- 158
constant MM2S_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_19C_OFFSET : std_logic_vector(8 downto 0) := "110011100"; -- 19C
constant RESERVED_1A0_OFFSET : std_logic_vector(8 downto 0) := "110100000"; -- 1A0
constant RESERVED_1A4_OFFSET : std_logic_vector(8 downto 0) := "110100100"; -- 1A4
constant RESERVED_1A8_OFFSET : std_logic_vector(8 downto 0) := "110101000"; -- 1A8
constant S2MM_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "110101100"; -- 1AC
constant S2MM_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "110110000"; -- 1B0
constant S2MM_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "110110100"; -- 1B4
constant S2MM_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "110111000"; -- 1B8
constant S2MM_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "110111100"; -- 1BC
constant S2MM_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "111000000"; -- 1C0
constant S2MM_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "111000100"; -- 1C4
constant S2MM_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "111001000"; -- 1C8
constant S2MM_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "111001100"; -- 1CC
constant S2MM_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "111010000"; -- 1D0
constant S2MM_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "111010100"; -- 1D4
constant S2MM_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "111011000"; -- 1D8
constant S2MM_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "111011100"; -- 1DC
constant S2MM_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "111100000"; -- 1E0
constant S2MM_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "111100100"; -- 1E4
constant S2MM_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "111101000"; -- 1E8
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_CRCLPRK_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SYNCEN_BIT : integer := 3;
constant DMACR_FRMCNTEN_BIT : integer := 4;
constant DMACR_FSYNCSEL_LSB : integer := 5;
constant DMACR_FSYNCSEL_MSB : integer := 6;
constant DMACR_GENLOCK_SEL_BIT : integer := 7;
constant DMACR_PNTR_NUM_LSB : integer := 8;
constant DMACR_PNTR_NUM_MSB : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
--constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_REPEAT_EN_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_RESERVED2_BIT : integer := 2;
constant DMASR_ERR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_FSIZEERR_BIT : integer := 7;
constant DMASR_LSIZEERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
--constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_LSIZE_MORE_ERR_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
constant PARKPTR_FRMSTR_RSVD_BIT31 : integer := 31;
constant PARKPTR_FRMSTR_S2MM_MSB_BIT : integer := 28;
constant PARKPTR_FRMSTR_S2MM_LSB_BIT : integer := 24;
constant PARKPTR_FRMSTR_MM2S_MSB_BIT : integer := 20;
constant PARKPTR_FRMSTR_MM2S_LSB_BIT : integer := 16;
constant PARKPTR_FRMSTR_RSVD_BIT15 : integer := 15;
constant PARKPTR_FRMPTR_S2MM_MSB_BIT : integer := 12;
constant PARKPTR_FRMPTR_S2MM_LSB_BIT : integer := 8;
constant PARKPTR_FRMPTR_MM2S_MSB_BIT : integer := 4;
constant PARKPTR_FRMPTR_MM2S_LSB_BIT : integer := 0;
-- FRAMESTORE
constant FRMSTORE_LSB_BIT : integer := 0;
constant FRMSTORE_MSB_BIT : integer := NUM_FRM_STORE_WIDTH-1;
-- LineBuffer Threshold
constant THRESH_LSB_BIT : integer := 0;
constant THRESH_MSB_BIT : integer := LINEBUFFER_THRESH_WIDTH-1;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Word 0 : NXTDESC PTR LS-WORD
-- Descriptor Word 1 : NXTDESC PTR MS-WORD
-- Descriptor Word 2 : STARTADDR PTR LS-WORD
-- Descriptor Word 3 : STARTADDR PTR MS-WORD
-- Descriptor Word 4
constant DESC_WRD4_VSIZE_LSB_BIT : integer := 0;
constant DESC_WRD4_VSIZE_MSB_BIT : integer := 12;
-- Descriptor Word 5
constant DESC_WRD5_HSIZE_LSB_BIT : integer := 0;
constant DESC_WRD5_HSIZE_MSB_BIT : integer := 15;
-- Descriptor Word 6
constant DESC_WRD6_STRIDE_LSB_BIT : integer := 0;
constant DESC_WRD6_STRIDE_MSB_BIT : integer := 15;
constant DESC_WRD6_FRMDLY_LSB_BIT : integer := 24;
constant DESC_WRD6_FRMDLY_MSB_BIT : integer := 28;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Gen-Lock constants
constant MSTR0 : std_logic_vector(3 downto 0) := "0000";
constant MSTR1 : std_logic_vector(3 downto 0) := "0001";
constant MSTR2 : std_logic_vector(3 downto 0) := "0010";
constant MSTR3 : std_logic_vector(3 downto 0) := "0011";
constant MSTR4 : std_logic_vector(3 downto 0) := "0100";
constant MSTR5 : std_logic_vector(3 downto 0) := "0101";
constant MSTR6 : std_logic_vector(3 downto 0) := "0110";
constant MSTR7 : std_logic_vector(3 downto 0) := "0111";
constant MSTR8 : std_logic_vector(3 downto 0) := "1000";
constant MSTR9 : std_logic_vector(3 downto 0) := "1001";
constant MSTR10 : std_logic_vector(3 downto 0) := "1010";
constant MSTR11 : std_logic_vector(3 downto 0) := "1011";
constant MSTR12 : std_logic_vector(3 downto 0) := "1100";
constant MSTR13 : std_logic_vector(3 downto 0) := "1101";
constant MSTR14 : std_logic_vector(3 downto 0) := "1110";
constant MSTR15 : std_logic_vector(3 downto 0) := "1111";
constant MSTR0_LO_INDEX : integer := 0;
constant MSTR0_HI_INDEX : integer := 5;
constant MSTR1_LO_INDEX : integer := 6;
constant MSTR1_HI_INDEX : integer := 11;
constant MSTR2_LO_INDEX : integer := 12;
constant MSTR2_HI_INDEX : integer := 17;
constant MSTR3_LO_INDEX : integer := 18;
constant MSTR3_HI_INDEX : integer := 23;
constant MSTR4_LO_INDEX : integer := 24;
constant MSTR4_HI_INDEX : integer := 29;
constant MSTR5_LO_INDEX : integer := 30;
constant MSTR5_HI_INDEX : integer := 35;
constant MSTR6_LO_INDEX : integer := 36;
constant MSTR6_HI_INDEX : integer := 41;
constant MSTR7_LO_INDEX : integer := 42;
constant MSTR7_HI_INDEX : integer := 47;
constant MSTR8_LO_INDEX : integer := 48;
constant MSTR8_HI_INDEX : integer := 53;
constant MSTR9_LO_INDEX : integer := 54;
constant MSTR9_HI_INDEX : integer := 59;
constant MSTR10_LO_INDEX : integer := 60;
constant MSTR10_HI_INDEX : integer := 65;
constant MSTR11_LO_INDEX : integer := 66;
constant MSTR11_HI_INDEX : integer := 71;
constant MSTR12_LO_INDEX : integer := 72;
constant MSTR12_HI_INDEX : integer := 77;
constant MSTR13_LO_INDEX : integer := 78;
constant MSTR13_HI_INDEX : integer := 83;
constant MSTR14_LO_INDEX : integer := 84;
constant MSTR14_HI_INDEX : integer := 89;
constant MSTR15_LO_INDEX : integer := 90;
constant MSTR15_HI_INDEX : integer := 95;
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
constant BITS_PER_REG : integer := 32;
type STARTADDR_ARRAY_TYPE is array(natural range <>)
of std_logic_vector(BITS_PER_REG - 1 downto 0);
end axi_vdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_vdma_pkg is
-- coverage off
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- String to Integer Function
-------------------------------------------------------------------------------
function string2int(strngbuf: string)
return integer is
variable result : integer := 0;
begin
for i in 1 to strngbuf'length loop
case strngbuf(i) is
when '0' => result := result*10;
when '1' => result := result*10 + 1;
when '2' => result := result*10 + 2;
when '3' => result := result*10 + 3;
when '4' => result := result*10 + 4;
when '5' => result := result*10 + 5;
when '6' => result := result*10 + 6;
when '7' => result := result*10 + 7;
when '8' => result := result*10 + 8;
when '9' => result := result*10 + 9;
-- coverage off
when others => null;
-- coverage on
end case;
end loop;
return result;
end;
--------------------------------------------------------------------------------
--Channel Fsync & Flush decoding
--------------------------------------------------------------------------------
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 2) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_fsync;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer is
begin
if (use_s2mm_fsync = 1 or use_s2mm_fsync = 2)then
return 1;
else
return 0;
end if;
end function find_s2mm_fsync_01;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 3) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_fsync;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 2))then
return 1;
elsif (use_fsync = 2 and flush_on_fsync = 2)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_flush;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 3))then
return 1;
elsif (use_fsync = 3 and flush_on_fsync = 3)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_flush;
-- coverage on
----------------------------------------------------------------------------------------------------------
-- Function to calculate minimum threshold value for MM2S Line buffer based on TDATA, and LineBuffer Depth
----------------------------------------------------------------------------------------------------------
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth : integer)
return integer is
begin
if(mm2s_included = 0 or mm2s_linebuffer_depth = 0)then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 8) then
return 1;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 16) then
return 2;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 32) then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 64) then
return 8;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 128) then
return 16;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 256) then
return 32;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 512) then
return 64;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_mm2s_linebuffer_thresh;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth : integer)
return integer is
begin
if(s2mm_included = 0 or s2mm_linebuffer_depth = 0)then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 8) then
return 1;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 16) then
return 2;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 32) then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 64) then
return 8;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 128) then
return 16;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 256) then
return 32;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 512) then
return 64;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_s2mm_linebuffer_thresh;
-------------------------------------------------------------------------------
-- Function to calculate C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED from C_M_AXIS_MM2S_TDATA_WIDTH
-------------------------------------------------------------------------------
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer is
begin
if(mm2s_tdata_dwidth <= 16)then
return mm2s_tdata_dwidth;
elsif(mm2s_tdata_dwidth > 16 and mm2s_tdata_dwidth <= 32) then
return 32;
elsif(mm2s_tdata_dwidth > 32 and mm2s_tdata_dwidth <= 64) then
return 64;
elsif(mm2s_tdata_dwidth > 64 and mm2s_tdata_dwidth <= 128) then
return 128;
elsif(mm2s_tdata_dwidth > 128 and mm2s_tdata_dwidth <= 256) then
return 256;
elsif(mm2s_tdata_dwidth > 256 and mm2s_tdata_dwidth <= 512) then
return 512;
elsif(mm2s_tdata_dwidth > 512 and mm2s_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_mm2s_tdata_width;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer is
begin
if(s2mm_tdata_dwidth <= 16)then
return s2mm_tdata_dwidth;
elsif(s2mm_tdata_dwidth > 16 and s2mm_tdata_dwidth <= 32) then
return 32;
elsif(s2mm_tdata_dwidth > 32 and s2mm_tdata_dwidth <= 64) then
return 64;
elsif(s2mm_tdata_dwidth > 64 and s2mm_tdata_dwidth <= 128) then
return 128;
elsif(s2mm_tdata_dwidth > 128 and s2mm_tdata_dwidth <= 256) then
return 256;
elsif(s2mm_tdata_dwidth > 256 and s2mm_tdata_dwidth <= 512) then
return 512;
elsif(s2mm_tdata_dwidth > 512 and s2mm_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_s2mm_tdata_width;
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer is
begin
if(DRE_ON = 1 or ( tdata_width_calculated /= tdata_dwidth))then
return 1;
else
return 0 ;
end if;
end function enable_tkeep_connectivity;
-------------------------------------------------------------------------------
-- function to return number of registers depending on mode of operation
-------------------------------------------------------------------------------
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer is
begin
-- 1 = Scatter Gather Mode
-- 0 = Register Direct Mode
if(mode = 1)then
return sg_num;
else
return regdir_num;
end if;
end;
-- coverage off
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-- coverage on
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
return 0;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the base registers
-------------------------------------------------------------------------------
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
new_index := mm2s_index + 12;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the regdir registers
-------------------------------------------------------------------------------
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
--new_index := mm2s_index + 68;
new_index := mm2s_index + 20;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- enable internal genlock bus based on genlock modes and internal genlock
-- parameters.
-------------------------------------------------------------------------------
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer is
begin
-- internal genlock turned OFF at parameter or if NOT both channel enabled.
if(internal_genlock = 0 or mm2s_enabled = 0 or s2mm_enabled = 0)then
return 0;
-- at least one channel must be a master and one be a slave
-- before turning ON the internal genlock bus
elsif( (mm2s_genlock_mode = 0 and s2mm_genlock_mode = 1)
or (mm2s_genlock_mode = 1 and s2mm_genlock_mode = 0))then
return 1;
elsif( (mm2s_genlock_mode = 2 and s2mm_genlock_mode = 3)
or (mm2s_genlock_mode = 3 and s2mm_genlock_mode = 2))then
return 1;
-- either both are maters or both are slaves therefore
-- turn OFF internal genlock bus
else
return 0;
end if;
end;
end package body axi_vdma_pkg;
|
-------------------------------------------------------------------------------
-- axi_vdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI VDMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
package axi_vdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer;
-- CALCULATE mm2s_tdata_width for axi_vdma
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer;
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth: integer)
return integer;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth: integer)
return integer;
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Converts string to interger
function string2int(strngbuf: string)
return integer;
-- Return number of registers
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return enable genlock bus
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL_SG : integer := 62;
constant NUM_REG_TOTAL_REGDIR : integer := 62;
----constant NUM_REG_TOTAL_SG : integer := 20;
----constant NUM_REG_TOTAL_REGDIR : integer := 59;
--constant NUM_REG_TOTAL_REGDIR : integer := 156;
--constant NUM_REG_TOTAL_REGDIR : integer := 123;
constant NUM_REG_PER_CHANNEL : integer := 8;
constant NUM_DIRECT_REG_PER_CHANNEL : integer := 19;
--constant NUM_DIRECT_REG_PER_CHANNEL : integer := 67;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Clock Domain Crossing Constants
constant CDC_TYPE_PULSE_P_S : integer := 0;
constant CDC_TYPE_LEVEL_P_S : integer := 1;
constant CDC_TYPE_PULSE_S_P : integer := 2;
constant CDC_TYPE_LEVEL_S_P : integer := 3;
constant CDC_TYPE_VECTR_P_S : integer := 4;
constant CDC_TYPE_VECTR_S_P : integer := 5;
constant CDC_TYPE_PULSE_P_S_NO_RST : integer := 6;
constant CDC_TYPE_LEVEL_P_S_NO_RST : integer := 7;
constant CDC_TYPE_PULSE_S_P_NO_RST : integer := 8;
constant CDC_TYPE_LEVEL_S_P_NO_RST : integer := 9;
constant CDC_TYPE_PULSE_P_S_LL : integer := 10;
constant CDC_TYPE_PULSE_S_P_LL : integer := 11;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED : integer := 12;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED : integer := 13;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST : integer := 14;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST : integer := 15;
constant MTBF_STAGES : integer := 4;
constant MTBF_STAGES_LITE : integer := 3;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Frame Store
constant NUM_FRM_STORE_WIDTH : integer := 6;
constant FRAME_NUMBER_WIDTH : integer := NUM_FRM_STORE_WIDTH - 1;
constant ZERO_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
constant ONE_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH));
constant MAX_FSTORES : integer := 32;
-- Line Buffer
constant LINEBUFFER_THRESH_WIDTH : integer := 17;
-- Video parameter constants
constant VSIZE_DWIDTH : integer := 13;
constant HSIZE_DWIDTH : integer := 16;
constant STRIDE_DWIDTH : integer := 16;
constant FRMDLY_DWIDTH : integer := FRAME_NUMBER_WIDTH;
constant FRMDLY_MSB : integer := 28;
constant FRMDLY_LSB : integer := 24;
constant RSVD_BITS_31TO29 : std_logic_vector(2 downto 0) := (others => '0');
constant RSVD_BITS_23TO16 : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_REG_IND : integer := 5;
constant MM2S_FRAME_STORE_INDEX : integer := 6;
constant MM2S_THRESHOLD_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant VDMA_GLPTR_INDEX : integer := 9;
constant VDMA_PARKPTR_INDEX : integer := 10;
constant VDMA_VERISON_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_DMA_IRQ_MASK : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_REG_IND : integer := 17;
constant S2MM_FRAME_STORE_INDEX : integer := 18;
constant S2MM_THRESHOLD_INDEX : integer := 19;
-- Register direct
constant MM2S_VSIZE_INDEX : integer := 20;
constant MM2S_HSIZE_INDEX : integer := 21;
constant MM2S_DLYSTRD_INDEX : integer := 22;
constant MM2S_STARTADDR1_INDEX : integer := 23;
constant MM2S_STARTADDR2_INDEX : integer := 24;
constant MM2S_STARTADDR3_INDEX : integer := 25;
constant MM2S_STARTADDR4_INDEX : integer := 26;
constant MM2S_STARTADDR5_INDEX : integer := 27;
constant MM2S_STARTADDR6_INDEX : integer := 28;
constant MM2S_STARTADDR7_INDEX : integer := 29;
constant MM2S_STARTADDR8_INDEX : integer := 30;
constant MM2S_STARTADDR9_INDEX : integer := 31;
constant MM2S_STARTADDR10_INDEX : integer := 32;
constant MM2S_STARTADDR11_INDEX : integer := 33;
constant MM2S_STARTADDR12_INDEX : integer := 34;
constant MM2S_STARTADDR13_INDEX : integer := 35;
constant MM2S_STARTADDR14_INDEX : integer := 36;
constant MM2S_STARTADDR15_INDEX : integer := 37;
constant MM2S_STARTADDR16_INDEX : integer := 38;
constant RESERVED_9C_INDEX : integer := 39;
constant S2MM_VSIZE_INDEX : integer := 40;
constant S2MM_HSIZE_INDEX : integer := 41;
constant S2MM_DLYSTRD_INDEX : integer := 42;
constant S2MM_STARTADDR1_INDEX : integer := 43;
constant S2MM_STARTADDR2_INDEX : integer := 44;
constant S2MM_STARTADDR3_INDEX : integer := 45;
constant S2MM_STARTADDR4_INDEX : integer := 46;
constant S2MM_STARTADDR5_INDEX : integer := 47;
constant S2MM_STARTADDR6_INDEX : integer := 48;
constant S2MM_STARTADDR7_INDEX : integer := 49;
constant S2MM_STARTADDR8_INDEX : integer := 50;
constant S2MM_STARTADDR9_INDEX : integer := 51;
constant S2MM_STARTADDR10_INDEX : integer := 52;
constant S2MM_STARTADDR11_INDEX : integer := 53;
constant S2MM_STARTADDR12_INDEX : integer := 54;
constant S2MM_STARTADDR13_INDEX : integer := 55;
constant S2MM_STARTADDR14_INDEX : integer := 56;
constant S2MM_STARTADDR15_INDEX : integer := 57;
constant S2MM_STARTADDR16_INDEX : integer := 58;
constant RESERVED_EC_INDEX : integer := 59;
--constant RESERVED_F0_INDEX : integer := 60;
constant HSIZE_AT_LLESS_ERR_F0_INDEX : integer := 60;
--constant RESERVED_F4_INDEX : integer := 61;
constant VSIZE_AT_FLESS_ERR_F4_INDEX : integer := 61;
constant RESERVED_F8_INDEX : integer := 62;
constant RESERVED_FC_INDEX : integer := 63;
constant RESERVED_100_INDEX : integer := 64;
constant RESERVED_104_INDEX : integer := 65;
constant RESERVED_108_INDEX : integer := 66;
constant RESERVED_10C_INDEX : integer := 67;
constant RESERVED_110_INDEX : integer := 68;
constant RESERVED_114_INDEX : integer := 69;
constant RESERVED_118_INDEX : integer := 70;
constant RESERVED_11C_INDEX : integer := 71;
constant RESERVED_120_INDEX : integer := 72;
constant RESERVED_124_INDEX : integer := 73;
constant RESERVED_128_INDEX : integer := 74;
constant RESERVED_12C_INDEX : integer := 75;
constant RESERVED_130_INDEX : integer := 76;
constant RESERVED_134_INDEX : integer := 77;
constant RESERVED_138_INDEX : integer := 78;
constant RESERVED_13C_INDEX : integer := 79;
constant RESERVED_140_INDEX : integer := 80;
constant RESERVED_144_INDEX : integer := 81;
constant RESERVED_148_INDEX : integer := 82;
constant RESERVED_14C_INDEX : integer := 83;
constant RESERVED_150_INDEX : integer := 84;
constant RESERVED_154_INDEX : integer := 85;
constant RESERVED_158_INDEX : integer := 86;
constant MM2S_STARTADDR17_INDEX : integer := 87;
constant MM2S_STARTADDR18_INDEX : integer := 88;
constant MM2S_STARTADDR19_INDEX : integer := 89;
constant MM2S_STARTADDR20_INDEX : integer := 90;
constant MM2S_STARTADDR21_INDEX : integer := 91;
constant MM2S_STARTADDR22_INDEX : integer := 92;
constant MM2S_STARTADDR23_INDEX : integer := 93;
constant MM2S_STARTADDR24_INDEX : integer := 94;
constant MM2S_STARTADDR25_INDEX : integer := 95;
constant MM2S_STARTADDR26_INDEX : integer := 96;
constant MM2S_STARTADDR27_INDEX : integer := 97;
constant MM2S_STARTADDR28_INDEX : integer := 98;
constant MM2S_STARTADDR29_INDEX : integer := 99;
constant MM2S_STARTADDR30_INDEX : integer := 100;
constant MM2S_STARTADDR31_INDEX : integer := 101;
constant MM2S_STARTADDR32_INDEX : integer := 102;
constant RESERVED_19C_INDEX : integer := 103;
constant RESERVED_1A0_INDEX : integer := 104;
constant RESERVED_1A4_INDEX : integer := 105;
constant RESERVED_1A8_INDEX : integer := 106;
constant S2MM_STARTADDR17_INDEX : integer := 107;
constant S2MM_STARTADDR18_INDEX : integer := 108;
constant S2MM_STARTADDR19_INDEX : integer := 109;
constant S2MM_STARTADDR20_INDEX : integer := 110;
constant S2MM_STARTADDR21_INDEX : integer := 111;
constant S2MM_STARTADDR22_INDEX : integer := 112;
constant S2MM_STARTADDR23_INDEX : integer := 113;
constant S2MM_STARTADDR24_INDEX : integer := 114;
constant S2MM_STARTADDR25_INDEX : integer := 115;
constant S2MM_STARTADDR26_INDEX : integer := 116;
constant S2MM_STARTADDR27_INDEX : integer := 117;
constant S2MM_STARTADDR28_INDEX : integer := 118;
constant S2MM_STARTADDR29_INDEX : integer := 119;
constant S2MM_STARTADDR30_INDEX : integer := 120;
constant S2MM_STARTADDR31_INDEX : integer := 121;
constant S2MM_STARTADDR32_INDEX : integer := 122;
-- READ MUX Offsets
constant MM2S_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
-- }
constant MM2S_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_SG : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_SG : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant VDMA_PARK_PTRREF_OFFSET_SG : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_SG : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_8 : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_8 : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET_8 : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_8 : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000000"; -- 000
constant MM2S_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000100"; -- 004
constant MM2S_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001000"; -- 008
constant MM2S_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001100"; -- 00C
constant MM2S_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010000"; -- 010
constant MM2S_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 014
constant MM2S_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "000011000"; -- 018
constant MM2S_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "000011100"; -- 01C
constant RESERVED_20_OFFSET_90 : std_logic_vector(8 downto 0) := "000100000"; -- 020
constant RESERVED_24_OFFSET_90 : std_logic_vector(8 downto 0) := "000100100"; -- 024
constant VDMA_PARK_PTRREF_OFFSET_90 : std_logic_vector(8 downto 0) := "000101000"; -- 028
constant VDMA_VERSION_OFFSET_90 : std_logic_vector(8 downto 0) := "000101100"; -- 02C
constant S2MM_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110000"; -- 030
constant S2MM_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110100"; -- 034
constant S2MM_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111000"; -- 038
constant S2MM_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_DMA_IRQ_MASK_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000000"; -- 040
constant S2MM_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 044
constant S2MM_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "001001000"; -- 048
constant S2MM_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "001001100"; -- 04C
------
constant MM2S_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant MM2S_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant MM2S_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant MM2S_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant MM2S_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant MM2S_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant MM2S_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant MM2S_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_20_OFFSET_91 : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_24_OFFSET_91 : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant VDMA_PARK_PTRREF_OFFSET_91 : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant VDMA_VERSION_OFFSET_91 : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant S2MM_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant S2MM_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant S2MM_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant S2MM_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_DMA_IRQ_MASK_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant S2MM_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant S2MM_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant S2MM_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "101001100"; -- 14C
------
-------- Register direct READ MUX Offsets
constant MM2S_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010000"; -- 50
constant MM2S_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010100"; -- 54
constant MM2S_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "01011000"; -- 58
constant MM2S_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010000"; -- 050
constant MM2S_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "001011000"; -- 058
constant MM2S_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010000"; -- 050
constant MM2S_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "101011000"; -- 058
constant MM2S_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "01011100"; -- 5C
constant MM2S_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "01100000"; -- 60
constant MM2S_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "01100100"; -- 64
constant MM2S_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "01101000"; -- 68
constant MM2S_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "01101100"; -- 6C
constant MM2S_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "01110000"; -- 70
constant MM2S_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "01110100"; -- 74
constant MM2S_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "01111000"; -- 78
constant MM2S_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "01111100"; -- 7C
constant MM2S_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "10000000"; -- 80
constant MM2S_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "10000100"; -- 84
constant MM2S_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "10001000"; -- 88
constant MM2S_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "10001100"; -- 8C
constant MM2S_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "10010000"; -- 90
constant MM2S_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "10010100"; -- 94
constant MM2S_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "10011000"; -- 98
constant MM2S_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "001011100"; -- 05C
constant MM2S_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "001100000"; -- 060
constant MM2S_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "001100100"; -- 064
constant MM2S_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "001101000"; -- 068
constant MM2S_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "001101100"; -- 06C
constant MM2S_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "001110000"; -- 070
constant MM2S_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "001110100"; -- 074
constant MM2S_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "001111000"; -- 078
constant MM2S_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "001111100"; -- 07C
constant MM2S_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "010000000"; -- 080
constant MM2S_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "010000100"; -- 084
constant MM2S_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "010001000"; -- 088
constant MM2S_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "010001100"; -- 08C
constant MM2S_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "010010000"; -- 090
constant MM2S_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "010010100"; -- 094
constant MM2S_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "010011000"; -- 098
constant MM2S_STARTADDR1_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR2_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR3_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR4_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR5_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR6_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR7_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR8_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR9_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR10_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR11_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR12_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR13_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR14_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR15_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR16_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_9C_OFFSET_90 : std_logic_vector(8 downto 0) := "010011100"; -- 9C
constant S2MM_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100000"; -- A0
constant S2MM_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "10101000"; -- A8
constant S2MM_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100000"; -- A0
constant S2MM_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "010101000"; -- A8
constant S2MM_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100000"; -- A0
constant S2MM_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "110101000"; -- A8
constant S2MM_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "10101100"; -- AC
constant S2MM_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "10110000"; -- B0
constant S2MM_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "10110100"; -- B4
constant S2MM_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "10111000"; -- B8
constant S2MM_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "10111100"; -- BC
constant S2MM_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "11000000"; -- C0
constant S2MM_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "11000100"; -- C4
constant S2MM_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "11001000"; -- C8
constant S2MM_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "11001100"; -- CC
constant S2MM_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "11010000"; -- D0
constant S2MM_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "11010100"; -- D4
constant S2MM_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "11011000"; -- D8
constant S2MM_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "11011100"; -- DC
constant S2MM_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "11100000"; -- E0
constant S2MM_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "11100100"; -- E4
constant S2MM_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "11101000"; -- E8
constant S2MM_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "010101100"; -- 0AC
constant S2MM_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "010110000"; -- 0B0
constant S2MM_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "010110100"; -- 0B4
constant S2MM_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "010111000"; -- 0B8
constant S2MM_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "010111100"; -- 0BC
constant S2MM_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "011000000"; -- 0C0
constant S2MM_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "011000100"; -- 0C4
constant S2MM_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "011001000"; -- 0C8
constant S2MM_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "011001100"; -- 0CC
constant S2MM_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "011010000"; -- 0D0
constant S2MM_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "011010100"; -- 0D4
constant S2MM_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "011011000"; -- 0D8
constant S2MM_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "011011100"; -- 0DC
constant S2MM_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "011100000"; -- 0E0
constant S2MM_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "011100100"; -- 0E4
constant S2MM_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "011101000"; -- 0E8
constant RESERVED_EC_OFFSET : std_logic_vector(8 downto 0) := "011101100"; -- 0EC
constant RESERVED_F0_OFFSET : std_logic_vector(8 downto 0) := "011110000"; -- 0F0
constant RESERVED_F4_OFFSET : std_logic_vector(8 downto 0) := "011110100"; -- 0F4
constant RESERVED_F8_OFFSET : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
constant RESERVED_FC_OFFSET : std_logic_vector(8 downto 0) := "011111100"; -- 0FC
constant RESERVED_100_OFFSET : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant RESERVED_104_OFFSET : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant RESERVED_108_OFFSET : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant RESERVED_10C_OFFSET : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant RESERVED_110_OFFSET : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant RESERVED_114_OFFSET : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant RESERVED_118_OFFSET : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant RESERVED_11C_OFFSET : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_120_OFFSET : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_124_OFFSET : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant RESERVED_128_OFFSET : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant RESERVED_12C_OFFSET : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant RESERVED_130_OFFSET : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant RESERVED_134_OFFSET : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant RESERVED_138_OFFSET : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant RESERVED_13C_OFFSET : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant RESERVED_140_OFFSET : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant RESERVED_144_OFFSET : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant RESERVED_148_OFFSET : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant RESERVED_14C_OFFSET : std_logic_vector(8 downto 0) := "101001100"; -- 14C
constant RESERVED_150_OFFSET : std_logic_vector(8 downto 0) := "101010000"; -- 150
constant RESERVED_154_OFFSET : std_logic_vector(8 downto 0) := "101010100"; -- 154
constant RESERVED_158_OFFSET : std_logic_vector(8 downto 0) := "101011000"; -- 158
constant MM2S_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_19C_OFFSET : std_logic_vector(8 downto 0) := "110011100"; -- 19C
constant RESERVED_1A0_OFFSET : std_logic_vector(8 downto 0) := "110100000"; -- 1A0
constant RESERVED_1A4_OFFSET : std_logic_vector(8 downto 0) := "110100100"; -- 1A4
constant RESERVED_1A8_OFFSET : std_logic_vector(8 downto 0) := "110101000"; -- 1A8
constant S2MM_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "110101100"; -- 1AC
constant S2MM_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "110110000"; -- 1B0
constant S2MM_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "110110100"; -- 1B4
constant S2MM_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "110111000"; -- 1B8
constant S2MM_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "110111100"; -- 1BC
constant S2MM_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "111000000"; -- 1C0
constant S2MM_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "111000100"; -- 1C4
constant S2MM_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "111001000"; -- 1C8
constant S2MM_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "111001100"; -- 1CC
constant S2MM_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "111010000"; -- 1D0
constant S2MM_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "111010100"; -- 1D4
constant S2MM_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "111011000"; -- 1D8
constant S2MM_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "111011100"; -- 1DC
constant S2MM_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "111100000"; -- 1E0
constant S2MM_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "111100100"; -- 1E4
constant S2MM_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "111101000"; -- 1E8
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_CRCLPRK_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SYNCEN_BIT : integer := 3;
constant DMACR_FRMCNTEN_BIT : integer := 4;
constant DMACR_FSYNCSEL_LSB : integer := 5;
constant DMACR_FSYNCSEL_MSB : integer := 6;
constant DMACR_GENLOCK_SEL_BIT : integer := 7;
constant DMACR_PNTR_NUM_LSB : integer := 8;
constant DMACR_PNTR_NUM_MSB : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
--constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_REPEAT_EN_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_RESERVED2_BIT : integer := 2;
constant DMASR_ERR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_FSIZEERR_BIT : integer := 7;
constant DMASR_LSIZEERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
--constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_LSIZE_MORE_ERR_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
constant PARKPTR_FRMSTR_RSVD_BIT31 : integer := 31;
constant PARKPTR_FRMSTR_S2MM_MSB_BIT : integer := 28;
constant PARKPTR_FRMSTR_S2MM_LSB_BIT : integer := 24;
constant PARKPTR_FRMSTR_MM2S_MSB_BIT : integer := 20;
constant PARKPTR_FRMSTR_MM2S_LSB_BIT : integer := 16;
constant PARKPTR_FRMSTR_RSVD_BIT15 : integer := 15;
constant PARKPTR_FRMPTR_S2MM_MSB_BIT : integer := 12;
constant PARKPTR_FRMPTR_S2MM_LSB_BIT : integer := 8;
constant PARKPTR_FRMPTR_MM2S_MSB_BIT : integer := 4;
constant PARKPTR_FRMPTR_MM2S_LSB_BIT : integer := 0;
-- FRAMESTORE
constant FRMSTORE_LSB_BIT : integer := 0;
constant FRMSTORE_MSB_BIT : integer := NUM_FRM_STORE_WIDTH-1;
-- LineBuffer Threshold
constant THRESH_LSB_BIT : integer := 0;
constant THRESH_MSB_BIT : integer := LINEBUFFER_THRESH_WIDTH-1;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Word 0 : NXTDESC PTR LS-WORD
-- Descriptor Word 1 : NXTDESC PTR MS-WORD
-- Descriptor Word 2 : STARTADDR PTR LS-WORD
-- Descriptor Word 3 : STARTADDR PTR MS-WORD
-- Descriptor Word 4
constant DESC_WRD4_VSIZE_LSB_BIT : integer := 0;
constant DESC_WRD4_VSIZE_MSB_BIT : integer := 12;
-- Descriptor Word 5
constant DESC_WRD5_HSIZE_LSB_BIT : integer := 0;
constant DESC_WRD5_HSIZE_MSB_BIT : integer := 15;
-- Descriptor Word 6
constant DESC_WRD6_STRIDE_LSB_BIT : integer := 0;
constant DESC_WRD6_STRIDE_MSB_BIT : integer := 15;
constant DESC_WRD6_FRMDLY_LSB_BIT : integer := 24;
constant DESC_WRD6_FRMDLY_MSB_BIT : integer := 28;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Gen-Lock constants
constant MSTR0 : std_logic_vector(3 downto 0) := "0000";
constant MSTR1 : std_logic_vector(3 downto 0) := "0001";
constant MSTR2 : std_logic_vector(3 downto 0) := "0010";
constant MSTR3 : std_logic_vector(3 downto 0) := "0011";
constant MSTR4 : std_logic_vector(3 downto 0) := "0100";
constant MSTR5 : std_logic_vector(3 downto 0) := "0101";
constant MSTR6 : std_logic_vector(3 downto 0) := "0110";
constant MSTR7 : std_logic_vector(3 downto 0) := "0111";
constant MSTR8 : std_logic_vector(3 downto 0) := "1000";
constant MSTR9 : std_logic_vector(3 downto 0) := "1001";
constant MSTR10 : std_logic_vector(3 downto 0) := "1010";
constant MSTR11 : std_logic_vector(3 downto 0) := "1011";
constant MSTR12 : std_logic_vector(3 downto 0) := "1100";
constant MSTR13 : std_logic_vector(3 downto 0) := "1101";
constant MSTR14 : std_logic_vector(3 downto 0) := "1110";
constant MSTR15 : std_logic_vector(3 downto 0) := "1111";
constant MSTR0_LO_INDEX : integer := 0;
constant MSTR0_HI_INDEX : integer := 5;
constant MSTR1_LO_INDEX : integer := 6;
constant MSTR1_HI_INDEX : integer := 11;
constant MSTR2_LO_INDEX : integer := 12;
constant MSTR2_HI_INDEX : integer := 17;
constant MSTR3_LO_INDEX : integer := 18;
constant MSTR3_HI_INDEX : integer := 23;
constant MSTR4_LO_INDEX : integer := 24;
constant MSTR4_HI_INDEX : integer := 29;
constant MSTR5_LO_INDEX : integer := 30;
constant MSTR5_HI_INDEX : integer := 35;
constant MSTR6_LO_INDEX : integer := 36;
constant MSTR6_HI_INDEX : integer := 41;
constant MSTR7_LO_INDEX : integer := 42;
constant MSTR7_HI_INDEX : integer := 47;
constant MSTR8_LO_INDEX : integer := 48;
constant MSTR8_HI_INDEX : integer := 53;
constant MSTR9_LO_INDEX : integer := 54;
constant MSTR9_HI_INDEX : integer := 59;
constant MSTR10_LO_INDEX : integer := 60;
constant MSTR10_HI_INDEX : integer := 65;
constant MSTR11_LO_INDEX : integer := 66;
constant MSTR11_HI_INDEX : integer := 71;
constant MSTR12_LO_INDEX : integer := 72;
constant MSTR12_HI_INDEX : integer := 77;
constant MSTR13_LO_INDEX : integer := 78;
constant MSTR13_HI_INDEX : integer := 83;
constant MSTR14_LO_INDEX : integer := 84;
constant MSTR14_HI_INDEX : integer := 89;
constant MSTR15_LO_INDEX : integer := 90;
constant MSTR15_HI_INDEX : integer := 95;
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
constant BITS_PER_REG : integer := 32;
type STARTADDR_ARRAY_TYPE is array(natural range <>)
of std_logic_vector(BITS_PER_REG - 1 downto 0);
end axi_vdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_vdma_pkg is
-- coverage off
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- String to Integer Function
-------------------------------------------------------------------------------
function string2int(strngbuf: string)
return integer is
variable result : integer := 0;
begin
for i in 1 to strngbuf'length loop
case strngbuf(i) is
when '0' => result := result*10;
when '1' => result := result*10 + 1;
when '2' => result := result*10 + 2;
when '3' => result := result*10 + 3;
when '4' => result := result*10 + 4;
when '5' => result := result*10 + 5;
when '6' => result := result*10 + 6;
when '7' => result := result*10 + 7;
when '8' => result := result*10 + 8;
when '9' => result := result*10 + 9;
-- coverage off
when others => null;
-- coverage on
end case;
end loop;
return result;
end;
--------------------------------------------------------------------------------
--Channel Fsync & Flush decoding
--------------------------------------------------------------------------------
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 2) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_fsync;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer is
begin
if (use_s2mm_fsync = 1 or use_s2mm_fsync = 2)then
return 1;
else
return 0;
end if;
end function find_s2mm_fsync_01;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 3) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_fsync;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 2))then
return 1;
elsif (use_fsync = 2 and flush_on_fsync = 2)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_flush;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 3))then
return 1;
elsif (use_fsync = 3 and flush_on_fsync = 3)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_flush;
-- coverage on
----------------------------------------------------------------------------------------------------------
-- Function to calculate minimum threshold value for MM2S Line buffer based on TDATA, and LineBuffer Depth
----------------------------------------------------------------------------------------------------------
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth : integer)
return integer is
begin
if(mm2s_included = 0 or mm2s_linebuffer_depth = 0)then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 8) then
return 1;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 16) then
return 2;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 32) then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 64) then
return 8;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 128) then
return 16;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 256) then
return 32;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 512) then
return 64;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_mm2s_linebuffer_thresh;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth : integer)
return integer is
begin
if(s2mm_included = 0 or s2mm_linebuffer_depth = 0)then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 8) then
return 1;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 16) then
return 2;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 32) then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 64) then
return 8;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 128) then
return 16;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 256) then
return 32;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 512) then
return 64;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_s2mm_linebuffer_thresh;
-------------------------------------------------------------------------------
-- Function to calculate C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED from C_M_AXIS_MM2S_TDATA_WIDTH
-------------------------------------------------------------------------------
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer is
begin
if(mm2s_tdata_dwidth <= 16)then
return mm2s_tdata_dwidth;
elsif(mm2s_tdata_dwidth > 16 and mm2s_tdata_dwidth <= 32) then
return 32;
elsif(mm2s_tdata_dwidth > 32 and mm2s_tdata_dwidth <= 64) then
return 64;
elsif(mm2s_tdata_dwidth > 64 and mm2s_tdata_dwidth <= 128) then
return 128;
elsif(mm2s_tdata_dwidth > 128 and mm2s_tdata_dwidth <= 256) then
return 256;
elsif(mm2s_tdata_dwidth > 256 and mm2s_tdata_dwidth <= 512) then
return 512;
elsif(mm2s_tdata_dwidth > 512 and mm2s_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_mm2s_tdata_width;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer is
begin
if(s2mm_tdata_dwidth <= 16)then
return s2mm_tdata_dwidth;
elsif(s2mm_tdata_dwidth > 16 and s2mm_tdata_dwidth <= 32) then
return 32;
elsif(s2mm_tdata_dwidth > 32 and s2mm_tdata_dwidth <= 64) then
return 64;
elsif(s2mm_tdata_dwidth > 64 and s2mm_tdata_dwidth <= 128) then
return 128;
elsif(s2mm_tdata_dwidth > 128 and s2mm_tdata_dwidth <= 256) then
return 256;
elsif(s2mm_tdata_dwidth > 256 and s2mm_tdata_dwidth <= 512) then
return 512;
elsif(s2mm_tdata_dwidth > 512 and s2mm_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_s2mm_tdata_width;
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer is
begin
if(DRE_ON = 1 or ( tdata_width_calculated /= tdata_dwidth))then
return 1;
else
return 0 ;
end if;
end function enable_tkeep_connectivity;
-------------------------------------------------------------------------------
-- function to return number of registers depending on mode of operation
-------------------------------------------------------------------------------
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer is
begin
-- 1 = Scatter Gather Mode
-- 0 = Register Direct Mode
if(mode = 1)then
return sg_num;
else
return regdir_num;
end if;
end;
-- coverage off
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-- coverage on
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
return 0;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the base registers
-------------------------------------------------------------------------------
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
new_index := mm2s_index + 12;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the regdir registers
-------------------------------------------------------------------------------
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
--new_index := mm2s_index + 68;
new_index := mm2s_index + 20;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- enable internal genlock bus based on genlock modes and internal genlock
-- parameters.
-------------------------------------------------------------------------------
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer is
begin
-- internal genlock turned OFF at parameter or if NOT both channel enabled.
if(internal_genlock = 0 or mm2s_enabled = 0 or s2mm_enabled = 0)then
return 0;
-- at least one channel must be a master and one be a slave
-- before turning ON the internal genlock bus
elsif( (mm2s_genlock_mode = 0 and s2mm_genlock_mode = 1)
or (mm2s_genlock_mode = 1 and s2mm_genlock_mode = 0))then
return 1;
elsif( (mm2s_genlock_mode = 2 and s2mm_genlock_mode = 3)
or (mm2s_genlock_mode = 3 and s2mm_genlock_mode = 2))then
return 1;
-- either both are maters or both are slaves therefore
-- turn OFF internal genlock bus
else
return 0;
end if;
end;
end package body axi_vdma_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_219 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_219;
architecture augh of mul_219 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_219 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_219;
architecture augh of mul_219 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01914ent IS
END c07s02b01x00p01n01i01914ent;
ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := not b1;
assert NOT(b1 = '1')
report "***PASSED TEST: c07s02b01x00p01n01i01914"
severity NOTE;
assert (b1 = '1')
report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01914arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01914ent IS
END c07s02b01x00p01n01i01914ent;
ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := not b1;
assert NOT(b1 = '1')
report "***PASSED TEST: c07s02b01x00p01n01i01914"
severity NOTE;
assert (b1 = '1')
report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01914arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01914ent IS
END c07s02b01x00p01n01i01914ent;
ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := not b1;
assert NOT(b1 = '1')
report "***PASSED TEST: c07s02b01x00p01n01i01914"
severity NOTE;
assert (b1 = '1')
report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01914arch;
|
-------------------------------------------------------------------------------
-- Title : CRC32 calculator
-------------------------------------------------------------------------------
-- File : crc32.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module calculates a 32-bit CRC over the incoming data-
-- stream (N-bits at a time). Note that the last bit of the
-- polynom needs to be set to '0', due to the way the code
-- is constructed.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc32 is
generic (
g_data_width : natural := 8 );
port (
clock : in std_logic;
clock_en : in std_logic;
sync : in std_logic;
data : in std_logic_vector(g_data_width-1 downto 0);
data_valid : in std_logic;
crc : out std_logic_vector(31 downto 0) );
end crc32;
architecture behavioral of crc32 is
signal crc_reg : std_logic_vector(31 downto 0) := (others => '0');
constant polynom : std_logic_vector(31 downto 0) := X"04C11DB6";
-- CRC-32 = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 (used in Ethernet)
-- 3322 2222 2222 1111 1111 1100 0000 0000
-- 1098 7654 3210 9876 5432 1098 7654 3210
-- 0000 0100 1100 0001 0001 1101 1011 0111
begin
process(clock)
function new_crc(i, p: std_logic_vector; data : std_logic) return std_logic_vector is
variable sh : std_logic_vector(i'range);
variable d : std_logic;
begin
d := data xor i(i'high);
sh := i(i'high-1 downto 0) & d; --'0';
if d = '1' then
sh := sh xor p;
end if;
return sh;
end new_crc;
variable tmp : std_logic_vector(crc_reg'range);
begin
if rising_edge(clock) then
if clock_en='1' then
if data_valid='1' then
if sync='1' then
tmp := (others => '1');
else
tmp := crc_reg;
end if;
for i in data'reverse_range loop -- LSB first!
tmp := new_crc(tmp, polynom, data(i));
end loop;
crc_reg <= tmp;
elsif sync='1' then
crc_reg <= (others => '1');
end if;
end if;
end if;
end process;
process(crc_reg)
begin
for i in 0 to 31 loop
crc(i) <= not crc_reg(31-i);
end loop;
end process;
end behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_12;
USE axi_dma_v7_1_12.axi_dma;
ENTITY system_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_axi_dma_0_0;
ARCHITECTURE system_axi_dma_0_0_arch OF system_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_dma_0_0_arch : ARCHITECTURE IS "system_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_dma_0_0_arch: ARCHITECTURE IS "system_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=1,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_A" &
"XIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END system_axi_dma_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 12:06:03
-- Design Name: rx_path_lookup.vhd
-- Module Name: rx_path_lookup - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- this module handles the frame lookup
-- according to the header input the output ports for each frame are searched for in the lookup memory
-- the lookup memory constists of one base configuration, frame confiugrations and one default configuration
-- - base configuration gives the entry to the frame configuration
-- - frame configurations returns a one-hot-encoded output ports vector for each valid mac destination address
-- and the priority of the frame
-- - for mac address not in the lookup table the default configuration decides whether to skip this frame or
-- to send it to default output ports
-- transmitting the frame on the receiving port is prevented by setting the corresponding bit in the ports vector to '0'
--
-- for more details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
-- for more detail on the lookup module see switch_port_rxpath_lookup.svg
--
-- base_address is an internal register pointing to the base configuration; lateron it has to be connected to a processor
-- the housekeeping processor also has to take care of writing all the configurations to the lookup memory
-- thereby, an overflow of the memory address space of the binary list must not happen as no overflow control is
-- implemented in the lookup algorithm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity rx_path_lookup is
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
-- lookup memory address constants
LOWER_ADDR_START : integer := 20;
UPPER_ADDR_START : integer := 40;
DEF_ADDR_START : integer := 0;
ENABLE_START : integer := 63;
PORTS_START : integer := 60;
PRIO_START : integer := 48;
SKIP_FRAME_START : integer := 0;
DEST_MAC_START : integer := 0
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end rx_path_lookup;
architecture rtl of rx_path_lookup is
-- determine the next search address (median) of the binary search
-- upper and lower are the corresponding border memory adresses of the remaining search space
-- return value median = (upper + lower) / 2
function upper_add_lower_by2_f (upper, lower : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0))
return std_logic_vector is
variable x1 : integer;
variable x2 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH downto 0);
variable x3 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
x1 := to_integer(unsigned(upper)) + to_integer(unsigned(lower));
x2 := std_logic_vector(to_unsigned(x1,x2'length));
x3 := x2(LOOKUP_MEM_ADDR_WIDTH downto 1);
return x3;
end upper_add_lower_by2_f;
-- lookup state machine
type state is (
IDLE,
READ_BASE,
LOOKUP,
READ_DEFAULT
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal read_header_sig : std_logic := '0';
signal read_base_sig : std_logic := '0';
signal read_default_sig : std_logic := '0';
signal lookup_valid_sig : std_logic := '0';
signal read_lookup_sig : std_logic := '0';
signal update_sig : std_logic := '0';
signal lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
-- process registers
signal dest_mac_reg : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
signal vlan_enable_reg : std_logic;
signal vlan_prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lower_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal default_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal ports_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal skip_frame_reg : std_logic;
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- alias signals for memory read access
signal mem_lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_default_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_lookup_enable_sig : std_logic;
signal mem_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal mem_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal mem_skip_frame_sig : std_logic;
signal mem_dest_mac_sig : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
-- internal registers (to be connected to the outside, e.g. housekeeping processor)
signal base_address : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0) := "000000000";
begin
-- alias names (signals) for lookup memory output ranges
mem_lower_sig <= mem_data(LOWER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto LOWER_ADDR_START);
mem_upper_sig <= mem_data(UPPER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto UPPER_ADDR_START);
mem_default_sig <= mem_data(DEF_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto DEF_ADDR_START);
mem_lookup_enable_sig <= mem_data(ENABLE_START);
mem_ports_sig <= mem_data(PORTS_START+NR_PORTS-1 downto PORTS_START);
mem_prio_sig <= mem_data(PRIO_START+VLAN_PRIO_WIDTH-1 downto PRIO_START);
mem_skip_frame_sig <= mem_data(SKIP_FRAME_START);
mem_dest_mac_sig <= mem_data(DEST_MAC_START+DEST_MAC_WIDTH-1 downto DEST_MAC_START);
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, lookup_in_valid, mem_lookup_enable_sig, mem_default_sig,
BASE_ADDRESS, median_sig, upper_reg, lower_reg, median_reg, default_reg, dest_mac_reg,
mem_dest_mac_sig, mem_upper_sig, mem_lower_sig)
begin
-- default signal assignments
nxt_state <= IDLE;
read_header_sig <= '0'; -- read_header_p
read_base_sig <= '0'; -- write_internal_registers_p
read_default_sig <= '0'; -- output_reg_p
lookup_valid_sig <= '0'; -- output_valid_p
read_lookup_sig <= '0'; -- output_reg_p
update_sig <= '0'; -- write_internal_registers_p
upper_sig <= (others => '0'); -- upper_add_lower_by2_f
lower_sig <= (others => '0'); -- upper_add_lower_by2_f
-- default output values
mem_enable <= '0';
mem_addr <= (others => '1');
case cur_state is
when IDLE => -- waiting for a new header
if lookup_in_valid = '1' then
nxt_state <= READ_BASE;
read_header_sig <= '1'; -- read_header_p
mem_enable <= '1';
mem_addr <= BASE_ADDRESS;
end if;
when READ_BASE => -- read base address, determine if lookup is enabled
read_base_sig <= '1'; -- internal_reg_p
mem_enable <= '1';
if mem_lookup_enable_sig = '0' then -- lookup disabled, read default configuration
nxt_state <= READ_DEFAULT;
mem_addr <= mem_default_sig;
else -- lookup enabled, search for address in the middle of binary lookup list
nxt_state <= LOOKUP;
upper_sig <= mem_upper_sig; -- upper_add_lower_by2_f
lower_sig <= mem_lower_sig; -- upper_add_lower_by2_f
mem_addr <= median_sig; -- upper_add_lower_by2_f
end if;
when LOOKUP => -- lookup the median memory address and check if the memory mac address matches the frame mac address
if dest_mac_reg = mem_dest_mac_sig then -- MAC ADDRESS found -> Algorithm terminates
nxt_state <= IDLE;
read_lookup_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
elsif upper_reg <= lower_reg then -- MAC ADDRESS not found -> Algorithm terminats with default configuration
nxt_state <= READ_DEFAULT;
mem_addr <= default_reg;
mem_enable <= '1';
else -- MAC ADDRESS not found, Algorithm not terminated yet, continue lookup with decreased search space
update_sig <= '1'; -- internal_reg_p
mem_addr <= median_sig; -- upper_add_lower_by2_f
mem_enable <= '1';
nxt_state <= LOOKUP;
if dest_mac_reg > mem_dest_mac_sig then
upper_sig <= upper_reg; -- upper_add_lower_by2_f
lower_sig <= median_reg + 1; -- upper_add_lower_by2_f
else -- dest_mac_reg < mem_dest_mac_sig
upper_sig <= median_reg - 1; -- upper_add_lower_by2_f
lower_sig <= lower_reg; -- upper_add_lower_by2_f
end if;
end if;
when READ_DEFAULT =>
nxt_state <= IDLE;
read_default_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
end case;
end process;
-- handshake protocol to read header from previous module and store header into internal buffer
read_header_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
dest_mac_reg <= (others => '0');
vlan_enable_reg <= '0';
vlan_prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
lookup_in_ready <= '0';
else
dest_mac_reg <= dest_mac_reg;
vlan_enable_reg <= vlan_enable_reg;
vlan_prio_reg <= vlan_prio_reg;
timestamp_reg <= timestamp_reg;
lookup_in_ready <= '0';
if read_header_sig = '1' then
dest_mac_reg <= lookup_in_dest;
vlan_enable_reg <= lookup_in_vlan_enable;
vlan_prio_reg <= lookup_in_vlan_prio;
timestamp_reg <= lookup_in_timestamp;
lookup_in_ready <= '1';
end if;
end if;
end if;
end process;
-- handles access to the internal registers needed for lookup
internal_reg_p : process (clk) -- to be done
begin
if clk'event and clk = '1' then
if reset = '1' then
lower_reg <= (others => '0');
upper_reg <= (others => '0');
default_reg <= (others => '0');
median_reg <= (others => '0');
else
lower_reg <= lower_reg;
upper_reg <= upper_reg;
default_reg <= default_reg;
median_reg <= median_reg;
if read_base_sig = '1' then -- read inital values from base configuration
lower_reg <= mem_lower_sig;
upper_reg <= mem_upper_sig;
default_reg <= mem_default_sig;
median_reg <= median_sig;
elsif update_sig = '1' then -- update registers according to remaining search space
lower_reg <= lower_sig;
upper_reg <= upper_sig;
median_reg <= median_sig;
end if;
end if;
end if;
end process;
-- assign next memory search address: median address in the remaining address search space
median_sig <= upper_add_lower_by2_f(upper_sig, lower_sig);
-- updates the output value registers (ports, priority and skip)
output_reg_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
ports_reg <= (others => '0');
prio_reg <= (others => '0');
skip_frame_reg <= '0';
else
ports_reg <= ports_reg;
prio_reg <= prio_reg;
skip_frame_reg <= skip_frame_reg;
if read_default_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0';
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= mem_skip_frame_sig;
elsif read_lookup_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0'; -- comment for loopback functionality
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= '0';
end if;
end if;
end if;
end process;
-- sets the output valid bit
output_valid_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
lookup_out_valid <= '0';
else
lookup_out_valid <= '0';
if lookup_valid_sig = '1' then
lookup_out_valid <= '1';
end if;
end if;
end if;
end process;
-- other outputs
lookup_out_ports <= ports_reg;
lookup_out_prio <= prio_reg;
lookup_out_skip <= skip_frame_reg;
lookup_out_timestamp <= timestamp_reg;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 12:06:03
-- Design Name: rx_path_lookup.vhd
-- Module Name: rx_path_lookup - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- this module handles the frame lookup
-- according to the header input the output ports for each frame are searched for in the lookup memory
-- the lookup memory constists of one base configuration, frame confiugrations and one default configuration
-- - base configuration gives the entry to the frame configuration
-- - frame configurations returns a one-hot-encoded output ports vector for each valid mac destination address
-- and the priority of the frame
-- - for mac address not in the lookup table the default configuration decides whether to skip this frame or
-- to send it to default output ports
-- transmitting the frame on the receiving port is prevented by setting the corresponding bit in the ports vector to '0'
--
-- for more details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
-- for more detail on the lookup module see switch_port_rxpath_lookup.svg
--
-- base_address is an internal register pointing to the base configuration; lateron it has to be connected to a processor
-- the housekeeping processor also has to take care of writing all the configurations to the lookup memory
-- thereby, an overflow of the memory address space of the binary list must not happen as no overflow control is
-- implemented in the lookup algorithm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity rx_path_lookup is
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
-- lookup memory address constants
LOWER_ADDR_START : integer := 20;
UPPER_ADDR_START : integer := 40;
DEF_ADDR_START : integer := 0;
ENABLE_START : integer := 63;
PORTS_START : integer := 60;
PRIO_START : integer := 48;
SKIP_FRAME_START : integer := 0;
DEST_MAC_START : integer := 0
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end rx_path_lookup;
architecture rtl of rx_path_lookup is
-- determine the next search address (median) of the binary search
-- upper and lower are the corresponding border memory adresses of the remaining search space
-- return value median = (upper + lower) / 2
function upper_add_lower_by2_f (upper, lower : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0))
return std_logic_vector is
variable x1 : integer;
variable x2 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH downto 0);
variable x3 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
x1 := to_integer(unsigned(upper)) + to_integer(unsigned(lower));
x2 := std_logic_vector(to_unsigned(x1,x2'length));
x3 := x2(LOOKUP_MEM_ADDR_WIDTH downto 1);
return x3;
end upper_add_lower_by2_f;
-- lookup state machine
type state is (
IDLE,
READ_BASE,
LOOKUP,
READ_DEFAULT
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal read_header_sig : std_logic := '0';
signal read_base_sig : std_logic := '0';
signal read_default_sig : std_logic := '0';
signal lookup_valid_sig : std_logic := '0';
signal read_lookup_sig : std_logic := '0';
signal update_sig : std_logic := '0';
signal lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
-- process registers
signal dest_mac_reg : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
signal vlan_enable_reg : std_logic;
signal vlan_prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lower_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal default_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal ports_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal skip_frame_reg : std_logic;
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- alias signals for memory read access
signal mem_lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_default_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_lookup_enable_sig : std_logic;
signal mem_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal mem_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal mem_skip_frame_sig : std_logic;
signal mem_dest_mac_sig : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
-- internal registers (to be connected to the outside, e.g. housekeeping processor)
signal base_address : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0) := "000000000";
begin
-- alias names (signals) for lookup memory output ranges
mem_lower_sig <= mem_data(LOWER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto LOWER_ADDR_START);
mem_upper_sig <= mem_data(UPPER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto UPPER_ADDR_START);
mem_default_sig <= mem_data(DEF_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto DEF_ADDR_START);
mem_lookup_enable_sig <= mem_data(ENABLE_START);
mem_ports_sig <= mem_data(PORTS_START+NR_PORTS-1 downto PORTS_START);
mem_prio_sig <= mem_data(PRIO_START+VLAN_PRIO_WIDTH-1 downto PRIO_START);
mem_skip_frame_sig <= mem_data(SKIP_FRAME_START);
mem_dest_mac_sig <= mem_data(DEST_MAC_START+DEST_MAC_WIDTH-1 downto DEST_MAC_START);
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, lookup_in_valid, mem_lookup_enable_sig, mem_default_sig,
BASE_ADDRESS, median_sig, upper_reg, lower_reg, median_reg, default_reg, dest_mac_reg,
mem_dest_mac_sig, mem_upper_sig, mem_lower_sig)
begin
-- default signal assignments
nxt_state <= IDLE;
read_header_sig <= '0'; -- read_header_p
read_base_sig <= '0'; -- write_internal_registers_p
read_default_sig <= '0'; -- output_reg_p
lookup_valid_sig <= '0'; -- output_valid_p
read_lookup_sig <= '0'; -- output_reg_p
update_sig <= '0'; -- write_internal_registers_p
upper_sig <= (others => '0'); -- upper_add_lower_by2_f
lower_sig <= (others => '0'); -- upper_add_lower_by2_f
-- default output values
mem_enable <= '0';
mem_addr <= (others => '1');
case cur_state is
when IDLE => -- waiting for a new header
if lookup_in_valid = '1' then
nxt_state <= READ_BASE;
read_header_sig <= '1'; -- read_header_p
mem_enable <= '1';
mem_addr <= BASE_ADDRESS;
end if;
when READ_BASE => -- read base address, determine if lookup is enabled
read_base_sig <= '1'; -- internal_reg_p
mem_enable <= '1';
if mem_lookup_enable_sig = '0' then -- lookup disabled, read default configuration
nxt_state <= READ_DEFAULT;
mem_addr <= mem_default_sig;
else -- lookup enabled, search for address in the middle of binary lookup list
nxt_state <= LOOKUP;
upper_sig <= mem_upper_sig; -- upper_add_lower_by2_f
lower_sig <= mem_lower_sig; -- upper_add_lower_by2_f
mem_addr <= median_sig; -- upper_add_lower_by2_f
end if;
when LOOKUP => -- lookup the median memory address and check if the memory mac address matches the frame mac address
if dest_mac_reg = mem_dest_mac_sig then -- MAC ADDRESS found -> Algorithm terminates
nxt_state <= IDLE;
read_lookup_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
elsif upper_reg <= lower_reg then -- MAC ADDRESS not found -> Algorithm terminats with default configuration
nxt_state <= READ_DEFAULT;
mem_addr <= default_reg;
mem_enable <= '1';
else -- MAC ADDRESS not found, Algorithm not terminated yet, continue lookup with decreased search space
update_sig <= '1'; -- internal_reg_p
mem_addr <= median_sig; -- upper_add_lower_by2_f
mem_enable <= '1';
nxt_state <= LOOKUP;
if dest_mac_reg > mem_dest_mac_sig then
upper_sig <= upper_reg; -- upper_add_lower_by2_f
lower_sig <= median_reg + 1; -- upper_add_lower_by2_f
else -- dest_mac_reg < mem_dest_mac_sig
upper_sig <= median_reg - 1; -- upper_add_lower_by2_f
lower_sig <= lower_reg; -- upper_add_lower_by2_f
end if;
end if;
when READ_DEFAULT =>
nxt_state <= IDLE;
read_default_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
end case;
end process;
-- handshake protocol to read header from previous module and store header into internal buffer
read_header_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
dest_mac_reg <= (others => '0');
vlan_enable_reg <= '0';
vlan_prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
lookup_in_ready <= '0';
else
dest_mac_reg <= dest_mac_reg;
vlan_enable_reg <= vlan_enable_reg;
vlan_prio_reg <= vlan_prio_reg;
timestamp_reg <= timestamp_reg;
lookup_in_ready <= '0';
if read_header_sig = '1' then
dest_mac_reg <= lookup_in_dest;
vlan_enable_reg <= lookup_in_vlan_enable;
vlan_prio_reg <= lookup_in_vlan_prio;
timestamp_reg <= lookup_in_timestamp;
lookup_in_ready <= '1';
end if;
end if;
end if;
end process;
-- handles access to the internal registers needed for lookup
internal_reg_p : process (clk) -- to be done
begin
if clk'event and clk = '1' then
if reset = '1' then
lower_reg <= (others => '0');
upper_reg <= (others => '0');
default_reg <= (others => '0');
median_reg <= (others => '0');
else
lower_reg <= lower_reg;
upper_reg <= upper_reg;
default_reg <= default_reg;
median_reg <= median_reg;
if read_base_sig = '1' then -- read inital values from base configuration
lower_reg <= mem_lower_sig;
upper_reg <= mem_upper_sig;
default_reg <= mem_default_sig;
median_reg <= median_sig;
elsif update_sig = '1' then -- update registers according to remaining search space
lower_reg <= lower_sig;
upper_reg <= upper_sig;
median_reg <= median_sig;
end if;
end if;
end if;
end process;
-- assign next memory search address: median address in the remaining address search space
median_sig <= upper_add_lower_by2_f(upper_sig, lower_sig);
-- updates the output value registers (ports, priority and skip)
output_reg_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
ports_reg <= (others => '0');
prio_reg <= (others => '0');
skip_frame_reg <= '0';
else
ports_reg <= ports_reg;
prio_reg <= prio_reg;
skip_frame_reg <= skip_frame_reg;
if read_default_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0';
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= mem_skip_frame_sig;
elsif read_lookup_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0'; -- comment for loopback functionality
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= '0';
end if;
end if;
end if;
end process;
-- sets the output valid bit
output_valid_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
lookup_out_valid <= '0';
else
lookup_out_valid <= '0';
if lookup_valid_sig = '1' then
lookup_out_valid <= '1';
end if;
end if;
end if;
end process;
-- other outputs
lookup_out_ports <= ports_reg;
lookup_out_prio <= prio_reg;
lookup_out_skip <= skip_frame_reg;
lookup_out_timestamp <= timestamp_reg;
end rtl;
|
-------------------------------------------------------------------------------
-- $Id: park_lock_logic.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- park_lock_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: park_lock_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the grant_last_register logic, the park
-- logic, and the grant_logic which determines the final grant
-- signal to the Masters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/24/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- Modified the code so that the arbitration cycle and/or the internal grant
-- register enables are based off the external grants, i.e., grants output
-- to the bus taking into account buslock and park.
-- This file now generates Any_mgrant which indicates when any external grant
-- is asserted and Bus_park which indicates when the bus is parked. Also,
-- OPB_buslock now gates the internal grant signals and bus parking.
-- ~~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
-- Package file that contains constant definition for RESET_ACTIVE and function
-- pad_4
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of Masters
-- C_NUM_MID_BITS -- number of bits required for master IDs
-- C_PARK -- parking supported
-- C_REG_GRANTS -- register grant outputs
--
-- Definition of Ports:
--
-- input Arb_cycle -- Valid arbitration cycle
-- input OPB_buslock -- Bus is locked
--
-- -- Control register interface
-- input Park_master_notlast -- Park on Master not last
-- input Park_master_id -- Master ID to park on
-- input Park_enable -- Enable parking
--
-- -- Intermediate grant signals from arbitration logic
-- input Grant
--
-- -- Master request signals
-- input M_request
--
-- -- Final Master grant signals
-- output Opb_mgrant -- output grants to masters
-- -- may be registered if C_REG_GRANTS=true
-- output MGrant -- cmb grant outputs to priority reg logic
-- output MGrant_n -- cmb active low grant signals to
-- -- priority reg logic
--
-- -- Clock and reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity park_lock_logic is
generic( C_NUM_MASTERS : integer := 8;
C_NUM_MID_BITS : integer := 3;
C_PARK : boolean := false;
C_REG_GRANTS : boolean := true );
port (
Arb_cycle : in std_logic;
OPB_buslock : in std_logic;
Park_master_notlast : in std_logic;
Park_master_id : in std_logic_vector(0 to C_NUM_MID_BITS-1);
Park_enable : in std_logic;
Grant : in std_logic_vector(0 to C_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
Bus_park : out std_logic;
Any_mgrant : out std_logic;
OPB_Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
MGrant_n : out std_logic_vector(0 to C_NUM_MASTERS-1);
Clk : in std_logic;
Rst : in std_logic
);
end park_lock_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of park_lock_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- pad number of masters(requests) and Park_enable to nearest multiple of 4
constant NUM_REQ_PAD : integer := pad_4(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- 1-hot register indicating which master was granted the bus
signal grant_last_reg : std_logic_vector(0 to C_NUM_MASTERS-1);
-- Signal indicating that a grant was asserted
signal any_grant : std_logic;
-- 1-hot bus indicating which master has locked the bus
signal locked : std_logic_vector(0 to C_NUM_MASTERS-1);
-- 1-hot bus indicating which master the bus is parked on
signal park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_d1 : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_fe : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signal indicating if other masters are parked
signal others_park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signals indicating if other masters are requesting the bus
signal pend_req_cmb : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal pend_req : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- indicates if any master is requesting the bus
signal any_request : std_logic_vector(0 to 0) := (others => '0');
-- internal grant signals
signal mgrant_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_n_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_reg_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Xilinx primitives are used to generate the PARK signals
-- OR_BITS is used to OR all of the Grant signals so that the Grant_last_reg
-- can be updated.
-- OR_GATE is used to determine if there are any pending requests for the
-- park logic and to determine if any master is parked
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- GRANT_LAST_REGISTER registers the grant signals for use in determining
-- parking and locking.
-- This register is clock enabled by the OR of all the Master grant signals,
-- i.e. only register the grant signals when a new grant has been issued.
-- Note that the GRANT_LAST_REGISTER uses registered internal grant signals
-- when design is configured for registered grant outputs. It uses combinational
-- grant signals when configured for combinational internal grant outputs
-------------------------------------------------------------------------------
REGGRNTS_LASTGRNT: if C_REG_GRANTS generate
begin
-- use internal registered grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_reg_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_reg_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate REGGRNTS_LASTGRNT;
CMBGRNTS_LASTGRNT: if not(C_REG_GRANTS) generate
begin
-- use internal combinational grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate CMBGRNTS_LASTGRNT;
-------------------------------------------------------------------------------
-- LOCK signals indicate which Master (if any) has locked the bus. Only a Master
-- which has been granted the bus and is still requesting can lock it.
-------------------------------------------------------------------------------
LOCK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
locked(i) <= '1' when grant_last_reg(i) = '1' and OPB_buslock = '1'
else '0';
end generate LOCK_GEN;
-------------------------------------------------------------------------------
-- PARK signals indicate which Master to park the bus on based on the Park
-- Enable, Park Master Not Last, and Park Master ID bits in the Control
-- Register. This code is only implemented if C_PARK=true indicating that
-- parking is supported. If C_PARK=false, the park bus and all OPB park signals
-- stay at their default values of 0.
-------------------------------------------------------------------------------
PARKLOGIC_GEN: if C_PARK generate
-- For each master, must determine if there are any other requests and if parking is enabled
PENDREQ_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
PENDREQ_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (or_gate_input,pend_req(i to i));
end generate PENDREQ_GEN;
-- If parking is enabled and there are no pending requests, then determine
-- which master to park on based on the PMNL bit.
-- If park on master not last = 0, then park on last master, i.e, park =
-- grant_last_reg. Otherwise, park on master whose ID is set in control register.
-- Register the master's park signals
PARK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal park_or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
PARK_PROCESS: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park(i) <= '0';
elsif pend_req(i) = '0' and Park_enable = '1' then
if Park_master_notlast = '1' then
if Park_master_id = conv_std_logic_vector(i, C_NUM_MID_BITS) then
park(i) <= '1';
else
park(i) <= '0';
end if;
else
park(i) <= grant_last_reg(i);
end if;
else
park(i) <= '0';
end if;
end if;
end process PARK_PROCESS;
-- When the grant outputs are registered, the parked master's grant won't negate
-- until a clock after parking is disabled. Since the park bus is registered,
-- the grant signal must negate as soon as possible after the park bus negates,
-- therefore, use the falling edge of each masters' park to asynchronously reset
-- that master's OPB_MGrant register.
PARK_D1_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park_d1(i) <= '0';
else
park_d1(i) <= park(i);
end if;
end if;
end process PARK_D1_PROCESS;
park_fe(i) <= '1' when park(i) = '0' and park_d1(i) = '1'
else '0';
-- determine if other masters are parked so that the grant from the arbitration
-- logic can be properly gated.
OR_ALLPARK_BUT_SELF_PROCESS: process (park) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
park_or_gate_input(j) <= park(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
park_or_gate_input(j-1) <= park(j);
end loop;
end process OR_ALLPARK_BUT_SELF_PROCESS;
OTHERSPARK_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (park_or_gate_input,others_park(i to i));
end generate PARK_GEN;
-- determine if parked on any master
OR_PARK_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => park,
Sig => '0',
Or_out => Bus_park
);
end generate PARKLOGIC_GEN;
NOPARK_GEN: if not(C_PARK) generate
Bus_park <= '0';
park <= (others => '0');
others_park <= (others => '0');
park_fe <= (others => '0');
end generate NOPARK_GEN;
-------------------------------------------------------------------------------
-- GRANT_LOGIC determines the final Master grant signals based on the park/lock
-- signals and the intermediate grant signals from the arbitration logic.
-- The MGrant signals are always combinatorial and are used by the priority
-- register logic.
-------------------------------------------------------------------------------
GRANT_GEN: for i in 0 to C_NUM_MASTERS-1 generate
mgrant_i(i) <= '1' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '0';
mgrant_n_i(i) <= '0' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '1';
-- Register the grant signals if registered grant outputs
-- reset this register with park_fe
REGGRNT_GEN: if (C_REG_GRANTS) generate
REGGRNT_PROCESS: process (Clk, park_fe(i))
begin
-- asynchronously reset when park negates
if park_fe(i) = '1' then
mgrant_reg_i(i) <= '0';
elsif Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
mgrant_reg_i(i) <= '0';
else
mgrant_reg_i(i) <= mgrant_i(i);
end if;
end if;
end process REGGRNT_PROCESS;
end generate REGGRNT_GEN;
end generate GRANT_GEN;
-------------------------------------------------------------------------------
-- Assign internal signals to outputs
-- Master grant signal outputs are registered or combinatorial based on the
-- C_REG_GRANTS parameter.
-------------------------------------------------------------------------------
MGrant <= mgrant_i;
MGrant_n <= mgrant_n_i;
Any_mgrant <= any_grant;
REGGRANT_GEN: if C_REG_GRANTS generate
OPB_MGrant <= mgrant_reg_i;
end generate REGGRANT_GEN;
CMBGRANT_GEN: if not(C_REG_GRANTS) generate
OPB_MGrant <= mgrant_i;
end generate CMBGRANT_GEN;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: park_lock_logic.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- park_lock_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
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-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: park_lock_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the grant_last_register logic, the park
-- logic, and the grant_logic which determines the final grant
-- signal to the Masters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/24/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- Modified the code so that the arbitration cycle and/or the internal grant
-- register enables are based off the external grants, i.e., grants output
-- to the bus taking into account buslock and park.
-- This file now generates Any_mgrant which indicates when any external grant
-- is asserted and Bus_park which indicates when the bus is parked. Also,
-- OPB_buslock now gates the internal grant signals and bus parking.
-- ~~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
-- Package file that contains constant definition for RESET_ACTIVE and function
-- pad_4
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of Masters
-- C_NUM_MID_BITS -- number of bits required for master IDs
-- C_PARK -- parking supported
-- C_REG_GRANTS -- register grant outputs
--
-- Definition of Ports:
--
-- input Arb_cycle -- Valid arbitration cycle
-- input OPB_buslock -- Bus is locked
--
-- -- Control register interface
-- input Park_master_notlast -- Park on Master not last
-- input Park_master_id -- Master ID to park on
-- input Park_enable -- Enable parking
--
-- -- Intermediate grant signals from arbitration logic
-- input Grant
--
-- -- Master request signals
-- input M_request
--
-- -- Final Master grant signals
-- output Opb_mgrant -- output grants to masters
-- -- may be registered if C_REG_GRANTS=true
-- output MGrant -- cmb grant outputs to priority reg logic
-- output MGrant_n -- cmb active low grant signals to
-- -- priority reg logic
--
-- -- Clock and reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity park_lock_logic is
generic( C_NUM_MASTERS : integer := 8;
C_NUM_MID_BITS : integer := 3;
C_PARK : boolean := false;
C_REG_GRANTS : boolean := true );
port (
Arb_cycle : in std_logic;
OPB_buslock : in std_logic;
Park_master_notlast : in std_logic;
Park_master_id : in std_logic_vector(0 to C_NUM_MID_BITS-1);
Park_enable : in std_logic;
Grant : in std_logic_vector(0 to C_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
Bus_park : out std_logic;
Any_mgrant : out std_logic;
OPB_Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
MGrant_n : out std_logic_vector(0 to C_NUM_MASTERS-1);
Clk : in std_logic;
Rst : in std_logic
);
end park_lock_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of park_lock_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- pad number of masters(requests) and Park_enable to nearest multiple of 4
constant NUM_REQ_PAD : integer := pad_4(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- 1-hot register indicating which master was granted the bus
signal grant_last_reg : std_logic_vector(0 to C_NUM_MASTERS-1);
-- Signal indicating that a grant was asserted
signal any_grant : std_logic;
-- 1-hot bus indicating which master has locked the bus
signal locked : std_logic_vector(0 to C_NUM_MASTERS-1);
-- 1-hot bus indicating which master the bus is parked on
signal park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_d1 : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_fe : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signal indicating if other masters are parked
signal others_park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signals indicating if other masters are requesting the bus
signal pend_req_cmb : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal pend_req : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- indicates if any master is requesting the bus
signal any_request : std_logic_vector(0 to 0) := (others => '0');
-- internal grant signals
signal mgrant_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_n_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_reg_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Xilinx primitives are used to generate the PARK signals
-- OR_BITS is used to OR all of the Grant signals so that the Grant_last_reg
-- can be updated.
-- OR_GATE is used to determine if there are any pending requests for the
-- park logic and to determine if any master is parked
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- GRANT_LAST_REGISTER registers the grant signals for use in determining
-- parking and locking.
-- This register is clock enabled by the OR of all the Master grant signals,
-- i.e. only register the grant signals when a new grant has been issued.
-- Note that the GRANT_LAST_REGISTER uses registered internal grant signals
-- when design is configured for registered grant outputs. It uses combinational
-- grant signals when configured for combinational internal grant outputs
-------------------------------------------------------------------------------
REGGRNTS_LASTGRNT: if C_REG_GRANTS generate
begin
-- use internal registered grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_reg_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_reg_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate REGGRNTS_LASTGRNT;
CMBGRNTS_LASTGRNT: if not(C_REG_GRANTS) generate
begin
-- use internal combinational grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate CMBGRNTS_LASTGRNT;
-------------------------------------------------------------------------------
-- LOCK signals indicate which Master (if any) has locked the bus. Only a Master
-- which has been granted the bus and is still requesting can lock it.
-------------------------------------------------------------------------------
LOCK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
locked(i) <= '1' when grant_last_reg(i) = '1' and OPB_buslock = '1'
else '0';
end generate LOCK_GEN;
-------------------------------------------------------------------------------
-- PARK signals indicate which Master to park the bus on based on the Park
-- Enable, Park Master Not Last, and Park Master ID bits in the Control
-- Register. This code is only implemented if C_PARK=true indicating that
-- parking is supported. If C_PARK=false, the park bus and all OPB park signals
-- stay at their default values of 0.
-------------------------------------------------------------------------------
PARKLOGIC_GEN: if C_PARK generate
-- For each master, must determine if there are any other requests and if parking is enabled
PENDREQ_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
PENDREQ_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (or_gate_input,pend_req(i to i));
end generate PENDREQ_GEN;
-- If parking is enabled and there are no pending requests, then determine
-- which master to park on based on the PMNL bit.
-- If park on master not last = 0, then park on last master, i.e, park =
-- grant_last_reg. Otherwise, park on master whose ID is set in control register.
-- Register the master's park signals
PARK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal park_or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
PARK_PROCESS: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park(i) <= '0';
elsif pend_req(i) = '0' and Park_enable = '1' then
if Park_master_notlast = '1' then
if Park_master_id = conv_std_logic_vector(i, C_NUM_MID_BITS) then
park(i) <= '1';
else
park(i) <= '0';
end if;
else
park(i) <= grant_last_reg(i);
end if;
else
park(i) <= '0';
end if;
end if;
end process PARK_PROCESS;
-- When the grant outputs are registered, the parked master's grant won't negate
-- until a clock after parking is disabled. Since the park bus is registered,
-- the grant signal must negate as soon as possible after the park bus negates,
-- therefore, use the falling edge of each masters' park to asynchronously reset
-- that master's OPB_MGrant register.
PARK_D1_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park_d1(i) <= '0';
else
park_d1(i) <= park(i);
end if;
end if;
end process PARK_D1_PROCESS;
park_fe(i) <= '1' when park(i) = '0' and park_d1(i) = '1'
else '0';
-- determine if other masters are parked so that the grant from the arbitration
-- logic can be properly gated.
OR_ALLPARK_BUT_SELF_PROCESS: process (park) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
park_or_gate_input(j) <= park(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
park_or_gate_input(j-1) <= park(j);
end loop;
end process OR_ALLPARK_BUT_SELF_PROCESS;
OTHERSPARK_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (park_or_gate_input,others_park(i to i));
end generate PARK_GEN;
-- determine if parked on any master
OR_PARK_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => park,
Sig => '0',
Or_out => Bus_park
);
end generate PARKLOGIC_GEN;
NOPARK_GEN: if not(C_PARK) generate
Bus_park <= '0';
park <= (others => '0');
others_park <= (others => '0');
park_fe <= (others => '0');
end generate NOPARK_GEN;
-------------------------------------------------------------------------------
-- GRANT_LOGIC determines the final Master grant signals based on the park/lock
-- signals and the intermediate grant signals from the arbitration logic.
-- The MGrant signals are always combinatorial and are used by the priority
-- register logic.
-------------------------------------------------------------------------------
GRANT_GEN: for i in 0 to C_NUM_MASTERS-1 generate
mgrant_i(i) <= '1' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '0';
mgrant_n_i(i) <= '0' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '1';
-- Register the grant signals if registered grant outputs
-- reset this register with park_fe
REGGRNT_GEN: if (C_REG_GRANTS) generate
REGGRNT_PROCESS: process (Clk, park_fe(i))
begin
-- asynchronously reset when park negates
if park_fe(i) = '1' then
mgrant_reg_i(i) <= '0';
elsif Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
mgrant_reg_i(i) <= '0';
else
mgrant_reg_i(i) <= mgrant_i(i);
end if;
end if;
end process REGGRNT_PROCESS;
end generate REGGRNT_GEN;
end generate GRANT_GEN;
-------------------------------------------------------------------------------
-- Assign internal signals to outputs
-- Master grant signal outputs are registered or combinatorial based on the
-- C_REG_GRANTS parameter.
-------------------------------------------------------------------------------
MGrant <= mgrant_i;
MGrant_n <= mgrant_n_i;
Any_mgrant <= any_grant;
REGGRANT_GEN: if C_REG_GRANTS generate
OPB_MGrant <= mgrant_reg_i;
end generate REGGRANT_GEN;
CMBGRANT_GEN: if not(C_REG_GRANTS) generate
OPB_MGrant <= mgrant_i;
end generate CMBGRANT_GEN;
end implementation;
|
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RandomNumberw_counter_Tb is
end RandomNumberw_counter_Tb;
-- Testes unitários para a sincronização das entidade RandomNumber e counter9999
architecture Stimulus of RandomNumberw_counter_Tb is
signal s_reset, s_stop, s_clock, s_count, s_resetOut : std_logic;
signal s_random0, s_random3,s_random2,s_random1 : std_logic_vector(3 downto 0);
begin
uutrandom: entity work.RandomNumber(Behavioral)
port map(clock => s_clock,
stop_signal => s_stop,
reset => s_reset,
count => s_count,
resetOut => s_resetOut);
uutcounter: entity work.Counter9999(Behavioral)
port map(clk => s_clock,
reset => s_resetOut,
enable => s_count,
count0 => s_random0,
count1 => s_random1,
count2 => s_random2,
count3 => s_random3);
clk_proc:process
begin
s_clock <= '1';
wait for 13 ns;
s_clock <= '0';
wait for 13 ns;
end process;
comb_process:process
begin
s_stop <= '0';
s_reset <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 25 ns;
s_stop <= '0';
wait for 25 ns;
s_reset <= '1';
wait for 25 ns;
end process;
end Stimulus; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc673.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00673ent IS
END c03s04b01x00p23n01i00673ent;
ARCHITECTURE c03s04b01x00p23n01i00673arch OF c03s04b01x00p23n01i00673ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
type FT is file of DATE;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.51";
-- Declare a variable into which we will read.
constant CON : DATE := ( 1,1,1 );
variable VAR : DATE;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00673"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00673 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00673arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc673.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00673ent IS
END c03s04b01x00p23n01i00673ent;
ARCHITECTURE c03s04b01x00p23n01i00673arch OF c03s04b01x00p23n01i00673ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
type FT is file of DATE;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.51";
-- Declare a variable into which we will read.
constant CON : DATE := ( 1,1,1 );
variable VAR : DATE;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00673"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00673 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00673arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc673.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00673ent IS
END c03s04b01x00p23n01i00673ent;
ARCHITECTURE c03s04b01x00p23n01i00673arch OF c03s04b01x00p23n01i00673ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
type FT is file of DATE;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.51";
-- Declare a variable into which we will read.
constant CON : DATE := ( 1,1,1 );
variable VAR : DATE;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00673"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00673 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00673arch;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
ival : in std_logic_vector(31 downto 0)
);
end clk;
architecture rtl of clk is
signal foo : std_logic_vector(10+3 downto 0);
signal baz : std_logic_vector(2 downto 0);
signal egg : std_logic_vector(4 to 7-1);
begin
pfoo: process(reset, sysclk)
begin
if( reset /= '0' ) then
foo <= (others => '1');
elsif( sysclk'event and sysclk = '1' ) then
foo <= ival(31 downto 31-(10+3));
end if;
end process;
pbaz: process(preset, dsysclk)
begin
if( preset /= '1' ) then
baz <= (others => '0');
elsif( dsysclk'event and dsysclk = '0' ) then
baz <= ival(2 downto 0);
end if;
end process;
pegg: process(qreset, esysclk)
begin
if( qreset /= '1' ) then
egg <= (others => '0');
elsif( esysclk'event and esysclk = '0' ) then
egg <= ival(6 downto 4);
end if;
end process;
end rtl;
|
-- NEED RESULT: *** An assertion follows with severity level NOTE
-- NEED RESULT: An assertion with severity NOTE
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00322
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00322)
-- ENT00322_Test_Bench(ARCH00322_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match the comment messages output.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00322 of E00000 is
signal Dummy : Boolean := false;
begin
P1 :
process ( Dummy )
begin
print ("*** An assertion follows with severity level NOTE") ;
end process ;
assert Dummy
report "An assertion with severity NOTE"
severity Severity_Level'Left ;
end ARCH00322 ;
entity ENT00322_Test_Bench is
end ENT00322_Test_Bench ;
architecture ARCH00322_Test_Bench of ENT00322_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00322 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00322_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity four_bit_adder is
port(
cin : in vl_logic;
A : in vl_logic_vector(3 downto 0);
B : in vl_logic_vector(3 downto 0);
sum : out vl_logic_vector(3 downto 0);
cout : out vl_logic;
c1 : out vl_logic;
c2 : out vl_logic;
c3 : out vl_logic
);
end four_bit_adder;
|
-------------------------------------------------------------------------------
-- Title : Instruction Tracker
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Instruction_Tracker.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-07
-- Last update: 2016-12-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Each in-flight instruction in the pipeline tracker
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-07 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
use work.instruction_defs.all;
use work.instruction_record.all;
-------------------------------------------------------------------------------
entity Instruction_Tracker is
generic (
ADDR_WIDTH : integer
);
port (
clk : in std_logic;
rst : in std_logic;
-- Input instruction recorder
--- Acquire enable, (i_pc1 and i_pc1_instr_tag will be linked together).
i_record_pc1_req : in std_logic;
--- Acquire enable, (i_pc2 and i_pc2_instr_tag will be linked together).
i_record_pc2_req : in std_logic;
i_pc1 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_pc2 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_pc1_instr_tag : in instr_tag_t;
i_pc2_instr_tag : in instr_tag_t;
i_pc1_predict_next_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_pc2_predict_next_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Retire instruction recorder
i_commited_instr_tag : in instr_tag_t;
i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Misprediction computation
o_commited_instr_record : out instr_record;
o_commited_instr_tag : out instr_tag_t;
-- Branch prediction module
i_btb_instr_tag : in instr_tag_t;
o_btb_instr_record : out instr_record -- available on next cycle
);
end entity Instruction_Tracker;
-------------------------------------------------------------------------------
architecture rtl of Instruction_Tracker is
subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal irecords : instr_records;
signal commited_instr_record : instr_record;
begin -- architecture rtl
itrack_recorder : process(clk, rst) is
begin
if rst = '1' then
elsif rising_edge(clk) then
if i_record_pc1_req = '1' then
record_one_instr(i_pc1, i_pc1_predict_next_pc, i_pc1_instr_tag,
irecords);
end if;
if i_record_pc2_req = '1' then
record_one_instr(i_pc2, i_pc2_predict_next_pc, i_pc2_instr_tag,
irecords);
end if;
if i_commited_instr_tag.valid then
retire_one_instr(i_commited_instr_tag, irecords);
end if;
end if;
end process itrack_recorder;
-- Misprediction forwarding
commited_instr_record <= get_record(i_commited_instr_tag, irecords);
o_commited_instr_record <= commited_instr_record;
-- Commited instruction forwarding
o_commited_instr_tag <= i_commited_instr_tag;
end architecture rtl;
-------------------------------------------------------------------------------
|
-- file: clocks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____10.000______0.000______50.0______439.530____196.077
-- CLK_OUT2___133.333______0.000______50.0______230.136____196.077
-- CLK_OUT3___133.333____180.000______50.0______230.136____196.077
-- CLK_OUT4____25.000______0.000______50.0______364.543____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocks is
port
(-- Clock in ports
clkin : in std_logic;
-- Clock out ports
clk10mhz : out std_logic;
clk133mhz : out std_logic;
clk133mhzinv : out std_logic;
clk25mhz : out std_logic
);
end clocks;
architecture xilinx of clocks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocks,clk_wiz_v3_6,{component_name=clocks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clkin);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 80,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 6,
CLKOUT2_PHASE => 180.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 32,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clk10mhz,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk133mhz,
I => clkout1);
clkout3_buf : BUFG
port map
(O => clk133mhzinv,
I => clkout2);
clkout4_buf : BUFG
port map
(O => clk25mhz,
I => clkout3);
end xilinx;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccos_s5
-- VHDL created on Thu Feb 28 17:20:47 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid11_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid12_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid13_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid14_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid15_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal cstBiasM2_uid16_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasP1_uid17_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid45_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid48_fpArccosXTest_q : std_logic_vector (12 downto 0);
signal pi_uid85_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid91_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal pi2_uid102_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid118_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expSum_uid352_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid353_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (10 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_a : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_pr : UNSIGNED (47 downto 0);
signal prod_uid355_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid380_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid296_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid297_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid298_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid440_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid441_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid442_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid456_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid457_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid458_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (22 downto 0);
signal ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q : signal is true;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q : signal is true;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid18_uid54_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid102_uid103_fpArccosXTest_q : std_logic_vector (27 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid381_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid383_arcsinL_uid78_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid114_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid128_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid6_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal singX_uid8_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal singX_uid8_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid24_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid24_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid26_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid26_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid28_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid29_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid36_fpArccosXTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid36_fpArccosXTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid36_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid36_fpArccosXTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid37_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid37_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid38_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid43_fpArccosXTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid43_fpArccosXTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid43_fpArccosXTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid43_fpArccosXTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid44_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal oMy_uid54_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal oMy_uid54_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal oMy_uid54_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expL_uid58_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expL_uid58_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expL_uid58_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srVal_uid67_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srVal_uid67_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid86_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid86_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid92_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid103_fpArccosXTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid103_fpArccosXTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid103_fpArccosXTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid125_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid125_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid129_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid131_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid169_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid176_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid190_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid329_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid345_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid387_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid388_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid393_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid399_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal piF_uid119_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal piF_uid119_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid122_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid122_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid362_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid72_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid130_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal concExc_uid398_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal R_uid411_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid42_uid42_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid33_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid46_fpArccosXTest_b : std_logic_vector (5 downto 0);
signal l_uid56_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal l_uid56_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid60_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid60_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid68_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid68_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid88_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid89_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid90_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid93_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal normBit_uid105_fpArccosXTest_in : std_logic_vector (27 downto 0);
signal normBit_uid105_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid106_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid109_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal sR_uid132_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (18 downto 0);
signal vStage_uid178_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal vStage_uid185_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (32 downto 0);
signal vStage_uid199_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid301_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid302_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid307_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid308_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid445_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid446_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid451_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid452_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid461_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid462_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid467_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid468_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid299_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid459_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid79_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid81_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid49_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid31_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid31_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid40_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid47_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid47_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal vStage_uid171_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (2 downto 0);
signal fpL_uid61_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid94_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid107_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid110_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal cStage_uid179_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid183_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid186_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid197_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid200_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid331_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid335_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid347_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid303_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid309_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid447_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid453_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid463_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid469_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid80_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid82_fpArccosXTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid135_fxpX_uid50_fpArccosXTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid138_fxpX_uid50_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid32_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid32_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid41_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal cStage_uid172_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid216_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid218_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid96_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid96_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid112_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal sticky_uid367_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal s1_uid301_uid304_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid307_uid310_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid445_uid448_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid451_uid454_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid461_uid464_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid467_uid470_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid83_fpArccosXTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid35_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid35_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid126_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid121_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid124_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid116_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid116_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal inputIsMax_uid51_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid51_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal y_uid52_fpArccosXTest_in : std_logic_vector (35 downto 0);
signal y_uid52_fpArccosXTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal vStage_uid192_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal vStage_uid206_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid71_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid71_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid351_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal lrs_uid369_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid74_fpArccosXTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid101_fpArccosXTest_b : std_logic_vector (26 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in : std_logic_vector (28 downto 0);
signal fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid127_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid127_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid120_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid123_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal firstPath_uid53_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid53_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid98_fpArccosXTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid98_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid99_fpArccosXTest_b : std_logic_vector (14 downto 0);
signal cStage_uid193_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid204_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal cStage_uid207_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid113_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid117_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal yT1_uid443_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid443_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (34 downto 0);
signal vCount_uid209_fpLOut1_uid57_fpArccosXTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid372_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid76_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid59_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal join_uid255_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q : std_logic_vector (26 downto 0);
signal roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (25 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal expY_uid313_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signY_uid315_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal fracY_uid318_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid64_fpArccosXTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid66_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid314_arcsinL_uid78_fpArccosXTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q : std_logic_vector (3 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid65_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q : std_logic_vector (23 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid9_fpArccosXTest(CONSTANT,8)
cstAllOWE_uid9_fpArccosXTest_q <= "11111111";
--cstBiasP1_uid17_fpArccosXTest(CONSTANT,16)
cstBiasP1_uid17_fpArccosXTest_q <= "10000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable(LOGICAL,1194)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q <= not ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_a;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor(LOGICAL,1222)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q <= not (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_a or ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_b);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top(CONSTANT,1218)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q <= "011001";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp(LOGICAL,1219)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_mem_top_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q <= "1" when ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_a = ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_b else "0";
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg(REG,1220)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena(REG,1223)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_nor_q = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd(LOGICAL,1224)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_sticky_ena_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_a and ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest(CONSTANT,161)
rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q <= "000";
--RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest(BITSELECT,160)@1
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_in(36 downto 3);
--rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest(BITJOIN,162)@1
rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3Pad3_uid162_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto3_uid161_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest(CONSTANT,158)
rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q <= "00";
--RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest(BITSELECT,157)@1
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_in(36 downto 2);
--rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest(BITJOIN,159)@1
rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage136dto2_uid158_fxpX_uid50_fpArccosXTest_b;
--RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest(BITSELECT,154)@1
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b <= RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_in(36 downto 1);
--rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest(BITJOIN,156)@1
rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q <= GND_q & RightShiftStage136dto1_uid155_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest(CONSTANT,150)
rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q <= "000000000000";
--rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest(CONSTANT,140)
rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest(CONSTANT,138)
rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q <= "00000000000000000000000000000000";
--X36dto32_uid138_fxpX_uid50_fpArccosXTest(BITSELECT,137)@0
X36dto32_uid138_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto32_uid138_fxpX_uid50_fpArccosXTest_b <= X36dto32_uid138_fxpX_uid50_fpArccosXTest_in(36 downto 32);
--rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest(BITJOIN,139)@0
rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q & X36dto32_uid138_fxpX_uid50_fpArccosXTest_b;
--rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest(CONSTANT,135)
rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q <= "0000000000000000";
--X36dto16_uid135_fxpX_uid50_fpArccosXTest(BITSELECT,134)@0
X36dto16_uid135_fxpX_uid50_fpArccosXTest_in <= oFracXExt_uid49_fpArccosXTest_q;
X36dto16_uid135_fxpX_uid50_fpArccosXTest_b <= X36dto16_uid135_fxpX_uid50_fpArccosXTest_in(36 downto 16);
--rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest(BITJOIN,136)@0
rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X36dto16_uid135_fxpX_uid50_fpArccosXTest_b;
--fracX_uid7_fpArccosXTest(BITSELECT,6)@0
fracX_uid7_fpArccosXTest_in <= a(22 downto 0);
fracX_uid7_fpArccosXTest_b <= fracX_uid7_fpArccosXTest_in(22 downto 0);
--oFracX_uid42_uid42_fpArccosXTest(BITJOIN,41)@0
oFracX_uid42_uid42_fpArccosXTest_q <= VCC_q & fracX_uid7_fpArccosXTest_b;
--cst01pWShift_uid48_fpArccosXTest(CONSTANT,47)
cst01pWShift_uid48_fpArccosXTest_q <= "0000000000000";
--oFracXExt_uid49_fpArccosXTest(BITJOIN,48)@0
oFracXExt_uid49_fpArccosXTest_q <= oFracX_uid42_uid42_fpArccosXTest_q & cst01pWShift_uid48_fpArccosXTest_q;
--shiftOutVal_uid45_fpArccosXTest(CONSTANT,44)
shiftOutVal_uid45_fpArccosXTest_q <= "100100";
--expX_uid6_fpArccosXTest(BITSELECT,5)@0
expX_uid6_fpArccosXTest_in <= a(30 downto 0);
expX_uid6_fpArccosXTest_b <= expX_uid6_fpArccosXTest_in(30 downto 23);
--cstBias_uid13_fpArccosXTest(CONSTANT,12)
cstBias_uid13_fpArccosXTest_q <= "01111111";
--shiftValuePre_uid44_fpArccosXTest(SUB,43)@0
shiftValuePre_uid44_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
shiftValuePre_uid44_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpArccosXTest_b);
shiftValuePre_uid44_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid44_fpArccosXTest_a) - UNSIGNED(shiftValuePre_uid44_fpArccosXTest_b));
shiftValuePre_uid44_fpArccosXTest_q <= shiftValuePre_uid44_fpArccosXTest_o(8 downto 0);
--fxpShifterBits_uid46_fpArccosXTest(BITSELECT,45)@0
fxpShifterBits_uid46_fpArccosXTest_in <= shiftValuePre_uid44_fpArccosXTest_q(5 downto 0);
fxpShifterBits_uid46_fpArccosXTest_b <= fxpShifterBits_uid46_fpArccosXTest_in(5 downto 0);
--cstBiasMwFMwShift_uid15_fpArccosXTest(CONSTANT,14)
cstBiasMwFMwShift_uid15_fpArccosXTest_q <= "001011100";
--shiftValue_uid43_fpArccosXTest(COMPARE,42)@0
shiftValue_uid43_fpArccosXTest_cin <= GND_q;
shiftValue_uid43_fpArccosXTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid15_fpArccosXTest_q(8)) & cstBiasMwFMwShift_uid15_fpArccosXTest_q) & '0';
shiftValue_uid43_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid6_fpArccosXTest_b) & shiftValue_uid43_fpArccosXTest_cin(0);
shiftValue_uid43_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid43_fpArccosXTest_a) - SIGNED(shiftValue_uid43_fpArccosXTest_b));
shiftValue_uid43_fpArccosXTest_n(0) <= not shiftValue_uid43_fpArccosXTest_o(11);
--shiftValue_uid47_fpArccosXTest(MUX,46)@0
shiftValue_uid47_fpArccosXTest_s <= shiftValue_uid43_fpArccosXTest_n;
shiftValue_uid47_fpArccosXTest: PROCESS (shiftValue_uid47_fpArccosXTest_s, en, fxpShifterBits_uid46_fpArccosXTest_b, shiftOutVal_uid45_fpArccosXTest_q)
BEGIN
CASE shiftValue_uid47_fpArccosXTest_s IS
WHEN "0" => shiftValue_uid47_fpArccosXTest_q <= fxpShifterBits_uid46_fpArccosXTest_b;
WHEN "1" => shiftValue_uid47_fpArccosXTest_q <= shiftOutVal_uid45_fpArccosXTest_q;
WHEN OTHERS => shiftValue_uid47_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest(BITSELECT,141)@0
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q;
rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_in(5 downto 4);
--rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest(MUX,142)@0
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s <= rightShiftStageSel5Dto4_uid142_fxpX_uid50_fpArccosXTest_b;
rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s, en, oFracXExt_uid49_fpArccosXTest_q, rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q, rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= oFracXExt_uid49_fpArccosXTest_q;
WHEN "01" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx1_uid137_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx2_uid140_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= rightShiftStage0Idx3_uid141_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest(BITSELECT,149)@0
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_in(36 downto 12);
--rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest(BITJOIN,151)@0
rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx3Pad12_uid151_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto12_uid150_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5(REG,503)@0
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest(BITSELECT,146)@0
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_in(36 downto 8);
--rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest(BITJOIN,148)@0
rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & RightShiftStage036dto8_uid147_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4(REG,502)@0
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest(CONSTANT,144)
rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q <= "0000";
--RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest(BITSELECT,143)@0
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b <= RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_in(36 downto 4);
--rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest(BITJOIN,145)@0
rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage036dto4_uid144_fxpX_uid50_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3(REG,501)@0
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2(REG,500)@0
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q <= rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest(BITSELECT,152)@0
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1(REG,499)@0
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest(MUX,153)@1
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel3Dto2_uid153_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s, en, reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage0_uid143_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid146_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid149_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid152_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest(BITSELECT,163)@0
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in <= shiftValue_uid47_fpArccosXTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1(REG,504)@0
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q <= rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest(MUX,164)@1
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s <= reg_rightShiftStageSel1Dto0_uid164_fxpX_uid50_fpArccosXTest_0_to_rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_1_q;
rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest: PROCESS (rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s, en, rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q, rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_s IS
WHEN "00" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage1_uid154_fxpX_uid50_fpArccosXTest_q;
WHEN "01" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx1_uid157_fxpX_uid50_fpArccosXTest_q;
WHEN "10" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx2_uid160_fxpX_uid50_fpArccosXTest_q;
WHEN "11" => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= rightShiftStage2Idx3_uid163_fxpX_uid50_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid52_fpArccosXTest(BITSELECT,51)@1
y_uid52_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q(35 downto 0);
y_uid52_fpArccosXTest_b <= y_uid52_fpArccosXTest_in(35 downto 1);
--mAddr_uid98_fpArccosXTest(BITSELECT,97)@1
mAddr_uid98_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
mAddr_uid98_fpArccosXTest_b <= mAddr_uid98_fpArccosXTest_in(34 downto 27);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0(REG,578)@1
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q <= mAddr_uid98_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid442_arccosXO2TabGen_lutmem(DUALMEM,494)@2
memoryC2_uid442_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid442_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid442_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid442_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid442_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid442_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid442_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid442_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid442_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid442_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid442_arccosXO2TabGen_lutmem_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1(REG,580)@4
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q <= memoryC2_uid442_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid99_fpArccosXTest(BITSELECT,98)@1
mPPolyEval_uid99_fpArccosXTest_in <= y_uid52_fpArccosXTest_b(26 downto 0);
mPPolyEval_uid99_fpArccosXTest_b <= mPPolyEval_uid99_fpArccosXTest_in(26 downto 12);
--yT1_uid443_arccosXO2PolyEval(BITSELECT,442)@1
yT1_uid443_arccosXO2PolyEval_in <= mPPolyEval_uid99_fpArccosXTest_b;
yT1_uid443_arccosXO2PolyEval_b <= yT1_uid443_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg(DELAY,1328)
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid443_arccosXO2PolyEval_b, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a(DELAY,1172)@1
ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0(REG,579)@4
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q <= ld_yT1_uid443_arccosXO2PolyEval_b_to_reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid478_pT1_uid444_arccosXO2PolyEval(MULT,477)@5
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b);
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_a <= reg_yT1_uid443_arccosXO2PolyEval_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_0_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_b <= reg_memoryC2_uid442_arccosXO2TabGen_lutmem_0_to_prodXY_uid478_pT1_uid444_arccosXO2PolyEval_1_q;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid478_pT1_uid444_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid478_pT1_uid444_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval(BITSELECT,478)@8
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in <= prodXY_uid478_pT1_uid444_arccosXO2PolyEval_q;
prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid446_arccosXO2PolyEval(BITSELECT,445)@8
highBBits_uid446_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b;
highBBits_uid446_arccosXO2PolyEval_b <= highBBits_uid446_arccosXO2PolyEval_in(12 downto 1);
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a(DELAY,1086)@2
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid98_fpArccosXTest_0_to_memoryC2_uid442_arccosXO2TabGen_lutmem_0_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1289)
ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_q, xout => ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid441_arccosXO2TabGen_lutmem(DUALMEM,493)@6
memoryC1_uid441_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid441_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid441_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC1_uid441_arccosXO2TabGen_lutmem_0_q_to_memoryC1_uid441_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC1_uid441_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid441_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid441_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid441_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid441_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid441_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid441_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid441_arccosXO2TabGen_lutmem_q <= memoryC1_uid441_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid447_arccosXO2PolyEval(ADD,446)@8
sumAHighB_uid447_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid441_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid441_arccosXO2TabGen_lutmem_q);
sumAHighB_uid447_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid446_arccosXO2PolyEval_b(11)) & highBBits_uid446_arccosXO2PolyEval_b);
sumAHighB_uid447_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid447_arccosXO2PolyEval_b));
sumAHighB_uid447_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid445_arccosXO2PolyEval(BITSELECT,444)@8
lowRangeB_uid445_arccosXO2PolyEval_in <= prodXYTruncFR_uid479_pT1_uid444_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid445_arccosXO2PolyEval_b <= lowRangeB_uid445_arccosXO2PolyEval_in(0 downto 0);
--s1_uid445_uid448_arccosXO2PolyEval(BITJOIN,447)@8
s1_uid445_uid448_arccosXO2PolyEval_q <= sumAHighB_uid447_arccosXO2PolyEval_q & lowRangeB_uid445_arccosXO2PolyEval_b;
--reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1(REG,583)@8
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q <= s1_uid445_uid448_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor(LOGICAL,1339)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q <= not (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_a or ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_b);
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top(CONSTANT,1335)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q <= "0100";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp(LOGICAL,1336)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_mem_top_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q <= "1" when ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_a = ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_b else "0";
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg(REG,1337)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena(REG,1340)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_nor_q = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd(LOGICAL,1341)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_sticky_ena_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_a and ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_b;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg(DELAY,1329)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => mPPolyEval_uid99_fpArccosXTest_b, xout => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt(COUNTER,1331)
-- every=1, low=0, high=4, step=1, init=1
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i = 3 THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i - 4;
ELSE
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_i,3));
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg(REG,1332)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux(MUX,1333)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s <= en;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux: PROCESS (ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q, ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem(DUALMEM,1330)
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_inputreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdreg_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_rdmux_q;
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq,
address_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_aa,
data_a => ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_ia
);
ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0(REG,582)@8
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q <= ld_mPPolyEval_uid99_fpArccosXTest_b_to_reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid481_pT2_uid450_arccosXO2PolyEval(MULT,480)@9
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b);
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_a <= reg_mPPolyEval_uid99_fpArccosXTest_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_0_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_b <= reg_s1_uid445_uid448_arccosXO2PolyEval_0_to_prodXY_uid481_pT2_uid450_arccosXO2PolyEval_1_q;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid481_pT2_uid450_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid481_pT2_uid450_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval(BITSELECT,481)@12
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in <= prodXY_uid481_pT2_uid450_arccosXO2PolyEval_q;
prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid452_arccosXO2PolyEval(BITSELECT,451)@12
highBBits_uid452_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b;
highBBits_uid452_arccosXO2PolyEval_b <= highBBits_uid452_arccosXO2PolyEval_in(24 downto 2);
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor(LOGICAL,1352)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_a or ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,1296)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q <= "0101";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,1297)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg(REG,1298)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena(REG,1353)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd(LOGICAL,1354)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1342)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid98_fpArccosXTest_b, xout => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,1292)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 4 THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,1293)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,1294)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem(DUALMEM,1343)
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0(REG,584)@9
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid98_fpArccosXTest_b_to_reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid440_arccosXO2TabGen_lutmem(DUALMEM,492)@10
memoryC0_uid440_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid440_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid440_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid98_fpArccosXTest_0_to_memoryC0_uid440_arccosXO2TabGen_lutmem_0_q;
memoryC0_uid440_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid440_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid440_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid440_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid440_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid440_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid440_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid440_arccosXO2TabGen_lutmem_q <= memoryC0_uid440_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid453_arccosXO2PolyEval(ADD,452)@12
sumAHighB_uid453_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid440_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid440_arccosXO2TabGen_lutmem_q);
sumAHighB_uid453_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid452_arccosXO2PolyEval_b(22)) & highBBits_uid452_arccosXO2PolyEval_b);
sumAHighB_uid453_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid453_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid453_arccosXO2PolyEval_b));
sumAHighB_uid453_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid451_arccosXO2PolyEval(BITSELECT,450)@12
lowRangeB_uid451_arccosXO2PolyEval_in <= prodXYTruncFR_uid482_pT2_uid450_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid451_arccosXO2PolyEval_b <= lowRangeB_uid451_arccosXO2PolyEval_in(1 downto 0);
--s2_uid451_uid454_arccosXO2PolyEval(BITJOIN,453)@12
s2_uid451_uid454_arccosXO2PolyEval_q <= sumAHighB_uid453_arccosXO2PolyEval_q & lowRangeB_uid451_arccosXO2PolyEval_b;
--fxpArccosX_uid101_fpArccosXTest(BITSELECT,100)@12
fxpArccosX_uid101_fpArccosXTest_in <= s2_uid451_uid454_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid101_fpArccosXTest_b <= fxpArccosX_uid101_fpArccosXTest_in(30 downto 4);
--reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1(REG,586)@12
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q <= fxpArccosX_uid101_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid102_fpArccosXTest(CONSTANT,101)
pi2_uid102_fpArccosXTest_q <= "110010010000111111011010101";
--pad_pi2_uid102_uid103_fpArccosXTest(BITJOIN,102)@12
pad_pi2_uid102_uid103_fpArccosXTest_q <= pi2_uid102_fpArccosXTest_q & GND_q;
--reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0(REG,585)@12
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q <= pad_pi2_uid102_uid103_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid103_fpArccosXTest(SUB,103)@13
path2Diff_uid103_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid102_uid103_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_0_q);
path2Diff_uid103_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid101_fpArccosXTest_0_to_path2Diff_uid103_fpArccosXTest_1_q);
path2Diff_uid103_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid103_fpArccosXTest_a) - UNSIGNED(path2Diff_uid103_fpArccosXTest_b));
path2Diff_uid103_fpArccosXTest_q <= path2Diff_uid103_fpArccosXTest_o(28 downto 0);
--path2NegCaseFPFrac_uid106_fpArccosXTest(BITSELECT,105)@13
path2NegCaseFPFrac_uid106_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(26 downto 0);
path2NegCaseFPFrac_uid106_fpArccosXTest_b <= path2NegCaseFPFrac_uid106_fpArccosXTest_in(26 downto 4);
--path2NegCaseFPL_uid107_fpArccosXTest(BITJOIN,106)@13
path2NegCaseFPL_uid107_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & path2NegCaseFPFrac_uid106_fpArccosXTest_b;
--path2NegCaseFPFrac_uid109_fpArccosXTest(BITSELECT,108)@13
path2NegCaseFPFrac_uid109_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(25 downto 0);
path2NegCaseFPFrac_uid109_fpArccosXTest_b <= path2NegCaseFPFrac_uid109_fpArccosXTest_in(25 downto 3);
--path2NegCaseFPS_uid110_fpArccosXTest(BITJOIN,109)@13
path2NegCaseFPS_uid110_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & path2NegCaseFPFrac_uid109_fpArccosXTest_b;
--normBit_uid105_fpArccosXTest(BITSELECT,104)@13
normBit_uid105_fpArccosXTest_in <= path2Diff_uid103_fpArccosXTest_q(27 downto 0);
normBit_uid105_fpArccosXTest_b <= normBit_uid105_fpArccosXTest_in(27 downto 27);
--path2NegCaseFP_uid112_fpArccosXTest(MUX,111)@13
path2NegCaseFP_uid112_fpArccosXTest_s <= normBit_uid105_fpArccosXTest_b;
path2NegCaseFP_uid112_fpArccosXTest: PROCESS (path2NegCaseFP_uid112_fpArccosXTest_s, en, path2NegCaseFPS_uid110_fpArccosXTest_q, path2NegCaseFPL_uid107_fpArccosXTest_q)
BEGIN
CASE path2NegCaseFP_uid112_fpArccosXTest_s IS
WHEN "0" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPS_uid110_fpArccosXTest_q;
WHEN "1" => path2NegCaseFP_uid112_fpArccosXTest_q <= path2NegCaseFPL_uid107_fpArccosXTest_q;
WHEN OTHERS => path2NegCaseFP_uid112_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid113_fpArccosXTest(BITSELECT,112)@12
path2PosCaseFPFraction_uid113_fpArccosXTest_in <= fxpArccosX_uid101_fpArccosXTest_b(25 downto 0);
path2PosCaseFPFraction_uid113_fpArccosXTest_b <= path2PosCaseFPFraction_uid113_fpArccosXTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a(DELAY,680)@12
ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid113_fpArccosXTest_b, xout => ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid114_fpArccosXTest(BITJOIN,113)@13
path2PosCaseFP_uid114_fpArccosXTest_q <= GND_q & cstBias_uid13_fpArccosXTest_q & ld_path2PosCaseFPFraction_uid113_fpArccosXTest_b_to_path2PosCaseFP_uid114_fpArccosXTest_a_q;
--singX_uid8_fpArccosXTest(BITSELECT,7)@0
singX_uid8_fpArccosXTest_in <= a;
singX_uid8_fpArccosXTest_b <= singX_uid8_fpArccosXTest_in(31 downto 31);
--ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b(DELAY,681)@0
ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid116_fpArccosXTest(MUX,115)@13
path2ResFP_uid116_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path2ResFP_uid116_fpArccosXTest_b_q;
path2ResFP_uid116_fpArccosXTest: PROCESS (path2ResFP_uid116_fpArccosXTest_s, en, path2PosCaseFP_uid114_fpArccosXTest_q, path2NegCaseFP_uid112_fpArccosXTest_q)
BEGIN
CASE path2ResFP_uid116_fpArccosXTest_s IS
WHEN "0" => path2ResFP_uid116_fpArccosXTest_q <= path2PosCaseFP_uid114_fpArccosXTest_q;
WHEN "1" => path2ResFP_uid116_fpArccosXTest_q <= path2NegCaseFP_uid112_fpArccosXTest_q;
WHEN OTHERS => path2ResFP_uid116_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid123_fpArccosXTest(BITSELECT,122)@13
Path2ResFP30dto23_uid123_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(30 downto 0);
Path2ResFP30dto23_uid123_fpArccosXTest_b <= Path2ResFP30dto23_uid123_fpArccosXTest_in(30 downto 23);
--reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3(REG,590)@13
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q <= Path2ResFP30dto23_uid123_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt(COUNTER,1214)
-- every=1, low=0, high=25, step=1, init=1
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i = 24 THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_eq = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i - 25;
ELSE
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_i,5));
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg(REG,1215)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux(MUX,1216)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s <= en;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux: PROCESS (ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
WHEN "1" => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem(DUALMEM,1213)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0 <= areset;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia <= reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq,
address_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_aa,
data_a => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_ia
);
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_iq(7 downto 0);
--ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg(DELAY,1212)
ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_mem_q, xout => ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest(BITSELECT,433)@39
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest(BITJOIN,435)@39
rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid434_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest(CONSTANT,285)
rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q <= "000000";
--RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest(BITSELECT,428)@39
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest(BITJOIN,430)@39
rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid429_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest(BITSELECT,425)@39
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest(BITJOIN,427)@39
rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid426_alignArcsinL_uid84_fpArccosXTest_b;
--RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest(BITSELECT,422)@39
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b <= RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest(BITJOIN,424)@39
rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid423_alignArcsinL_uid84_fpArccosXTest_b;
--rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest(CONSTANT,275)
rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q <= "000000000000000000000000";
--cstAllZWF_uid10_fpArccosXTest(CONSTANT,9)
cstAllZWF_uid10_fpArccosXTest_q <= "00000000000000000000000";
--maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest(CONSTANT,209)
maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q <= "100011";
--reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1(REG,506)@1
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q <= y_uid52_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid18_uid54_fpArccosXTest(BITJOIN,53)@1
pad_o_uid18_uid54_fpArccosXTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0(REG,505)@1
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q <= pad_o_uid18_uid54_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid54_fpArccosXTest(SUB,54)@2
oMy_uid54_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid18_uid54_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_0_q);
oMy_uid54_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid52_fpArccosXTest_0_to_oMy_uid54_fpArccosXTest_1_q);
oMy_uid54_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid54_fpArccosXTest_a) - UNSIGNED(oMy_uid54_fpArccosXTest_b));
oMy_uid54_fpArccosXTest_q <= oMy_uid54_fpArccosXTest_o(36 downto 0);
--l_uid56_fpArccosXTest(BITSELECT,55)@2
l_uid56_fpArccosXTest_in <= oMy_uid54_fpArccosXTest_q(34 downto 0);
l_uid56_fpArccosXTest_b <= l_uid56_fpArccosXTest_in(34 downto 0);
--rVStage_uid168_fpLOut1_uid57_fpArccosXTest(BITSELECT,167)@2
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b;
rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_in(34 downto 3);
--reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1(REG,507)@2
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid168_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid169_fpLOut1_uid57_fpArccosXTest(LOGICAL,168)@3
vCount_uid169_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid168_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid169_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
vCount_uid169_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid169_fpLOut1_uid57_fpArccosXTest_a = vCount_uid169_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f(DELAY,792)@3
ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid169_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid171_fpLOut1_uid57_fpArccosXTest(BITSELECT,170)@2
vStage_uid171_fpLOut1_uid57_fpArccosXTest_in <= l_uid56_fpArccosXTest_b(2 downto 0);
vStage_uid171_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_in(2 downto 0);
--cStage_uid172_fpLOut1_uid57_fpArccosXTest(BITJOIN,171)@2
cStage_uid172_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid171_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx2Pad32_uid139_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3(REG,509)@2
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid172_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2(REG,508)@2
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q <= l_uid56_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid173_fpLOut1_uid57_fpArccosXTest(MUX,172)@3
vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid169_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid173_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s, en, reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid173_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_l_uid56_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid172_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid175_fpLOut1_uid57_fpArccosXTest(BITSELECT,174)@3
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_in(34 downto 19);
--reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1(REG,510)@3
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid175_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid176_fpLOut1_uid57_fpArccosXTest(LOGICAL,175)@4
vCount_uid176_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid175_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid176_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
vCount_uid176_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid176_fpLOut1_uid57_fpArccosXTest_a = vCount_uid176_fpLOut1_uid57_fpArccosXTest_b else "0";
--ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e(DELAY,791)@4
ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid176_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid178_fpLOut1_uid57_fpArccosXTest(BITSELECT,177)@3
vStage_uid178_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q(18 downto 0);
vStage_uid178_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_in(18 downto 0);
--cStage_uid179_fpLOut1_uid57_fpArccosXTest(BITJOIN,178)@3
cStage_uid179_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid178_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3(REG,512)@3
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid179_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2(REG,511)@3
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid173_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid180_fpLOut1_uid57_fpArccosXTest(MUX,179)@4
vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid176_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid180_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid180_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid173_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid179_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid180_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid182_fpLOut1_uid57_fpArccosXTest(BITSELECT,181)@4
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_in(34 downto 27);
--vCount_uid183_fpLOut1_uid57_fpArccosXTest(LOGICAL,182)@4
vCount_uid183_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid182_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
vCount_uid183_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid183_fpLOut1_uid57_fpArccosXTest_a = vCount_uid183_fpLOut1_uid57_fpArccosXTest_b else "0";
--reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3(REG,516)@4
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid185_fpLOut1_uid57_fpArccosXTest(BITSELECT,184)@4
vStage_uid185_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q(26 downto 0);
vStage_uid185_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_in(26 downto 0);
--cStage_uid186_fpLOut1_uid57_fpArccosXTest(BITJOIN,185)@4
cStage_uid186_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid185_fpLOut1_uid57_fpArccosXTest_b & cstAllZWE_uid12_fpArccosXTest_q;
--vStagei_uid187_fpLOut1_uid57_fpArccosXTest(MUX,186)@4
vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid183_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid187_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q, cStage_uid186_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid187_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid180_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid186_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid189_fpLOut1_uid57_fpArccosXTest(BITSELECT,188)@4
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_in(34 downto 31);
--reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1(REG,513)@4
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q <= rVStage_uid189_fpLOut1_uid57_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid190_fpLOut1_uid57_fpArccosXTest(LOGICAL,189)@5
vCount_uid190_fpLOut1_uid57_fpArccosXTest_a <= reg_rVStage_uid189_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid190_fpLOut1_uid57_fpArccosXTest_1_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
vCount_uid190_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid190_fpLOut1_uid57_fpArccosXTest_a = vCount_uid190_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid192_fpLOut1_uid57_fpArccosXTest(BITSELECT,191)@4
vStage_uid192_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q(30 downto 0);
vStage_uid192_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_in(30 downto 0);
--cStage_uid193_fpLOut1_uid57_fpArccosXTest(BITJOIN,192)@4
cStage_uid193_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid192_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q;
--reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3(REG,515)@4
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q <= cStage_uid193_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2(REG,514)@4
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q <= vStagei_uid187_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_fpLOut1_uid57_fpArccosXTest(MUX,193)@5
vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid190_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid194_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s, en, reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q, reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q)
BEGIN
CASE vStagei_uid194_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_vStagei_uid187_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_2_q;
WHEN "1" => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= reg_cStage_uid193_fpLOut1_uid57_fpArccosXTest_0_to_vStagei_uid194_fpLOut1_uid57_fpArccosXTest_3_q;
WHEN OTHERS => vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_fpLOut1_uid57_fpArccosXTest(BITSELECT,195)@5
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_in(34 downto 33);
--vCount_uid197_fpLOut1_uid57_fpArccosXTest(LOGICAL,196)@5
vCount_uid197_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid196_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_b <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
vCount_uid197_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid197_fpLOut1_uid57_fpArccosXTest_a = vCount_uid197_fpLOut1_uid57_fpArccosXTest_b else "0";
--vStage_uid199_fpLOut1_uid57_fpArccosXTest(BITSELECT,198)@5
vStage_uid199_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q(32 downto 0);
vStage_uid199_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_in(32 downto 0);
--cStage_uid200_fpLOut1_uid57_fpArccosXTest(BITJOIN,199)@5
cStage_uid200_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid199_fpLOut1_uid57_fpArccosXTest_b & rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q;
--vStagei_uid201_fpLOut1_uid57_fpArccosXTest(MUX,200)@5
vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid197_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid201_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q, cStage_uid200_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid201_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid194_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid200_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid203_fpLOut1_uid57_fpArccosXTest(BITSELECT,202)@5
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_in(34 downto 34);
--vCount_uid204_fpLOut1_uid57_fpArccosXTest(LOGICAL,203)@5
vCount_uid204_fpLOut1_uid57_fpArccosXTest_a <= rVStage_uid203_fpLOut1_uid57_fpArccosXTest_b;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_b <= GND_q;
vCount_uid204_fpLOut1_uid57_fpArccosXTest_q <= "1" when vCount_uid204_fpLOut1_uid57_fpArccosXTest_a = vCount_uid204_fpLOut1_uid57_fpArccosXTest_b else "0";
--vCount_uid209_fpLOut1_uid57_fpArccosXTest(BITJOIN,208)@5
vCount_uid209_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid169_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_f_q & ld_vCount_uid176_fpLOut1_uid57_fpArccosXTest_q_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_e_q & reg_vCount_uid183_fpLOut1_uid57_fpArccosXTest_0_to_vCount_uid209_fpLOut1_uid57_fpArccosXTest_3_q & vCount_uid190_fpLOut1_uid57_fpArccosXTest_q & vCount_uid197_fpLOut1_uid57_fpArccosXTest_q & vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
--ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c(DELAY,795)@5
ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid209_fpLOut1_uid57_fpArccosXTest_q, xout => ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1(REG,517)@5
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q <= vCount_uid209_fpLOut1_uid57_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid211_fpLOut1_uid57_fpArccosXTest(COMPARE,210)@6
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin <= GND_q;
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q) & '0';
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid209_fpLOut1_uid57_fpArccosXTest_0_to_vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_1_q) & vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_cin(0);
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_a) - UNSIGNED(vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_b));
vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c(0) <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_o(8);
--vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest(MUX,212)@6
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s <= vCountBig_uid211_fpLOut1_uid57_fpArccosXTest_c;
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= ld_vCount_uid209_fpLOut1_uid57_fpArccosXTest_q_to_vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_c_q;
WHEN "1" => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= maxCountVal_uid210_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid16_fpArccosXTest(CONSTANT,15)
cstBiasM2_uid16_fpArccosXTest_q <= "01111101";
--expL_uid58_fpArccosXTest(SUB,57)@7
expL_uid58_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid16_fpArccosXTest_q);
expL_uid58_fpArccosXTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid213_fpLOut1_uid57_fpArccosXTest_q);
expL_uid58_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid58_fpArccosXTest_a) - UNSIGNED(expL_uid58_fpArccosXTest_b));
expL_uid58_fpArccosXTest_q <= expL_uid58_fpArccosXTest_o(8 downto 0);
--expLRange_uid60_fpArccosXTest(BITSELECT,59)@7
expLRange_uid60_fpArccosXTest_in <= expL_uid58_fpArccosXTest_q(7 downto 0);
expLRange_uid60_fpArccosXTest_b <= expLRange_uid60_fpArccosXTest_in(7 downto 0);
--vStage_uid206_fpLOut1_uid57_fpArccosXTest(BITSELECT,205)@5
vStage_uid206_fpLOut1_uid57_fpArccosXTest_in <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
vStage_uid206_fpLOut1_uid57_fpArccosXTest_b <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_in(33 downto 0);
--cStage_uid207_fpLOut1_uid57_fpArccosXTest(BITJOIN,206)@5
cStage_uid207_fpLOut1_uid57_fpArccosXTest_q <= vStage_uid206_fpLOut1_uid57_fpArccosXTest_b & GND_q;
--vStagei_uid208_fpLOut1_uid57_fpArccosXTest(MUX,207)@5
vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s <= vCount_uid204_fpLOut1_uid57_fpArccosXTest_q;
vStagei_uid208_fpLOut1_uid57_fpArccosXTest: PROCESS (vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s, en, vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q, cStage_uid207_fpLOut1_uid57_fpArccosXTest_q)
BEGIN
CASE vStagei_uid208_fpLOut1_uid57_fpArccosXTest_s IS
WHEN "0" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= vStagei_uid201_fpLOut1_uid57_fpArccosXTest_q;
WHEN "1" => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= cStage_uid207_fpLOut1_uid57_fpArccosXTest_q;
WHEN OTHERS => vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid59_fpArccosXTest(BITSELECT,58)@5
fpLOutFrac_uid59_fpArccosXTest_in <= vStagei_uid208_fpLOut1_uid57_fpArccosXTest_q(33 downto 0);
fpLOutFrac_uid59_fpArccosXTest_b <= fpLOutFrac_uid59_fpArccosXTest_in(33 downto 11);
--ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a(DELAY,1111)@5
ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid59_fpArccosXTest_b, xout => ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0(REG,518)@6
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q <= ld_fpLOutFrac_uid59_fpArccosXTest_b_to_reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid61_fpArccosXTest(BITJOIN,60)@7
fpL_uid61_fpArccosXTest_q <= GND_q & expLRange_uid60_fpArccosXTest_b & reg_fpLOutFrac_uid59_fpArccosXTest_0_to_fpL_uid61_fpArccosXTest_0_q;
--signX_uid218_sqrtFPL_uid63_fpArccosXTest(BITSELECT,217)@7
signX_uid218_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q;
signX_uid218_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_in(31 downto 31);
--expX_uid216_sqrtFPL_uid63_fpArccosXTest(BITSELECT,215)@7
expX_uid216_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(30 downto 0);
expX_uid216_sqrtFPL_uid63_fpArccosXTest_b <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest(LOGICAL,222)@7
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q <= "1" when expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_a = expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_b else "0";
--negZero_uid266_sqrtFPL_uid63_fpArccosXTest(LOGICAL,265)@7
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
negZero_uid266_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q <= negZero_uid266_sqrtFPL_uid63_fpArccosXTest_a and negZero_uid266_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c(DELAY,851)@8
ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor(LOGICAL,1249)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q <= not (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_a or ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_b);
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top(CONSTANT,1245)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp(LOGICAL,1246)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_mem_top_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q <= "1" when ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_a = ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_b else "0";
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg(REG,1247)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena(REG,1250)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_nor_q = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd(LOGICAL,1251)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_sticky_ena_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_a and ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_b;
--cstBiasM1_uid14_fpArccosXTest(CONSTANT,13)
cstBiasM1_uid14_fpArccosXTest_q <= "01111110";
--reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0(REG,528)@7
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest(ADD,238)@8
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_b));
expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expROdd_uid240_sqrtFPL_uid63_fpArccosXTest(BITSELECT,239)@8
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in <= expOddSig_uid239_sqrtFPL_uid63_fpArccosXTest_q;
expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest(ADD,235)@8
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid216_sqrtFPL_uid63_fpArccosXTest_0_to_expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_0_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_a) + UNSIGNED(expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_b));
expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_o(8 downto 0);
--expREven_uid237_sqrtFPL_uid63_fpArccosXTest(BITSELECT,236)@8
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in <= expEvenSig_uid236_sqrtFPL_uid63_fpArccosXTest_q;
expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_in(8 downto 1);
--expX0_uid241_sqrtFPL_uid63_fpArccosXTest(BITSELECT,240)@7
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b(0 downto 0);
expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_in(0 downto 0);
--expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest(LOGICAL,241)@7
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a <= expX0_uid241_sqrtFPL_uid63_fpArccosXTest_b;
expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q <= not expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_a;
--ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b(DELAY,819)@7
ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid243_sqrtFPL_uid63_fpArccosXTest(MUX,242)@8
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s <= ld_expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q_to_expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_b_q;
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "0" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expREven_uid237_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "1" => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= expROdd_uid240_sqrtFPL_uid63_fpArccosXTest_b;
WHEN OTHERS => expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b(DELAY,831)@7
ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid218_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest(LOGICAL,230)@8
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_a;
--fracX_uid217_sqrtFPL_uid63_fpArccosXTest(BITSELECT,216)@7
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in <= fpL_uid61_fpArccosXTest_q(22 downto 0);
fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_in(22 downto 0);
--reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1(REG,519)@7
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest(LOGICAL,226)@8
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a <= reg_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_0_to_fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_1_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q <= "1" when fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_a = fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_b else "0";
--expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest(LOGICAL,224)@7
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a <= expX_uid216_sqrtFPL_uid63_fpArccosXTest_b;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_a = expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_b) THEN
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid228_sqrtFPL_uid63_fpArccosXTest(LOGICAL,227)@8
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_a and exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_b;
--InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest(LOGICAL,231)@8
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q <= not InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_a;
--InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest(LOGICAL,232)@7
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a <= expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q;
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q <= not InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid234_sqrtFPL_uid63_fpArccosXTest(LOGICAL,233)@8
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a <= InvExpXIsZero_uid233_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b <= InvExc_I_uid232_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c <= InvExc_N_uid231_sqrtFPL_uid63_fpArccosXTest_q;
exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_a and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_b and exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_c;
--minReg_uid252_sqrtFPL_uid63_fpArccosXTest(LOGICAL,251)@8
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a <= exc_R_uid234_sqrtFPL_uid63_fpArccosXTest_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_a and minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b;
--minInf_uid253_sqrtFPL_uid63_fpArccosXTest(LOGICAL,252)@8
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q;
minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_a and minInf_uid253_sqrtFPL_uid63_fpArccosXTest_b;
--InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest(LOGICAL,228)@8
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a <= fracXIsZero_uid227_sqrtFPL_uid63_fpArccosXTest_q;
InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q <= not InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_a;
--exc_N_uid230_sqrtFPL_uid63_fpArccosXTest(LOGICAL,229)@8
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a <= expXIsMax_uid225_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b <= InvFracXIsZero_uid229_sqrtFPL_uid63_fpArccosXTest_q;
exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_a and exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_b;
--excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest(LOGICAL,253)@8
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a <= exc_N_uid230_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b <= minInf_uid253_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c <= minReg_uid252_sqrtFPL_uid63_fpArccosXTest_q;
excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_a or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_b or excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_c;
--InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest(LOGICAL,249)@7
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a <= signX_uid218_sqrtFPL_uid63_fpArccosXTest_b;
InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q <= not InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_a;
--ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b(DELAY,829)@7
ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest(LOGICAL,250)@8
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a <= exc_I_uid228_sqrtFPL_uid63_fpArccosXTest_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b <= ld_InvSignX_uid250_sqrtFPL_uid63_fpArccosXTest_q_to_inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b_q;
inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q <= inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_a and inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_b;
--ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a(DELAY,837)@7
ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid255_sqrtFPL_uid63_fpArccosXTest(BITJOIN,254)@8
join_uid255_sqrtFPL_uid63_fpArccosXTest_q <= excRNaN_uid254_sqrtFPL_uid63_fpArccosXTest_q & inInfAndNotNeg_uid251_sqrtFPL_uid63_fpArccosXTest_q & ld_expXIsZero_uid223_sqrtFPL_uid63_fpArccosXTest_q_to_join_uid255_sqrtFPL_uid63_fpArccosXTest_a_q;
--fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest(BITJOIN,255)@8
fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q <= ld_signX_uid218_sqrtFPL_uid63_fpArccosXTest_b_to_minReg_uid252_sqrtFPL_uid63_fpArccosXTest_b_q & join_uid255_sqrtFPL_uid63_fpArccosXTest_q;
--reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0(REG,520)@8
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q <= fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid257_sqrtFPL_uid63_fpArccosXTest(LOOKUP,256)@9
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest: PROCESS (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid256_sqrtFPL_uid63_fpArccosXTest_0_to_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_0_q) IS
WHEN "0000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "01";
WHEN "0001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "0101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "0110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "10";
WHEN "0111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1000" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1001" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "00";
WHEN "1010" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1011" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1100" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1101" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1110" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN "1111" => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= "11";
WHEN OTHERS =>
fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest(MUX,260)@9
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s <= fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q;
expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest: PROCESS (expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= expRMux_uid243_sqrtFPL_uid63_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg(DELAY,1239)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt(COUNTER,1241)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg(REG,1242)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux(MUX,1243)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q, ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem(DUALMEM,1240)
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_inputreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdreg_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_rdmux_q;
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_ia
);
ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q <= ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid11_fpArccosXTest(CONSTANT,10)
cstNaNWF_uid11_fpArccosXTest_q <= "00000000000000000000001";
--fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest(BITSELECT,244)@7
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in <= fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b;
fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b <= fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_in(22 downto 16);
--addrTable_uid246_sqrtFPL_uid63_fpArccosXTest(BITJOIN,245)@7
addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q <= expOddSelect_uid242_sqrtFPL_uid63_fpArccosXTest_q & fracXAddr_uid245_sqrtFPL_uid63_fpArccosXTest_b;
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0(REG,521)@7
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q <= addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid458_sqrtTableGenerator_lutmem(DUALMEM,497)@8
memoryC2_uid458_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid458_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid458_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid458_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid458_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid458_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid458_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid458_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid458_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid458_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid458_sqrtTableGenerator_lutmem_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1(REG,523)@10
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q <= memoryC2_uid458_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg(DELAY,1238)
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a(DELAY,825)@7
ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_inputreg_q, xout => ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest(BITSELECT,246)@10
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in <= ld_fracX_uid217_sqrtFPL_uid63_fpArccosXTest_b_to_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_a_q(15 downto 0);
FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_in(15 downto 0);
--yT1_uid459_sqrtPolynomialEvaluator(BITSELECT,458)@10
yT1_uid459_sqrtPolynomialEvaluator_in <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
yT1_uid459_sqrtPolynomialEvaluator_b <= yT1_uid459_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0(REG,522)@10
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q <= yT1_uid459_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator(MULT,483)@11
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b);
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_a <= reg_yT1_uid459_sqrtPolynomialEvaluator_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_0_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid458_sqrtTableGenerator_lutmem_0_to_prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_1_q;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator(BITSELECT,484)@14
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in <= prodXY_uid484_pT1_uid460_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid462_sqrtPolynomialEvaluator(BITSELECT,461)@14
highBBits_uid462_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b;
highBBits_uid462_sqrtPolynomialEvaluator_b <= highBBits_uid462_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1303)
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a(DELAY,1117)@7
ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_inputreg_q, xout => ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0(REG,524)@11
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_q_to_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid457_sqrtTableGenerator_lutmem(DUALMEM,496)@12
memoryC1_uid457_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid457_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid457_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC1_uid457_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid457_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid457_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid457_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid457_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid457_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid457_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid457_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid457_sqrtTableGenerator_lutmem_q <= memoryC1_uid457_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid463_sqrtPolynomialEvaluator(ADD,462)@14
sumAHighB_uid463_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid457_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid457_sqrtTableGenerator_lutmem_q);
sumAHighB_uid463_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid462_sqrtPolynomialEvaluator_b(11)) & highBBits_uid462_sqrtPolynomialEvaluator_b);
sumAHighB_uid463_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid463_sqrtPolynomialEvaluator_b));
sumAHighB_uid463_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid461_sqrtPolynomialEvaluator(BITSELECT,460)@14
lowRangeB_uid461_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid485_pT1_uid460_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid461_sqrtPolynomialEvaluator_b <= lowRangeB_uid461_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid461_uid464_sqrtPolynomialEvaluator(BITJOIN,463)@14
s1_uid461_uid464_sqrtPolynomialEvaluator_q <= sumAHighB_uid463_sqrtPolynomialEvaluator_q & lowRangeB_uid461_sqrtPolynomialEvaluator_b;
--reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1(REG,526)@14
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q <= s1_uid461_uid464_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor(LOGICAL,1285)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_a or ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_b);
--roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest(CONSTANT,369)
roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q <= "010";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp(LOGICAL,1282)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_a = ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg(REG,1283)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena(REG,1286)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,1287)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_b;
--reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0(REG,525)@10
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q <= FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,1277)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 1 THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 2;
ELSE
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_i,2));
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg(REG,1278)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,1279)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,1276)
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia <= reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_iq(15 downto 0);
--prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator(MULT,486)@15
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b);
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a <= ld_reg_FracX15dto0_uid247_sqrtFPL_uid63_fpArccosXTest_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_0_q_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_b <= reg_s1_uid461_uid464_sqrtPolynomialEvaluator_0_to_prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_1_q;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator(BITSELECT,487)@18
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in <= prodXY_uid487_pT2_uid466_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid468_sqrtPolynomialEvaluator(BITSELECT,467)@18
highBBits_uid468_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b;
highBBits_uid468_sqrtPolynomialEvaluator_b <= highBBits_uid468_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor(LOGICAL,1300)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena(REG,1301)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,1302)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,1291)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia <= reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC2_uid458_sqrtTableGenerator_lutmem_0_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1290)
ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_mem_q, xout => ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid456_sqrtTableGenerator_lutmem(DUALMEM,495)@16
memoryC0_uid456_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid456_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid456_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC0_uid456_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid456_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid456_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid456_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid456_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid456_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid456_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid456_sqrtTableGenerator_lutmem_q <= memoryC0_uid456_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid469_sqrtPolynomialEvaluator(ADD,468)@18
sumAHighB_uid469_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid456_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid456_sqrtTableGenerator_lutmem_q);
sumAHighB_uid469_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid468_sqrtPolynomialEvaluator_b(21)) & highBBits_uid468_sqrtPolynomialEvaluator_b);
sumAHighB_uid469_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid469_sqrtPolynomialEvaluator_b));
sumAHighB_uid469_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid467_sqrtPolynomialEvaluator(BITSELECT,466)@18
lowRangeB_uid467_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid488_pT2_uid466_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid467_sqrtPolynomialEvaluator_b <= lowRangeB_uid467_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid467_uid470_sqrtPolynomialEvaluator(BITJOIN,469)@18
s2_uid467_uid470_sqrtPolynomialEvaluator_q <= sumAHighB_uid469_sqrtPolynomialEvaluator_q & lowRangeB_uid467_sqrtPolynomialEvaluator_b;
--fracR_uid249_sqrtFPL_uid63_fpArccosXTest(BITSELECT,248)@18
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in <= s2_uid467_uid470_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_in(28 downto 6);
--ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b(DELAY,845)@9
ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q, xout => ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest(MUX,264)@18
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s <= ld_fracSel_uid257_sqrtFPL_uid63_fpArccosXTest_q_to_fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_b_q;
fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest: PROCESS (fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= fracR_uid249_sqrtFPL_uid63_fpArccosXTest_b;
WHEN "10" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest(BITJOIN,266)@18
RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q <= ld_negZero_uid266_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_c_q & ld_expRPostExc_uid261_sqrtFPL_uid63_fpArccosXTest_q_to_RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_b_replace_mem_q & fracRPostExc_uid265_sqrtFPL_uid63_fpArccosXTest_q;
--SqrtFPL22dto0_uid64_fpArccosXTest(BITSELECT,63)@18
SqrtFPL22dto0_uid64_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(22 downto 0);
SqrtFPL22dto0_uid64_fpArccosXTest_b <= SqrtFPL22dto0_uid64_fpArccosXTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1(REG,552)@18
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL22dto0_uid64_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest(LOGICAL,327)@19
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL22dto0_uid64_fpArccosXTest_0_to_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b(DELAY,901)@19
ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q, xout => ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid66_fpArccosXTest(BITSELECT,65)@18
SqrtFPL30dto23_uid66_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q(30 downto 0);
SqrtFPL30dto23_uid66_fpArccosXTest_b <= SqrtFPL30dto23_uid66_fpArccosXTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1(REG,530)@18
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q <= SqrtFPL30dto23_uid66_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid326_arcsinL_uid78_fpArccosXTest(LOGICAL,325)@19
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a(DELAY,900)@19
ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid329_arcsinL_uid78_fpArccosXTest(LOGICAL,328)@31
exc_I_uid329_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_a_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_b <= ld_fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q_to_exc_I_uid329_arcsinL_uid78_fpArccosXTest_b_q;
exc_I_uid329_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_a and exc_I_uid329_arcsinL_uid78_fpArccosXTest_b;
--reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2(REG,565)@31
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest(BITSELECT,289)@20
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_in(23 downto 1);
--rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest(BITJOIN,291)@20
rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q <= GND_q & RightShiftStage123dto1_uid290_alignSqrt_uid69_fpArccosXTest_b;
--oSqrtFPLFrac_uid65_fpArccosXTest(BITJOIN,64)@18
oSqrtFPLFrac_uid65_fpArccosXTest_q <= VCC_q & SqrtFPL22dto0_uid64_fpArccosXTest_b;
--X23dto16_uid273_alignSqrt_uid69_fpArccosXTest(BITSELECT,272)@18
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b <= X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest(BITJOIN,274)@18
rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid273_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4(REG,534)@18
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid270_alignSqrt_uid69_fpArccosXTest(BITSELECT,269)@18
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b <= X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest(BITJOIN,271)@18
rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid270_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3(REG,533)@18
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2(REG,532)@18
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q <= oSqrtFPLFrac_uid65_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid67_fpArccosXTest(SUB,66)@19
srVal_uid67_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid14_fpArccosXTest_q);
srVal_uid67_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q);
srVal_uid67_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid67_fpArccosXTest_a) - UNSIGNED(srVal_uid67_fpArccosXTest_b));
srVal_uid67_fpArccosXTest_q <= srVal_uid67_fpArccosXTest_o(8 downto 0);
--srValRange_uid68_fpArccosXTest(BITSELECT,67)@19
srValRange_uid68_fpArccosXTest_in <= srVal_uid67_fpArccosXTest_q(4 downto 0);
srValRange_uid68_fpArccosXTest_b <= srValRange_uid68_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest(BITSELECT,276)@19
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_in(4 downto 3);
--rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest(MUX,277)@19
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s <= rightShiftStageSel4Dto3_uid277_alignSqrt_uid69_fpArccosXTest_b;
rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s, en, reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid272_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid275_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest(BITSELECT,284)@19
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_in(23 downto 6);
--rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest(BITJOIN,286)@19
rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx3Pad6_uid286_alignSqrt_uid69_fpArccosXTest_q & RightShiftStage023dto6_uid285_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5(REG,539)@19
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q <= rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest(BITSELECT,281)@19
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_in(23 downto 4);
--rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest(BITJOIN,283)@19
rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1Idx1Pad4_uid145_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto4_uid282_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4(REG,538)@19
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q <= rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest(BITSELECT,278)@19
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b <= RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_in(23 downto 2);
--rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest(BITJOIN,280)@19
rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx2Pad2_uid159_fxpX_uid50_fpArccosXTest_q & RightShiftStage023dto2_uid279_alignSqrt_uid69_fpArccosXTest_b;
--reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3(REG,537)@19
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q <= rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2(REG,536)@19
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q <= rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest(BITSELECT,287)@19
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1(REG,535)@19
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest(MUX,288)@20
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid288_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s, en, reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q, reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q, reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q, reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q)
BEGIN
CASE rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx1_uid281_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx2_uid284_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= reg_rightShiftStage1Idx3_uid287_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_5_q;
WHEN OTHERS => rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest(BITSELECT,292)@19
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in <= srValRange_uid68_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1(REG,540)@19
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest(MUX,293)@20
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid293_alignSqrt_uid69_fpArccosXTest_0_to_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_1_q;
rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest: PROCESS (rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s, en, rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q, rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage1_uid289_alignSqrt_uid69_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= rightShiftStage2Idx1_uid292_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid71_fpArccosXTest(BITSELECT,70)@20
sAddr_uid71_fpArccosXTest_in <= rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q;
sAddr_uid71_fpArccosXTest_b <= sAddr_uid71_fpArccosXTest_in(23 downto 16);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0(REG,541)@20
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid71_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid298_arcsinXO2XTabGen_lutmem(DUALMEM,491)@21
memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid298_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC2_uid298_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid298_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid298_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid298_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1(REG,543)@23
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q <= memoryC2_uid298_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg(DELAY,1185)
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a(DELAY,642)@20
ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_inputreg_q, xout => ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid72_fpArccosXTest(BITSELECT,71)@23
sPPolyEval_uid72_fpArccosXTest_in <= ld_rightShiftStage2_uid294_alignSqrt_uid69_fpArccosXTest_q_to_sPPolyEval_uid72_fpArccosXTest_a_q(15 downto 0);
sPPolyEval_uid72_fpArccosXTest_b <= sPPolyEval_uid72_fpArccosXTest_in(15 downto 1);
--yT1_uid299_arcsinXO2XPolyEval(BITSELECT,298)@23
yT1_uid299_arcsinXO2XPolyEval_in <= sPPolyEval_uid72_fpArccosXTest_b;
yT1_uid299_arcsinXO2XPolyEval_b <= yT1_uid299_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0(REG,542)@23
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q <= yT1_uid299_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval(MULT,471)@24
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b);
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_a <= reg_yT1_uid299_arcsinXO2XPolyEval_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_0_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_b <= reg_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_1_q;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval(BITSELECT,472)@27
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in <= prodXY_uid472_pT1_uid300_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid302_arcsinXO2XPolyEval(BITSELECT,301)@27
highBBits_uid302_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b;
highBBits_uid302_arcsinXO2XPolyEval_b <= highBBits_uid302_arcsinXO2XPolyEval_in(12 downto 1);
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a(DELAY,1083)@21
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_sAddr_uid71_fpArccosXTest_0_to_memoryC2_uid298_arcsinXO2XTabGen_lutmem_0_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1288)
ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_q, xout => ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid297_arcsinXO2XTabGen_lutmem(DUALMEM,490)@25
memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab <= ld_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_0_q_to_memoryC1_uid297_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC1_uid297_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC1_uid297_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid297_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid297_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid297_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid303_arcsinXO2XPolyEval(ADD,302)@27
sumAHighB_uid303_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid297_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid297_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid303_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid302_arcsinXO2XPolyEval_b(11)) & highBBits_uid302_arcsinXO2XPolyEval_b);
sumAHighB_uid303_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid303_arcsinXO2XPolyEval_b));
sumAHighB_uid303_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid301_arcsinXO2XPolyEval(BITSELECT,300)@27
lowRangeB_uid301_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid473_pT1_uid300_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid301_arcsinXO2XPolyEval_b <= lowRangeB_uid301_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid301_uid304_arcsinXO2XPolyEval(BITJOIN,303)@27
s1_uid301_uid304_arcsinXO2XPolyEval_q <= sumAHighB_uid303_arcsinXO2XPolyEval_q & lowRangeB_uid301_arcsinXO2XPolyEval_b;
--reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1(REG,546)@27
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q <= s1_uid301_uid304_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1312)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg(REG,1310)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1313)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1314)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1304)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid72_fpArccosXTest_b, xout => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt(COUNTER,1306)
-- every=1, low=0, high=1, step=1, init=1
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_i,1));
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg(REG,1307)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux(MUX,1308)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s <= en;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux: PROCESS (ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q, ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1305)
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdreg_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_rdmux_q;
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0(REG,545)@27
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid72_fpArccosXTest_b_to_reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval(MULT,474)@28
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b);
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid72_fpArccosXTest_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_0_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_b <= reg_s1_uid301_uid304_arcsinXO2XPolyEval_0_to_prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_1_q;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval(BITSELECT,475)@31
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in <= prodXY_uid475_pT2_uid306_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid308_arcsinXO2XPolyEval(BITSELECT,307)@31
highBBits_uid308_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b;
highBBits_uid308_arcsinXO2XPolyEval_b <= highBBits_uid308_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1325)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1326)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1327)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1315)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid71_fpArccosXTest_b, xout => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1316)
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid246_sqrtFPL_uid63_fpArccosXTest_0_to_memoryC0_uid456_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid456_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0(REG,547)@28
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid71_fpArccosXTest_b_to_reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid296_arcsinXO2XTabGen_lutmem(DUALMEM,489)@29
memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid71_fpArccosXTest_0_to_memoryC0_uid296_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid296_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccos_s5_memoryC0_uid296_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid296_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid296_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid296_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid309_arcsinXO2XPolyEval(ADD,308)@31
sumAHighB_uid309_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid296_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid296_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid309_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid308_arcsinXO2XPolyEval_b(19)) & highBBits_uid308_arcsinXO2XPolyEval_b);
sumAHighB_uid309_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid309_arcsinXO2XPolyEval_b));
sumAHighB_uid309_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid307_arcsinXO2XPolyEval(BITSELECT,306)@31
lowRangeB_uid307_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid476_pT2_uid306_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid307_arcsinXO2XPolyEval_b <= lowRangeB_uid307_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid307_uid310_arcsinXO2XPolyEval(BITJOIN,309)@31
s2_uid307_uid310_arcsinXO2XPolyEval_q <= sumAHighB_uid309_arcsinXO2XPolyEval_q & lowRangeB_uid307_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid74_fpArccosXTest(BITSELECT,73)@31
fxpArcSinXO2XRes_uid74_fpArccosXTest_in <= s2_uid307_uid310_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid74_fpArccosXTest_b <= fxpArcSinXO2XRes_uid74_fpArccosXTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid75_fpArccosXTest(BITSELECT,74)@31
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in <= fxpArcSinXO2XRes_uid74_fpArccosXTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b <= fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_in(24 downto 2);
--fpArcsinXO2XRes_uid76_fpArccosXTest(BITJOIN,75)@31
fpArcsinXO2XRes_uid76_fpArccosXTest_q <= GND_q & cstBiasP1_uid17_fpArccosXTest_q & fxpArcsinXO2XResWFRange_uid75_fpArccosXTest_b;
--expY_uid313_arcsinL_uid78_fpArccosXTest(BITSELECT,312)@31
expY_uid313_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(30 downto 0);
expY_uid313_arcsinL_uid78_fpArccosXTest_b <= expY_uid313_arcsinL_uid78_fpArccosXTest_in(30 downto 23);
--expXIsZero_uid340_arcsinL_uid78_fpArccosXTest(LOGICAL,339)@31
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_b else "0";
--reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2(REG,549)@31
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest(LOGICAL,393)@32
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b <= reg_exc_I_uid329_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_b;
--fracY_uid318_arcsinL_uid78_fpArccosXTest(BITSELECT,317)@31
fracY_uid318_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q(22 downto 0);
fracY_uid318_arcsinL_uid78_fpArccosXTest_b <= fracY_uid318_arcsinL_uid78_fpArccosXTest_in(22 downto 0);
--reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1(REG,550)@31
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q <= fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest(LOGICAL,343)@32
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a <= reg_fracY_uid318_arcsinL_uid78_fpArccosXTest_0_to_fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_1_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q <= "1" when fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_a = fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_b else "0";
--expXIsMax_uid342_arcsinL_uid78_fpArccosXTest(LOGICAL,341)@31
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_a = expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_b) THEN
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "1";
ELSE
expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid345_arcsinL_uid78_fpArccosXTest(LOGICAL,344)@32
exc_I_uid345_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_b <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
exc_I_uid345_arcsinL_uid78_fpArccosXTest_q <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_a and exc_I_uid345_arcsinL_uid78_fpArccosXTest_b;
--expXIsZero_uid324_arcsinL_uid78_fpArccosXTest(LOGICAL,323)@19
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q <= "1" when expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_a = expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_b else "0";
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a(DELAY,964)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest(LOGICAL,394)@32
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_b;
--ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest(LOGICAL,395)@32
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a <= excXZAndExcYI_uid395_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b <= excYZAndExcXI_uid394_arcsinL_uid78_fpArccosXTest_q;
ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_a or ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest(LOGICAL,345)@32
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid344_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid347_arcsinL_uid78_fpArccosXTest(LOGICAL,346)@32
exc_N_uid347_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid342_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid346_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid347_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_a and exc_N_uid347_arcsinL_uid78_fpArccosXTest_b;
--InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest(LOGICAL,329)@19
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a <= fracXIsZero_uid328_arcsinL_uid78_fpArccosXTest_q;
InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q <= not InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_a;
--exc_N_uid331_arcsinL_uid78_fpArccosXTest(LOGICAL,330)@19
exc_N_uid331_arcsinL_uid78_fpArccosXTest_a <= expXIsMax_uid326_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_b <= InvFracXIsZero_uid330_arcsinL_uid78_fpArccosXTest_q;
exc_N_uid331_arcsinL_uid78_fpArccosXTest_q <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_a and exc_N_uid331_arcsinL_uid78_fpArccosXTest_b;
--ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a(DELAY,994)@19
ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid331_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid397_arcsinL_uid78_fpArccosXTest(LOGICAL,396)@32
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a <= ld_exc_N_uid331_arcsinL_uid78_fpArccosXTest_q_to_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c <= ZeroTimesInf_uid396_arcsinL_uid78_fpArccosXTest_q;
excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_a or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_b or excRNaN_uid397_arcsinL_uid78_fpArccosXTest_c;
--InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest(LOGICAL,408)@32
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a <= excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q;
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q <= not InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--signY_uid315_arcsinL_uid78_fpArccosXTest(BITSELECT,314)@31
signY_uid315_arcsinL_uid78_fpArccosXTest_in <= fpArcsinXO2XRes_uid76_fpArccosXTest_q;
signY_uid315_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--signX_uid314_arcsinL_uid78_fpArccosXTest(BITSELECT,313)@18
signX_uid314_arcsinL_uid78_fpArccosXTest_in <= RSqrt_uid267_sqrtFPL_uid63_fpArccosXTest_q;
signX_uid314_arcsinL_uid78_fpArccosXTest_b <= signX_uid314_arcsinL_uid78_fpArccosXTest_in(31 downto 31);
--reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1(REG,569)@18
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q <= signX_uid314_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a(DELAY,958)@19
ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid380_arcsinL_uid78_fpArccosXTest(LOGICAL,379)@31
signR_uid380_arcsinL_uid78_fpArccosXTest_a <= ld_reg_signX_uid314_arcsinL_uid78_fpArccosXTest_0_to_signR_uid380_arcsinL_uid78_fpArccosXTest_1_q_to_signR_uid380_arcsinL_uid78_fpArccosXTest_a_q;
signR_uid380_arcsinL_uid78_fpArccosXTest_b <= signY_uid315_arcsinL_uid78_fpArccosXTest_b;
signR_uid380_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid380_arcsinL_uid78_fpArccosXTest_q <= signR_uid380_arcsinL_uid78_fpArccosXTest_a xor signR_uid380_arcsinL_uid78_fpArccosXTest_b;
END IF;
END PROCESS;
--ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a(DELAY,1006)@32
ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid380_arcsinL_uid78_fpArccosXTest_q, xout => ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid410_arcsinL_uid78_fpArccosXTest(LOGICAL,409)@33
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a <= ld_signR_uid380_arcsinL_uid78_fpArccosXTest_q_to_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b <= InvExcRNaN_uid409_arcsinL_uid78_fpArccosXTest_q;
signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q <= signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_a and signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_b;
--ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c(DELAY,1010)@33
ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q, xout => ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest(BITJOIN,318)@31
add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q <= VCC_q & fracY_uid318_arcsinL_uid78_fpArccosXTest_b;
--reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1(REG,556)@31
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q <= add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1273)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top(CONSTANT,1257)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp(LOGICAL,1258)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg(REG,1259)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1274)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1275)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt(COUNTER,1253)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg(REG,1254)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux(MUX,1255)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1264)
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_rightShiftStage0_uid278_alignSqrt_uid69_fpArccosXTest_2_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(23 downto 0);
--prod_uid355_arcsinL_uid78_fpArccosXTest(MULT,354)@32
prod_uid355_arcsinL_uid78_fpArccosXTest_pr <= UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_a) * UNSIGNED(prod_uid355_arcsinL_uid78_fpArccosXTest_b);
prod_uid355_arcsinL_uid78_fpArccosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= (others => '0');
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_a <= ld_reg_oSqrtFPLFrac_uid65_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_0_q_to_prod_uid355_arcsinL_uid78_fpArccosXTest_a_replace_mem_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_b <= reg_add_one_fracY_uid318_uid319_uid319_arcsinL_uid78_fpArccosXTest_0_to_prod_uid355_arcsinL_uid78_fpArccosXTest_1_q;
prod_uid355_arcsinL_uid78_fpArccosXTest_s1 <= STD_LOGIC_VECTOR(prod_uid355_arcsinL_uid78_fpArccosXTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid355_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid355_arcsinL_uid78_fpArccosXTest_q <= prod_uid355_arcsinL_uid78_fpArccosXTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid356_arcsinL_uid78_fpArccosXTest(BITSELECT,355)@35
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q;
normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_in(47 downto 47);
--fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest(BITSELECT,357)@35
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(46 downto 0);
fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_in(46 downto 23);
--fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest(BITSELECT,358)@35
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(45 downto 0);
fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_in(45 downto 22);
--fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest(MUX,359)@35
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s, en, fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b, fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormLow_uid359_arcsinL_uid78_fpArccosXTest_b;
WHEN "1" => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= fracRPostNormHigh_uid358_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest(BITSELECT,367)@35
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in <= fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q(1 downto 0);
FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_in(1 downto 0);
--Prod22_uid362_arcsinL_uid78_fpArccosXTest(BITSELECT,361)@35
Prod22_uid362_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
Prod22_uid362_arcsinL_uid78_fpArccosXTest_b <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_in(22 downto 22);
--extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest(MUX,362)@35
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s <= normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b;
extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest: PROCESS (extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s, en, GND_q, Prod22_uid362_arcsinL_uid78_fpArccosXTest_b)
BEGIN
CASE extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_s IS
WHEN "0" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= Prod22_uid362_arcsinL_uid78_fpArccosXTest_b;
WHEN OTHERS => extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid361_arcsinL_uid78_fpArccosXTest(BITSELECT,360)@35
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in <= prod_uid355_arcsinL_uid78_fpArccosXTest_q(21 downto 0);
stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b <= stickyRange_uid361_arcsinL_uid78_fpArccosXTest_in(21 downto 0);
--stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest(BITJOIN,363)@35
stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q <= extraStickyBit_uid363_arcsinL_uid78_fpArccosXTest_q & stickyRange_uid361_arcsinL_uid78_fpArccosXTest_b;
--stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest(LOGICAL,365)@35
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a <= stickyExtendedRange_uid364_arcsinL_uid78_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q <= "1" when stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_a = stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_b else "0";
--sticky_uid367_arcsinL_uid78_fpArccosXTest(LOGICAL,366)@35
sticky_uid367_arcsinL_uid78_fpArccosXTest_a <= stickyRangeComparator_uid366_arcsinL_uid78_fpArccosXTest_q;
sticky_uid367_arcsinL_uid78_fpArccosXTest_q <= not sticky_uid367_arcsinL_uid78_fpArccosXTest_a;
--lrs_uid369_arcsinL_uid78_fpArccosXTest(BITJOIN,368)@35
lrs_uid369_arcsinL_uid78_fpArccosXTest_q <= FracRPostNorm1dto0_uid368_arcsinL_uid78_fpArccosXTest_b & sticky_uid367_arcsinL_uid78_fpArccosXTest_q;
--roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest(LOGICAL,370)@35
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a <= lrs_uid369_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b <= roundBitDetectionConstant_uid370_arcsinL_uid78_fpArccosXTest_q;
roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q <= "1" when roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_a = roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_b else "0";
--roundBit_uid372_arcsinL_uid78_fpArccosXTest(LOGICAL,371)@35
roundBit_uid372_arcsinL_uid78_fpArccosXTest_a <= roundBitDetectionPattern_uid371_arcsinL_uid78_fpArccosXTest_q;
roundBit_uid372_arcsinL_uid78_fpArccosXTest_q <= not roundBit_uid372_arcsinL_uid78_fpArccosXTest_a;
--roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest(BITJOIN,374)@35
roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q <= GND_q & normalizeBit_uid356_arcsinL_uid78_fpArccosXTest_b & cstAllZWF_uid10_fpArccosXTest_q & roundBit_uid372_arcsinL_uid78_fpArccosXTest_q;
--reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1(REG,560)@35
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q <= roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid353_arcsinL_uid78_fpArccosXTest(CONSTANT,352)
biasInc_uid353_arcsinL_uid78_fpArccosXTest_q <= "0001111111";
--reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1(REG,558)@31
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q <= expY_uid313_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor(LOGICAL,1261)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena(REG,1262)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd(LOGICAL,1263)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem(DUALMEM,1252)
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_1_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_iq(7 downto 0);
--expSum_uid352_arcsinL_uid78_fpArccosXTest(ADD,351)@32
expSum_uid352_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid66_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_0_q_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_a_replace_mem_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid313_arcsinL_uid78_fpArccosXTest_0_to_expSum_uid352_arcsinL_uid78_fpArccosXTest_1_q);
expSum_uid352_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid352_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_a) + UNSIGNED(expSum_uid352_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid352_arcsinL_uid78_fpArccosXTest_q <= expSum_uid352_arcsinL_uid78_fpArccosXTest_o(8 downto 0);
--ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a(DELAY,927)@33
ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid352_arcsinL_uid78_fpArccosXTest_q, xout => ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid354_arcsinL_uid78_fpArccosXTest(SUB,353)@34
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid352_arcsinL_uid78_fpArccosXTest_q_to_expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid353_arcsinL_uid78_fpArccosXTest_q(9)) & biasInc_uid353_arcsinL_uid78_fpArccosXTest_q);
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_o(10 downto 0);
--expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest(BITJOIN,372)@35
expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q <= expSumMBias_uid354_arcsinL_uid78_fpArccosXTest_q & fracRPostNorm_uid360_arcsinL_uid78_fpArccosXTest_q;
--reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0(REG,559)@35
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q <= expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest(ADD,375)@36
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q(34)) & reg_expFracPreRound_uid373_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_0_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid375_arcsinL_uid78_fpArccosXTest_0_to_expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_1_q);
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_a) + SIGNED(expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_b));
expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_o(35 downto 0);
--expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest(BITSELECT,377)@36
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q;
expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_in(35 downto 24);
--expRPreExc_uid379_arcsinL_uid78_fpArccosXTest(BITSELECT,378)@36
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b(7 downto 0);
expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_in(7 downto 0);
--reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3(REG,568)@36
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q <= expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d(DELAY,1004)@37
ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c(DELAY,999)@32
ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q, xout => ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1(REG,561)@36
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q <= expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid383_arcsinL_uid78_fpArccosXTest(COMPARE,382)@37
expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expOvf_uid383_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & '0';
expOvf_uid383_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid9_fpArccosXTest_q) & expOvf_uid383_arcsinL_uid78_fpArccosXTest_cin(0);
expOvf_uid383_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expOvf_uid383_arcsinL_uid78_fpArccosXTest_b));
expOvf_uid383_arcsinL_uid78_fpArccosXTest_n(0) <= not expOvf_uid383_arcsinL_uid78_fpArccosXTest_o(14);
--InvExc_N_uid348_arcsinL_uid78_fpArccosXTest(LOGICAL,347)@32
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid347_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_a;
--InvExc_I_uid349_arcsinL_uid78_fpArccosXTest(LOGICAL,348)@32
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_a;
--InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest(LOGICAL,349)@31
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a <= expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_q;
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_a;
END IF;
END PROCESS;
--exc_R_uid351_arcsinL_uid78_fpArccosXTest(LOGICAL,350)@32
exc_R_uid351_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid350_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid349_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_c <= InvExc_N_uid348_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid351_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_a and exc_R_uid351_arcsinL_uid78_fpArccosXTest_b and exc_R_uid351_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b(DELAY,969)@32
ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid351_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid332_arcsinL_uid78_fpArccosXTest(LOGICAL,331)@19
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a <= exc_N_uid331_arcsinL_uid78_fpArccosXTest_q;
InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q <= not InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_a;
--ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c(DELAY,910)@19
ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q, xout => ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid333_arcsinL_uid78_fpArccosXTest(LOGICAL,332)@31
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a <= exc_I_uid329_arcsinL_uid78_fpArccosXTest_q;
InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q <= not InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_a;
--ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a(DELAY,907)@19
ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q, xout => ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest(LOGICAL,333)@31
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a_q;
InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q <= not InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_a;
--exc_R_uid335_arcsinL_uid78_fpArccosXTest(LOGICAL,334)@31
exc_R_uid335_arcsinL_uid78_fpArccosXTest_a <= InvExpXIsZero_uid334_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_b <= InvExc_I_uid333_arcsinL_uid78_fpArccosXTest_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_c <= ld_InvExc_N_uid332_arcsinL_uid78_fpArccosXTest_q_to_exc_R_uid335_arcsinL_uid78_fpArccosXTest_c_q;
exc_R_uid335_arcsinL_uid78_fpArccosXTest_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_a and exc_R_uid335_arcsinL_uid78_fpArccosXTest_b and exc_R_uid335_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a(DELAY,968)@31
ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid335_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest(LOGICAL,391)@37
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c <= expOvf_uid383_arcsinL_uid78_fpArccosXTest_n;
ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_a and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_b and ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_c;
--ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a(DELAY,975)@31
ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid329_arcsinL_uid78_fpArccosXTest_q, xout => ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest(LOGICAL,390)@32
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q <= excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_a and excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_b;
--ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c(DELAY,986)@32
ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2(REG,554)@31
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q <= exc_R_uid335_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest(LOGICAL,389)@32
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q <= excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_a and excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_b;
--ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b(DELAY,985)@32
ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest(LOGICAL,388)@32
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a <= ld_exc_I_uid329_arcsinL_uid78_fpArccosXTest_q_to_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b <= exc_I_uid345_arcsinL_uid78_fpArccosXTest_q;
excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q <= excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_a and excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_b;
--ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a(DELAY,984)@32
ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid393_arcsinL_uid78_fpArccosXTest(LOGICAL,392)@37
excRInf_uid393_arcsinL_uid78_fpArccosXTest_a <= ld_excXIAndExcYI_uid389_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_a_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_b <= ld_excXRAndExcYI_uid390_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_b_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_c <= ld_excYRAndExcXI_uid391_arcsinL_uid78_fpArccosXTest_q_to_excRInf_uid393_arcsinL_uid78_fpArccosXTest_c_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_d <= ExcROvfAndInReg_uid392_arcsinL_uid78_fpArccosXTest_q;
excRInf_uid393_arcsinL_uid78_fpArccosXTest_q <= excRInf_uid393_arcsinL_uid78_fpArccosXTest_a or excRInf_uid393_arcsinL_uid78_fpArccosXTest_b or excRInf_uid393_arcsinL_uid78_fpArccosXTest_c or excRInf_uid393_arcsinL_uid78_fpArccosXTest_d;
--expUdf_uid381_arcsinL_uid78_fpArccosXTest(COMPARE,380)@37
expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin <= GND_q;
expUdf_uid381_arcsinL_uid78_fpArccosXTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid381_arcsinL_uid78_fpArccosXTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q(11)) & reg_expRPreExcExt_uid378_arcsinL_uid78_fpArccosXTest_0_to_expUdf_uid381_arcsinL_uid78_fpArccosXTest_1_q) & expUdf_uid381_arcsinL_uid78_fpArccosXTest_cin(0);
expUdf_uid381_arcsinL_uid78_fpArccosXTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_a) - SIGNED(expUdf_uid381_arcsinL_uid78_fpArccosXTest_b));
expUdf_uid381_arcsinL_uid78_fpArccosXTest_n(0) <= not expUdf_uid381_arcsinL_uid78_fpArccosXTest_o(14);
--excZC3_uid387_arcsinL_uid78_fpArccosXTest(LOGICAL,386)@37
excZC3_uid387_arcsinL_uid78_fpArccosXTest_a <= ld_exc_R_uid335_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_a_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_b <= ld_exc_R_uid351_arcsinL_uid78_fpArccosXTest_q_to_excZC3_uid387_arcsinL_uid78_fpArccosXTest_b_q;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_c <= expUdf_uid381_arcsinL_uid78_fpArccosXTest_n;
excZC3_uid387_arcsinL_uid78_fpArccosXTest_q <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_a and excZC3_uid387_arcsinL_uid78_fpArccosXTest_b and excZC3_uid387_arcsinL_uid78_fpArccosXTest_c;
--excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest(LOGICAL,385)@32
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b <= reg_exc_R_uid335_arcsinL_uid78_fpArccosXTest_0_to_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_2_q;
excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q <= excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_a and excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_b;
--ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c(DELAY,973)@32
ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q, xout => ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest(LOGICAL,384)@32
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a <= ld_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q_to_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b <= exc_R_uid351_arcsinL_uid78_fpArccosXTest_q;
excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b(DELAY,972)@32
ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1(REG,548)@19
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q <= expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a(DELAY,962)@20
ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q, xout => ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest(LOGICAL,383)@32
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a <= ld_reg_expXIsZero_uid324_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_1_q_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b <= reg_expXIsZero_uid340_arcsinL_uid78_fpArccosXTest_0_to_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_2_q;
excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q <= excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_a and excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_b;
--ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a(DELAY,971)@32
ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q, xout => ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid388_arcsinL_uid78_fpArccosXTest(LOGICAL,387)@37
excRZero_uid388_arcsinL_uid78_fpArccosXTest_a <= ld_excXZAndExcYZ_uid384_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_a_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_b <= ld_excXZAndExcYR_uid385_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_b_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_c <= ld_excYZAndExcXR_uid386_arcsinL_uid78_fpArccosXTest_q_to_excRZero_uid388_arcsinL_uid78_fpArccosXTest_c_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_d <= excZC3_uid387_arcsinL_uid78_fpArccosXTest_q;
excRZero_uid388_arcsinL_uid78_fpArccosXTest_q <= excRZero_uid388_arcsinL_uid78_fpArccosXTest_a or excRZero_uid388_arcsinL_uid78_fpArccosXTest_b or excRZero_uid388_arcsinL_uid78_fpArccosXTest_c or excRZero_uid388_arcsinL_uid78_fpArccosXTest_d;
--concExc_uid398_arcsinL_uid78_fpArccosXTest(BITJOIN,397)@37
concExc_uid398_arcsinL_uid78_fpArccosXTest_q <= ld_excRNaN_uid397_arcsinL_uid78_fpArccosXTest_q_to_concExc_uid398_arcsinL_uid78_fpArccosXTest_c_q & excRInf_uid393_arcsinL_uid78_fpArccosXTest_q & excRZero_uid388_arcsinL_uid78_fpArccosXTest_q;
--reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0(REG,566)@37
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q <= concExc_uid398_arcsinL_uid78_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid399_arcsinL_uid78_fpArccosXTest(LOOKUP,398)@38
excREnc_uid399_arcsinL_uid78_fpArccosXTest: PROCESS (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid398_arcsinL_uid78_fpArccosXTest_0_to_excREnc_uid399_arcsinL_uid78_fpArccosXTest_0_q) IS
WHEN "000" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "01";
WHEN "001" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "010" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "10";
WHEN "011" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "100" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "11";
WHEN "101" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "110" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN "111" => excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= "00";
WHEN OTHERS =>
excREnc_uid399_arcsinL_uid78_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid408_arcsinL_uid78_fpArccosXTest(MUX,407)@38
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
expRPostExc_uid408_arcsinL_uid78_fpArccosXTest: PROCESS (expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= ld_reg_expRPreExc_uid379_arcsinL_uid78_fpArccosXTest_0_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_3_q_to_expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest(BITSELECT,376)@36
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in <= expFracRPostRounding_uid376_arcsinL_uid78_fpArccosXTest_q(23 downto 0);
fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_in(23 downto 1);
--reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3(REG,567)@36
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q <= fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d(DELAY,1002)@37
ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q, xout => ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest(MUX,402)@38
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s <= excREnc_uid399_arcsinL_uid78_fpArccosXTest_q;
fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest: PROCESS (fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= ld_reg_fracRPreExc_uid377_arcsinL_uid78_fpArccosXTest_0_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_3_q_to_fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_d_q;
WHEN "10" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid411_arcsinL_uid78_fpArccosXTest(BITJOIN,410)@38
R_uid411_arcsinL_uid78_fpArccosXTest_q <= ld_signRPostExc_uid410_arcsinL_uid78_fpArccosXTest_q_to_R_uid411_arcsinL_uid78_fpArccosXTest_c_q & expRPostExc_uid408_arcsinL_uid78_fpArccosXTest_q & fracRPostExc_uid403_arcsinL_uid78_fpArccosXTest_q;
--ArcsinL22dto0_uid79_fpArccosXTest(BITSELECT,78)@38
ArcsinL22dto0_uid79_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(22 downto 0);
ArcsinL22dto0_uid79_fpArccosXTest_b <= ArcsinL22dto0_uid79_fpArccosXTest_in(22 downto 0);
--oFracArcsinL_uid80_fpArccosXTest(BITJOIN,79)@38
oFracArcsinL_uid80_fpArccosXTest_q <= VCC_q & ArcsinL22dto0_uid79_fpArccosXTest_b;
--X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest(BITSELECT,416)@38
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b <= X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_in(23 downto 16);
--rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest(BITJOIN,418)@38
rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx1Pad16_uid136_fxpX_uid50_fpArccosXTest_q & X23dto16_uid417_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4(REG,573)@38
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q <= rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest(BITSELECT,413)@38
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in <= oFracArcsinL_uid80_fpArccosXTest_q;
X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b <= X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_in(23 downto 8);
--rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest(BITJOIN,415)@38
rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q & X23dto8_uid414_alignArcsinL_uid84_fpArccosXTest_b;
--reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3(REG,572)@38
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q <= rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2(REG,571)@38
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q <= oFracArcsinL_uid80_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid81_fpArccosXTest(BITSELECT,80)@38
ArcsinL30dto23_uid81_fpArccosXTest_in <= R_uid411_arcsinL_uid78_fpArccosXTest_q(30 downto 0);
ArcsinL30dto23_uid81_fpArccosXTest_b <= ArcsinL30dto23_uid81_fpArccosXTest_in(30 downto 23);
--srValArcsinL_uid82_fpArccosXTest(SUB,81)@38
srValArcsinL_uid82_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
srValArcsinL_uid82_fpArccosXTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid81_fpArccosXTest_b);
srValArcsinL_uid82_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid82_fpArccosXTest_a) - UNSIGNED(srValArcsinL_uid82_fpArccosXTest_b));
srValArcsinL_uid82_fpArccosXTest_q <= srValArcsinL_uid82_fpArccosXTest_o(8 downto 0);
--srValArcsinLRange_uid83_fpArccosXTest(BITSELECT,82)@38
srValArcsinLRange_uid83_fpArccosXTest_in <= srValArcsinL_uid82_fpArccosXTest_q(4 downto 0);
srValArcsinLRange_uid83_fpArccosXTest_b <= srValArcsinLRange_uid83_fpArccosXTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest(BITSELECT,420)@38
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b;
rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1(REG,570)@38
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest(MUX,421)@39
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel4Dto3_uid421_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s, en, reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q, reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q, reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q, rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q)
BEGIN
CASE rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_oFracArcsinL_uid80_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_2_q;
WHEN "01" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx1_uid416_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_3_q;
WHEN "10" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= reg_rightShiftStage0Idx2_uid419_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_4_q;
WHEN "11" => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0Idx3_uid276_alignSqrt_uid69_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest(BITSELECT,431)@38
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1(REG,574)@38
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest(MUX,432)@39
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel2Dto1_uid432_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "00" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage0_uid422_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "01" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx1_uid425_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "10" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx2_uid428_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "11" => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1Idx3_uid431_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest(BITSELECT,436)@38
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in <= srValArcsinLRange_uid83_fpArccosXTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1(REG,575)@38
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q <= rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest(MUX,437)@39
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s <= reg_rightShiftStageSel0Dto0_uid437_alignArcsinL_uid84_fpArccosXTest_0_to_rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_1_q;
rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest: PROCESS (rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s, en, rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q, rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q)
BEGIN
CASE rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_s IS
WHEN "0" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage1_uid433_alignArcsinL_uid84_fpArccosXTest_q;
WHEN "1" => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= rightShiftStage2Idx1_uid436_alignArcsinL_uid84_fpArccosXTest_q;
WHEN OTHERS => rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid85_uid86_fpArccosXTest(BITJOIN,85)@39
pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q <= rightShiftStage2_uid438_alignArcsinL_uid84_fpArccosXTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1(REG,576)@39
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q <= pad_fxpArcsinL_uid85_uid86_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid85_fpArccosXTest(CONSTANT,84)
pi_uid85_fpArccosXTest_q <= "1100100100001111110110101010";
--path1NegCase_uid86_fpArccosXTest(SUB,86)@40
path1NegCase_uid86_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & pi_uid85_fpArccosXTest_q);
path1NegCase_uid86_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid85_uid86_fpArccosXTest_0_to_path1NegCase_uid86_fpArccosXTest_1_q);
path1NegCase_uid86_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid86_fpArccosXTest_a) - UNSIGNED(path1NegCase_uid86_fpArccosXTest_b));
path1NegCase_uid86_fpArccosXTest_q <= path1NegCase_uid86_fpArccosXTest_o(28 downto 0);
--path1NegCaseN_uid88_fpArccosXTest(BITSELECT,87)@40
path1NegCaseN_uid88_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(27 downto 0);
path1NegCaseN_uid88_fpArccosXTest_b <= path1NegCaseN_uid88_fpArccosXTest_in(27 downto 27);
--reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1(REG,577)@40
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q <= path1NegCaseN_uid88_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid92_fpArccosXTest(ADD,91)@41
path1NegCaseExp_uid92_fpArccosXTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid13_fpArccosXTest_q);
path1NegCaseExp_uid92_fpArccosXTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid88_fpArccosXTest_0_to_path1NegCaseExp_uid92_fpArccosXTest_1_q);
path1NegCaseExp_uid92_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_a) + UNSIGNED(path1NegCaseExp_uid92_fpArccosXTest_b));
path1NegCaseExp_uid92_fpArccosXTest_q <= path1NegCaseExp_uid92_fpArccosXTest_o(8 downto 0);
--path1NegCaseExpRange_uid93_fpArccosXTest(BITSELECT,92)@41
path1NegCaseExpRange_uid93_fpArccosXTest_in <= path1NegCaseExp_uid92_fpArccosXTest_q(7 downto 0);
path1NegCaseExpRange_uid93_fpArccosXTest_b <= path1NegCaseExpRange_uid93_fpArccosXTest_in(7 downto 0);
--path1NegCaseFracHigh_uid89_fpArccosXTest(BITSELECT,88)@40
path1NegCaseFracHigh_uid89_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(26 downto 0);
path1NegCaseFracHigh_uid89_fpArccosXTest_b <= path1NegCaseFracHigh_uid89_fpArccosXTest_in(26 downto 4);
--path1NegCaseFracLow_uid90_fpArccosXTest(BITSELECT,89)@40
path1NegCaseFracLow_uid90_fpArccosXTest_in <= path1NegCase_uid86_fpArccosXTest_q(25 downto 0);
path1NegCaseFracLow_uid90_fpArccosXTest_b <= path1NegCaseFracLow_uid90_fpArccosXTest_in(25 downto 3);
--path1NegCaseFrac_uid91_fpArccosXTest(MUX,90)@40
path1NegCaseFrac_uid91_fpArccosXTest_s <= path1NegCaseN_uid88_fpArccosXTest_b;
path1NegCaseFrac_uid91_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid91_fpArccosXTest_s IS
WHEN "0" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracLow_uid90_fpArccosXTest_b;
WHEN "1" => path1NegCaseFrac_uid91_fpArccosXTest_q <= path1NegCaseFracHigh_uid89_fpArccosXTest_b;
WHEN OTHERS => path1NegCaseFrac_uid91_fpArccosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid94_fpArccosXTest(BITJOIN,93)@41
path1NegCaseUR_uid94_fpArccosXTest_q <= GND_q & path1NegCaseExpRange_uid93_fpArccosXTest_b & path1NegCaseFrac_uid91_fpArccosXTest_q;
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg(DELAY,1198)
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid411_arcsinL_uid78_fpArccosXTest_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c(DELAY,664)@38
ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_inputreg_q, xout => ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor(LOGICAL,1195)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q <= not (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_a or ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_b);
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top(CONSTANT,1191)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q <= "0100111";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp(LOGICAL,1192)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_mem_top_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q <= "1" when ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_a = ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_b else "0";
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg(REG,1193)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena(REG,1196)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_nor_q = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd(LOGICAL,1197)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_sticky_ena_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_a and ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt(COUNTER,1187)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_i,6));
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg(REG,1188)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux(MUX,1189)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s <= en;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux: PROCESS (ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q, ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem(DUALMEM,1186)
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0 <= areset;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia <= singX_uid8_fpArccosXTest_b;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdreg_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_rdmux_q;
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq,
address_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_aa,
data_a => ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_ia
);
ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid96_fpArccosXTest(MUX,95)@41
path1ResFP_uid96_fpArccosXTest_s <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_replace_mem_q;
path1ResFP_uid96_fpArccosXTest: PROCESS (path1ResFP_uid96_fpArccosXTest_s, en, ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q, path1NegCaseUR_uid94_fpArccosXTest_q)
BEGIN
CASE path1ResFP_uid96_fpArccosXTest_s IS
WHEN "0" => path1ResFP_uid96_fpArccosXTest_q <= ld_R_uid411_arcsinL_uid78_fpArccosXTest_q_to_path1ResFP_uid96_fpArccosXTest_c_q;
WHEN "1" => path1ResFP_uid96_fpArccosXTest_q <= path1NegCaseUR_uid94_fpArccosXTest_q;
WHEN OTHERS => path1ResFP_uid96_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid124_fpArccosXTest(BITSELECT,123)@41
Path1ResFP30dto23_uid124_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(30 downto 0);
Path1ResFP30dto23_uid124_fpArccosXTest_b <= Path1ResFP30dto23_uid124_fpArccosXTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2(REG,589)@41
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q <= Path1ResFP30dto23_uid124_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor(LOGICAL,1209)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q <= not (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_a or ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_b);
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top(CONSTANT,1205)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp(LOGICAL,1206)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_mem_top_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q <= "1" when ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_a = ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_b else "0";
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg(REG,1207)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena(REG,1210)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_nor_q = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd(LOGICAL,1211)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_sticky_ena_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_a and ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_b;
--ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c(DELAY,686)@0
ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid8_fpArccosXTest_b, xout => ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid51_fpArccosXTest(BITSELECT,50)@1
inputIsMax_uid51_fpArccosXTest_in <= rightShiftStage2_uid165_fxpX_uid50_fpArccosXTest_q;
inputIsMax_uid51_fpArccosXTest_b <= inputIsMax_uid51_fpArccosXTest_in(36 downto 36);
--firstPath_uid53_fpArccosXTest(BITSELECT,52)@1
firstPath_uid53_fpArccosXTest_in <= y_uid52_fpArccosXTest_b;
firstPath_uid53_fpArccosXTest_b <= firstPath_uid53_fpArccosXTest_in(34 downto 34);
--pathSelBits_uid117_fpArccosXTest(BITJOIN,116)@1
pathSelBits_uid117_fpArccosXTest_q <= ld_singX_uid8_fpArccosXTest_b_to_pathSelBits_uid117_fpArccosXTest_c_q & inputIsMax_uid51_fpArccosXTest_b & firstPath_uid53_fpArccosXTest_b;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg(DELAY,1199)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid117_fpArccosXTest_q, xout => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt(COUNTER,1201)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg(REG,1202)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux(MUX,1203)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q, ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem(DUALMEM,1200)
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_inputreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_ia
);
ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid118_fpArccosXTest(LOOKUP,117)@41
fracOutMuxSelEnc_uid118_fpArccosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid118_fpArccosXTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid118_fpArccosXTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid125_fpArccosXTest(MUX,124)@42
expRCalc_uid125_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
expRCalc_uid125_fpArccosXTest: PROCESS (expRCalc_uid125_fpArccosXTest_s, en, reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q, ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q, cstBiasP1_uid17_fpArccosXTest_q, cstAllZWE_uid12_fpArccosXTest_q)
BEGIN
CASE expRCalc_uid125_fpArccosXTest_s IS
WHEN "00" => expRCalc_uid125_fpArccosXTest_q <= reg_Path1ResFP30dto23_uid124_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_2_q;
WHEN "01" => expRCalc_uid125_fpArccosXTest_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_outputreg_q;
WHEN "10" => expRCalc_uid125_fpArccosXTest_q <= cstBiasP1_uid17_fpArccosXTest_q;
WHEN "11" => expRCalc_uid125_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN OTHERS => expRCalc_uid125_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid12_fpArccosXTest(CONSTANT,11)
cstAllZWE_uid12_fpArccosXTest_q <= "00000000";
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor(LOGICAL,1235)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q <= not (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_a or ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_b);
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena(REG,1236)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_nor_q = "1") THEN
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd(LOGICAL,1237)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_sticky_ena_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b <= en;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_a and ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_b;
--fracXIsZero_uid38_fpArccosXTest(LOGICAL,37)@0
fracXIsZero_uid38_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid38_fpArccosXTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid38_fpArccosXTest_q <= "1" when fracXIsZero_uid38_fpArccosXTest_a = fracXIsZero_uid38_fpArccosXTest_b else "0";
--InvFracXIsZero_uid39_fpArccosXTest(LOGICAL,38)@0
InvFracXIsZero_uid39_fpArccosXTest_a <= fracXIsZero_uid38_fpArccosXTest_q;
InvFracXIsZero_uid39_fpArccosXTest_q <= not InvFracXIsZero_uid39_fpArccosXTest_a;
--expEQ0_uid37_fpArccosXTest(LOGICAL,36)@0
expEQ0_uid37_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expEQ0_uid37_fpArccosXTest_b <= cstBias_uid13_fpArccosXTest_q;
expEQ0_uid37_fpArccosXTest_q <= "1" when expEQ0_uid37_fpArccosXTest_a = expEQ0_uid37_fpArccosXTest_b else "0";
--expXZFracNotZero_uid40_fpArccosXTest(LOGICAL,39)@0
expXZFracNotZero_uid40_fpArccosXTest_a <= expEQ0_uid37_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_b <= InvFracXIsZero_uid39_fpArccosXTest_q;
expXZFracNotZero_uid40_fpArccosXTest_q <= expXZFracNotZero_uid40_fpArccosXTest_a and expXZFracNotZero_uid40_fpArccosXTest_b;
--expGT0_uid36_fpArccosXTest(COMPARE,35)@0
expGT0_uid36_fpArccosXTest_cin <= GND_q;
expGT0_uid36_fpArccosXTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid13_fpArccosXTest_q) & '0';
expGT0_uid36_fpArccosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpArccosXTest_b) & expGT0_uid36_fpArccosXTest_cin(0);
expGT0_uid36_fpArccosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid36_fpArccosXTest_a) - UNSIGNED(expGT0_uid36_fpArccosXTest_b));
expGT0_uid36_fpArccosXTest_c(0) <= expGT0_uid36_fpArccosXTest_o(10);
--inputOutOfRange_uid41_fpArccosXTest(LOGICAL,40)@0
inputOutOfRange_uid41_fpArccosXTest_a <= expGT0_uid36_fpArccosXTest_c;
inputOutOfRange_uid41_fpArccosXTest_b <= expXZFracNotZero_uid40_fpArccosXTest_q;
inputOutOfRange_uid41_fpArccosXTest_q <= inputOutOfRange_uid41_fpArccosXTest_a or inputOutOfRange_uid41_fpArccosXTest_b;
--InvExc_N_uid32_fpArccosXTest(LOGICAL,31)@0
InvExc_N_uid32_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
InvExc_N_uid32_fpArccosXTest_q <= not InvExc_N_uid32_fpArccosXTest_a;
--InvExc_I_uid33_fpArccosXTest(LOGICAL,32)@0
InvExc_I_uid33_fpArccosXTest_a <= exc_I_uid29_fpArccosXTest_q;
InvExc_I_uid33_fpArccosXTest_q <= not InvExc_I_uid33_fpArccosXTest_a;
--expXIsZero_uid24_fpArccosXTest(LOGICAL,23)@0
expXIsZero_uid24_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsZero_uid24_fpArccosXTest_b <= cstAllZWE_uid12_fpArccosXTest_q;
expXIsZero_uid24_fpArccosXTest_q <= "1" when expXIsZero_uid24_fpArccosXTest_a = expXIsZero_uid24_fpArccosXTest_b else "0";
--InvExpXIsZero_uid34_fpArccosXTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpArccosXTest_a <= expXIsZero_uid24_fpArccosXTest_q;
InvExpXIsZero_uid34_fpArccosXTest_q <= not InvExpXIsZero_uid34_fpArccosXTest_a;
--exc_R_uid35_fpArccosXTest(LOGICAL,34)@0
exc_R_uid35_fpArccosXTest_a <= InvExpXIsZero_uid34_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_b <= InvExc_I_uid33_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_c <= InvExc_N_uid32_fpArccosXTest_q;
exc_R_uid35_fpArccosXTest_q <= exc_R_uid35_fpArccosXTest_a and exc_R_uid35_fpArccosXTest_b and exc_R_uid35_fpArccosXTest_c;
--xRegAndOutOfRange_uid126_fpArccosXTest(LOGICAL,125)@0
xRegAndOutOfRange_uid126_fpArccosXTest_a <= exc_R_uid35_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_b <= inputOutOfRange_uid41_fpArccosXTest_q;
xRegAndOutOfRange_uid126_fpArccosXTest_q <= xRegAndOutOfRange_uid126_fpArccosXTest_a and xRegAndOutOfRange_uid126_fpArccosXTest_b;
--fracXIsZero_uid28_fpArccosXTest(LOGICAL,27)@0
fracXIsZero_uid28_fpArccosXTest_a <= fracX_uid7_fpArccosXTest_b;
fracXIsZero_uid28_fpArccosXTest_b <= cstAllZWF_uid10_fpArccosXTest_q;
fracXIsZero_uid28_fpArccosXTest_q <= "1" when fracXIsZero_uid28_fpArccosXTest_a = fracXIsZero_uid28_fpArccosXTest_b else "0";
--expXIsMax_uid26_fpArccosXTest(LOGICAL,25)@0
expXIsMax_uid26_fpArccosXTest_a <= expX_uid6_fpArccosXTest_b;
expXIsMax_uid26_fpArccosXTest_b <= cstAllOWE_uid9_fpArccosXTest_q;
expXIsMax_uid26_fpArccosXTest_q <= "1" when expXIsMax_uid26_fpArccosXTest_a = expXIsMax_uid26_fpArccosXTest_b else "0";
--exc_I_uid29_fpArccosXTest(LOGICAL,28)@0
exc_I_uid29_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_b <= fracXIsZero_uid28_fpArccosXTest_q;
exc_I_uid29_fpArccosXTest_q <= exc_I_uid29_fpArccosXTest_a and exc_I_uid29_fpArccosXTest_b;
--InvFracXIsZero_uid30_fpArccosXTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpArccosXTest_a <= fracXIsZero_uid28_fpArccosXTest_q;
InvFracXIsZero_uid30_fpArccosXTest_q <= not InvFracXIsZero_uid30_fpArccosXTest_a;
--exc_N_uid31_fpArccosXTest(LOGICAL,30)@0
exc_N_uid31_fpArccosXTest_a <= expXIsMax_uid26_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_b <= InvFracXIsZero_uid30_fpArccosXTest_q;
exc_N_uid31_fpArccosXTest_q <= exc_N_uid31_fpArccosXTest_a and exc_N_uid31_fpArccosXTest_b;
--excRNaN_uid127_fpArccosXTest(LOGICAL,126)@0
excRNaN_uid127_fpArccosXTest_a <= exc_N_uid31_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_b <= exc_I_uid29_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_c <= xRegAndOutOfRange_uid126_fpArccosXTest_q;
excRNaN_uid127_fpArccosXTest_q <= excRNaN_uid127_fpArccosXTest_a or excRNaN_uid127_fpArccosXTest_b or excRNaN_uid127_fpArccosXTest_c;
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg(DELAY,1225)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid127_fpArccosXTest_q, xout => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem(DUALMEM,1226)
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_inputreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdreg_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab <= ld_pathSelBits_uid117_fpArccosXTest_q_to_fracOutMuxSelEnc_uid118_fpArccosXTest_a_replace_rdmux_q;
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_ia
);
ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid128_fpArccosXTest(BITJOIN,127)@40
excSelBits_uid128_fpArccosXTest_q <= ld_excRNaN_uid127_fpArccosXTest_q_to_excSelBits_uid128_fpArccosXTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0(REG,498)@40
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q <= excSelBits_uid128_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid129_fpArccosXTest(LOOKUP,128)@41
outMuxSelEnc_uid129_fpArccosXTest: PROCESS (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid128_fpArccosXTest_0_to_outMuxSelEnc_uid129_fpArccosXTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid129_fpArccosXTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid129_fpArccosXTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid129_fpArccosXTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid129_fpArccosXTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid129_fpArccosXTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1(REG,591)@41
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q <= outMuxSelEnc_uid129_fpArccosXTest_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid131_fpArccosXTest(MUX,130)@42
expRPostExc_uid131_fpArccosXTest_s <= reg_outMuxSelEnc_uid129_fpArccosXTest_0_to_expRPostExc_uid131_fpArccosXTest_1_q;
expRPostExc_uid131_fpArccosXTest: PROCESS (expRPostExc_uid131_fpArccosXTest_s, en, cstAllZWE_uid12_fpArccosXTest_q, expRCalc_uid125_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q, cstAllOWE_uid9_fpArccosXTest_q)
BEGIN
CASE expRPostExc_uid131_fpArccosXTest_s IS
WHEN "00" => expRPostExc_uid131_fpArccosXTest_q <= cstAllZWE_uid12_fpArccosXTest_q;
WHEN "01" => expRPostExc_uid131_fpArccosXTest_q <= expRCalc_uid125_fpArccosXTest_q;
WHEN "10" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN "11" => expRPostExc_uid131_fpArccosXTest_q <= cstAllOWE_uid9_fpArccosXTest_q;
WHEN OTHERS => expRPostExc_uid131_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid119_fpArccosXTest(BITSELECT,118)@42
piF_uid119_fpArccosXTest_in <= pi_uid85_fpArccosXTest_q(26 downto 0);
piF_uid119_fpArccosXTest_b <= piF_uid119_fpArccosXTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor(LOGICAL,1365)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a <= ld_singX_uid8_fpArccosXTest_b_to_path1ResFP_uid96_fpArccosXTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_a or ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena(REG,1366)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd(LOGICAL,1367)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid120_fpArccosXTest(BITSELECT,119)@13
Path2ResFP22dto0_uid120_fpArccosXTest_in <= path2ResFP_uid116_fpArccosXTest_q(22 downto 0);
Path2ResFP22dto0_uid120_fpArccosXTest_b <= Path2ResFP22dto0_uid120_fpArccosXTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg(DELAY,1355)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid120_fpArccosXTest_b, xout => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem(DUALMEM,1356)
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdreg_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab <= ld_reg_Path2ResFP30dto23_uid123_fpArccosXTest_0_to_expRCalc_uid125_fpArccosXTest_3_q_to_expRCalc_uid125_fpArccosXTest_d_replace_rdmux_q;
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3(REG,588)@41
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q <= ld_Path2ResFP22dto0_uid120_fpArccosXTest_b_to_reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid121_fpArccosXTest(BITSELECT,120)@41
Path1ResFP22dto0_uid121_fpArccosXTest_in <= path1ResFP_uid96_fpArccosXTest_q(22 downto 0);
Path1ResFP22dto0_uid121_fpArccosXTest_b <= Path1ResFP22dto0_uid121_fpArccosXTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2(REG,587)@41
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q <= Path1ResFP22dto0_uid121_fpArccosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid122_fpArccosXTest(MUX,121)@42
fracRCalc_uid122_fpArccosXTest_s <= fracOutMuxSelEnc_uid118_fpArccosXTest_q;
fracRCalc_uid122_fpArccosXTest: PROCESS (fracRCalc_uid122_fpArccosXTest_s, en, reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q, reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q, piF_uid119_fpArccosXTest_b, cstAllZWF_uid10_fpArccosXTest_q)
BEGIN
CASE fracRCalc_uid122_fpArccosXTest_s IS
WHEN "00" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path1ResFP22dto0_uid121_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_2_q;
WHEN "01" => fracRCalc_uid122_fpArccosXTest_q <= reg_Path2ResFP22dto0_uid120_fpArccosXTest_0_to_fracRCalc_uid122_fpArccosXTest_3_q;
WHEN "10" => fracRCalc_uid122_fpArccosXTest_q <= piF_uid119_fpArccosXTest_b;
WHEN "11" => fracRCalc_uid122_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN OTHERS => fracRCalc_uid122_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b(DELAY,706)@41
ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid129_fpArccosXTest_q, xout => ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid130_fpArccosXTest(MUX,129)@42
fracRPostExc_uid130_fpArccosXTest_s <= ld_outMuxSelEnc_uid129_fpArccosXTest_q_to_fracRPostExc_uid130_fpArccosXTest_b_q;
fracRPostExc_uid130_fpArccosXTest: PROCESS (fracRPostExc_uid130_fpArccosXTest_s, en, cstAllZWF_uid10_fpArccosXTest_q, fracRCalc_uid122_fpArccosXTest_q, cstAllZWF_uid10_fpArccosXTest_q, cstNaNWF_uid11_fpArccosXTest_q)
BEGIN
CASE fracRPostExc_uid130_fpArccosXTest_s IS
WHEN "00" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "01" => fracRPostExc_uid130_fpArccosXTest_q <= fracRCalc_uid122_fpArccosXTest_q;
WHEN "10" => fracRPostExc_uid130_fpArccosXTest_q <= cstAllZWF_uid10_fpArccosXTest_q;
WHEN "11" => fracRPostExc_uid130_fpArccosXTest_q <= cstNaNWF_uid11_fpArccosXTest_q;
WHEN OTHERS => fracRPostExc_uid130_fpArccosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid132_fpArccosXTest(BITJOIN,131)@42
sR_uid132_fpArccosXTest_q <= GND_q & expRPostExc_uid131_fpArccosXTest_q & fracRPostExc_uid130_fpArccosXTest_q;
--xOut(GPOUT,4)@42
q <= sR_uid132_fpArccosXTest_q;
end normal;
|
---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : z126_01_wb_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wb_pkg.vhd,v $
-- Revision 1.1 2014/03/03 17:49:58 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE z126_01_wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
bte : std_logic_vector(1 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END z126_01_wb_pkg;
PACKAGE BODY z126_01_wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.bte <= wbo_0.bte;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity Mux4to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(1 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end Mux4to1;
architecture rtl of Mux4to1 is
begin
process(sel, i01, i02, i03, i04)
begin
case sel is
when "00" => mux_out <= i01;
when "01" => mux_out <= i02;
when "10" => mux_out <= i03;
when "11" => mux_out <= i04;
when others => mux_out <= x"0000";
end case;
end process;
end rtl; |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.t80_pack.all;
entity t80 is
generic(
t80mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end t80;
architecture rtl of t80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : t80_mcode
generic map(
t80mode => t80mode
)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : t80_alu
generic map(
t80mode => t80mode
)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if t80mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if t80mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif t80mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if t80mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(5) <= not ACC(5);
F(4) <= '1';
F(3) <= not ACC(3);
F(1) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(0) <= not F(0);
F(5) <= ACC(5);
F(4) <= F(0);
F(3) <= ACC(3);
F(1) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(0) <= '1';
F(5) <= ACC(5);
F(4) <= '0';
F(3) <= ACC(3);
F(1) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(2) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(2) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if t80mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(0) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(4) <= '0';
F(1) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(6) <= '1';
else
F(6) <= '0';
end if;
F(7) <= DI_Reg(7);
F(2) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(3) <= ALU_Q(3);
F(5) <= ALU_Q(1);
F(4) <= '0';
F(1) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(2) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and t80mode < 2 then
IncDecZ <= F_Out(6);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : t80_reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(2))) or
(I_BC and (not IR(4) or F(6) or not F(2))) or
(I_BTR and (not IR(4) or F(6)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and t80mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and t80mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_sfifo_15x128_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF k7_sfifo_15x128_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: k7_sfifo_15x128_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: k7_sfifo_15x128_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: k7_sfifo_15x128_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
k7_sfifo_15x128_inst : k7_sfifo_15x128_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_command_rec_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(4-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(4-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
--
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr_ctrl_ip_phy_alt_mem_phy_record_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr_ctrl_ip_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_ram;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr_ctrl_ip_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr_ctrl_ip_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_admin;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_mmi;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_dgrb;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_dgwb;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr_ctrl_ip_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr_ctrl_ip_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr_ctrl_ip_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr_ctrl_ip_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr_ctrl_ip_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr_ctrl_ip_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
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