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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_AND_MODULUS_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR(1 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end DIVIDER_AND_MODULUS_32b;
-- ready = 0 indique que le circuit est pret a calculer
-- 1 signifie que le circuit est occupe
-- nready = 1 indique que le calcul est termine (1 cycle suffit)
architecture behav of DIVIDER_AND_MODULUS_32b is
signal buf : STD_LOGIC_VECTOR(63 downto 0);
signal dbuf : STD_LOGIC_VECTOR(31 downto 0);
signal sm : INTEGER range 0 to 32;
alias buf1 is buf(63 downto 32);
alias buf2 is buf(31 downto 0);
signal fFunction : std_logic;
begin
ICC <= "0000";
-------------------------------------------------------------------------
reg : process(rst, clk)
variable sready, snready : std_logic;
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
fFunction <= '0';
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
if( fFunction = '1' ) then
OUTPUT_1 <= buf2; -- ON RETOURNE LE RESULTAT DE LA DIVISION
else
OUTPUT_1 <= buf1; -- ON RETOURNE LE RESTE DE LA DIVISION (MODULO)
end if;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
fFunction <= FONCTION(0);
else
sm <= sm;
end if;
-- Tous les autres états sont utiles au calcul
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
if buf(62 downto 31) >= dbuf then
buf1 <= '0' & (buf(61 downto 31) - dbuf(30 downto 0));
buf2 <= buf2(30 downto 0) & '1';
else
buf <= buf(62 downto 0) & '0';
end if;
if sm /= 32 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- Fin du process de calcul
end if;
end process;
end behav;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leon
-- File: leon.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Complete processor
------------------------------------------------------------------------------
-- modified for ddm 8.02.02 LA
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity leon is
port (
resetn : in std_logic; -- system signals
clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0); -- memory bus
---
data : inout std_logic_vector(31 downto 0); -- 32 bits conversion LA
---
ramsn : out std_logic_vector(3 downto 0);
ramoen : out std_logic_vector(3 downto 0);
rwen : inout std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : inout std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
---
pio : inout std_logic_vector(15 downto 0); -- I/O port 32 bits LA
buttons : in std_logic_vector(3 downto 0); -- ddm ports
audioin : in std_logic;
digit0 : out std_logic_vector(6 downto 0);
digit1 : out std_logic_vector(6 downto 0);
audioout : out std_logic;
lr_out : out std_logic;
shift_clk : out std_logic;
mclk : out std_logic;
dispen : out std_logic;
---
wdogn : out std_logic; -- watchdog output
test : in std_logic
);
end;
architecture rtl of leon is
component mcore
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
--
ddmi : in ddm_in_type; -- DDM signals LA
ddmo : out ddm_out_type;
--
test : in std_logic
);
end component;
signal gnd, clko, resetno : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
--
signal ddmi : ddm_in_type; -- DDM signals LA
signal ddmo : ddm_out_type;
--
begin
gnd <= '0';
-- main processor core
mcore0 : mcore
port map (
resetn => resetno, clk => clko,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
-- pcii => pcii, pcio => pcio, test => test
pcii => pcii, pcio => pcio, ddmi => ddmi, ddmo => ddmo, test => test -- DDM LA
);
-- pads
-- clk_pad : inpad port map (clk, clko); -- clock
clko <= clk; -- avoid buffering during synthesis
--original lines
reset_pad : smpad port map (resetn, resetno); -- reset
brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
--DDM lines
inpad4 : inpad port map (audioin, ddmi.audioin);
inpad5 : inpad port map (buttons(0),ddmi.button0);
inpad6 : inpad port map (buttons(1),ddmi.button1);
inpad7 : inpad port map (buttons(2),ddmi.button2);
inpad8 : inpad port map (buttons(3),ddmi.button3);
d_pads: for i in 0 to 31 generate -- data bus
d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
end generate;
-- dataout <= memo.data; -- databus DDM LA
-- memi.data <= datain;
-- datasel <= memo.bdrive;
pio_pads : for i in 0 to 15 generate -- parallel I/O port
pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
end generate;
-- pioo <= ioo.piol; -- parallel I/O port DDM
-- ioi.piol <= pioi;
-- piod <= ioo.piodir;
-- rwen(0) <= memo.wrn(0);
-- memi.wrn(0) <= memo.wrn(0);
-- rwen(1) <= memo.wrn(1);
-- memi.wrn(1) <= memo.wrn(1);
-- rwen(2) <= memo.wrn(2);
-- memi.wrn(2) <= memo.wrn(2);
-- rwen(3) <= memo.wrn(3);
-- memi.wrn(3) <= memo.wrn(3);
rwen_pads : for i in 0 to 3 generate -- ram write strobe
rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
end generate;
-- I/O write strobe
writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
-- writen <= memo.writen; -- DDM LA
-- memi.writen <= memo.writen;
--
a_pads: for i in 0 to 27 generate -- memory address
a_pad : outpad generic map (3) port map (memo.address(i), address(i));
end generate;
ramsn_pads : for i in 0 to 3 generate -- ram oen/rasn
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
end generate;
ramoen_pads : for i in 0 to 3 generate -- ram chip select
eamoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
end generate;
romsn_pads : for i in 0 to 1 generate -- rom chip select
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
end generate;
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
--
outpadb7: outpad port map (ddmo.shift_clk, shift_clk); -- DDM
outpadb8: outpad port map (ddmo.lr_out, lr_out);
outpadb9: outpad port map (ddmo.audioout, audioout);
outpadb10: for i in 0 to 6 generate
outpad101: outpad port map(ddmo.digit0(i), digit0(i));
end generate;
outpadb11: for i in 0 to 6 generate
outpad111: outpad port map(ddmo.digit1(i), digit1(i));
end generate;
outpadb12: outpad port map (ddmo.mclk, mclk);
dispen <= ddmo.dispen;
--
wd : if WDOGEN generate
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
end generate;
end ;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- PIO Access Controller (common for OCIDEC 2 and above) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ---
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 9th, 2001
-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd
--
--
-- CVS Log
--
-- $Id: atahost_pio_actrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_actrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
---------------------------
-- PIO Access controller --
---------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_pio_actrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
SelDev : in std_logic; -- Selected device
go : in std_logic; -- Start transfer sequence
done : out std_logic; -- Transfer sequence done
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
a : in std_logic_vector(3 downto 0):="0000"; -- PIO transfer address
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
oe : out std_logic; -- DDbus output-enable signal
DIOR,
DIOW : out std_logic;
IORDY : in std_logic
);
end entity atahost_pio_actrl;
architecture structural of atahost_pio_actrl is
--
-- Component declarations
--
component atahost_pio_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing/control register settings
IORDY_en : in std_logic; -- use IORDY (or not)
T1 : in std_logic_vector(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
T2 : in std_logic_vector(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
T4 : in std_logic_vector(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- PIO controller selected (strobe signal)
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
-- return signals
oe : out std_logic; -- output enable signal
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe, latch data (during read)
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic; -- IOwrite signal, active high
IORDY : in std_logic -- IORDY signal
);
end component atahost_pio_tctrl;
signal dstrb : std_logic;
signal T1, T2, T4, Teoc : std_logic_vector(TWIDTH -1 downto 0);
signal IORDYen : std_logic;
begin
--
--------------------------
-- PIO transfer control --
--------------------------
--
-- capture ATA data for PIO access
gen_PIOq: process(clk)
begin
if (clk'event and clk = '1') then
if (dstrb = '1') then
q <= DDi;
end if;
end if;
end process gen_PIOq;
--
-- PIO timing controllers
--
-- select timing settings for the addressed port
sel_port_t: process(clk)
variable Asel : std_logic; -- address selected
variable iT1, iT2, iT4, iTeoc : std_logic_vector(TWIDTH -1 downto 0);
variable iIORDYen : std_logic;
begin
if (clk'event and clk = '1') then
-- initially set timing registers to compatible timing
iT1 := cmdport_T1;
iT2 := cmdport_T2;
iT4 := cmdport_T4;
iTeoc := cmdport_Teoc;
iIORDYen := cmdport_IORDYen;
-- detect data-port access
Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port
if (Asel = '1') then -- data port selected, 16bit transfers
if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ?
iT1 := dport1_T1;
iT2 := dport1_T2;
iT4 := dport1_T4;
iTeoc := dport1_Teoc;
iIORDYen := dport1_IORDYen;
elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ?
iT1 := dport0_T1;
iT2 := dport0_T2;
iT4 := dport0_T4;
iTeoc := dport0_Teoc;
iIORDYen := dport0_IORDYen;
end if;
end if;
T1 <= iT1;
T2 <= iT2;
T4 <= iT4;
Teoc <= iTeoc;
IORDYen <= iIORDYen;
end if;
end process sel_port_t;
--
-- hookup timing controller
--
PIO_timing_controller: atahost_pio_tctrl
generic map (
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
IORDY_en => IORDYen,
T1 => T1,
T2 => T2,
T4 => T4,
Teoc => Teoc,
go => go,
we => dir,
oe => oe,
done => done,
dstrb => dstrb,
DIOR => dior,
DIOW => diow,
IORDY => IORDY
);
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- PIO Access Controller (common for OCIDEC 2 and above) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ---
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 9th, 2001
-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd
--
--
-- CVS Log
--
-- $Id: atahost_pio_actrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_actrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
---------------------------
-- PIO Access controller --
---------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_pio_actrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
SelDev : in std_logic; -- Selected device
go : in std_logic; -- Start transfer sequence
done : out std_logic; -- Transfer sequence done
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
a : in std_logic_vector(3 downto 0):="0000"; -- PIO transfer address
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
oe : out std_logic; -- DDbus output-enable signal
DIOR,
DIOW : out std_logic;
IORDY : in std_logic
);
end entity atahost_pio_actrl;
architecture structural of atahost_pio_actrl is
--
-- Component declarations
--
component atahost_pio_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing/control register settings
IORDY_en : in std_logic; -- use IORDY (or not)
T1 : in std_logic_vector(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
T2 : in std_logic_vector(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
T4 : in std_logic_vector(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- PIO controller selected (strobe signal)
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
-- return signals
oe : out std_logic; -- output enable signal
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe, latch data (during read)
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic; -- IOwrite signal, active high
IORDY : in std_logic -- IORDY signal
);
end component atahost_pio_tctrl;
signal dstrb : std_logic;
signal T1, T2, T4, Teoc : std_logic_vector(TWIDTH -1 downto 0);
signal IORDYen : std_logic;
begin
--
--------------------------
-- PIO transfer control --
--------------------------
--
-- capture ATA data for PIO access
gen_PIOq: process(clk)
begin
if (clk'event and clk = '1') then
if (dstrb = '1') then
q <= DDi;
end if;
end if;
end process gen_PIOq;
--
-- PIO timing controllers
--
-- select timing settings for the addressed port
sel_port_t: process(clk)
variable Asel : std_logic; -- address selected
variable iT1, iT2, iT4, iTeoc : std_logic_vector(TWIDTH -1 downto 0);
variable iIORDYen : std_logic;
begin
if (clk'event and clk = '1') then
-- initially set timing registers to compatible timing
iT1 := cmdport_T1;
iT2 := cmdport_T2;
iT4 := cmdport_T4;
iTeoc := cmdport_Teoc;
iIORDYen := cmdport_IORDYen;
-- detect data-port access
Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port
if (Asel = '1') then -- data port selected, 16bit transfers
if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ?
iT1 := dport1_T1;
iT2 := dport1_T2;
iT4 := dport1_T4;
iTeoc := dport1_Teoc;
iIORDYen := dport1_IORDYen;
elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ?
iT1 := dport0_T1;
iT2 := dport0_T2;
iT4 := dport0_T4;
iTeoc := dport0_Teoc;
iIORDYen := dport0_IORDYen;
end if;
end if;
T1 <= iT1;
T2 <= iT2;
T4 <= iT4;
Teoc <= iTeoc;
IORDYen <= iIORDYen;
end if;
end process sel_port_t;
--
-- hookup timing controller
--
PIO_timing_controller: atahost_pio_tctrl
generic map (
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
IORDY_en => IORDYen,
T1 => T1,
T2 => T2,
T4 => T4,
Teoc => Teoc,
go => go,
we => dir,
oe => oe,
done => done,
dstrb => dstrb,
DIOR => dior,
DIOW => diow,
IORDY => IORDY
);
end architecture structural;
|
-- $Id: cmoda7_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cmoda7_dummy - syn
-- Description: cmoda7 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_cmoda7
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cmoda7_dummy is -- CmodA7 dummy (base; loopback)
-- implements cmoda7_aif
port (
I_CLK12 : in slbit; -- 12 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3 -- c7 rgb-led 0 (act.low)
);
end cmoda7_dummy;
architecture syn of cmoda7_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_BTN; -- mirror BTN on LED
O_RGBLED0_N(0) <= not I_BTN(0); -- mirror BTN on RGBLED 0 -> red
O_RGBLED0_N(1) <= not I_BTN(1); -- 1 -> green
O_RGBLED0_N(2) <= not (I_BTN(0) and I_BTN(1)); -- 0+1 -> white
end syn;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic (
BITS: integer:= 4
);
port (
clk: in std_logic;
en: in std_logic;
rst: in std_logic;
count: out std_logic_vector(BITS-1 downto 0)
);
end counter;
architecture behav_counter of counter is
signal tmp_count: std_logic_vector(count'range):= (others => '0');
begin
count <= tmp_count;
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
tmp_count <= (others => '0');
elsif en = '1' then
tmp_count <= std_logic_vector(unsigned(tmp_count) + 1);
end if;
end if;
end process;
end behav_counter;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity VHDL_PLANB is
port
(
inclk:in std_logic:='0';
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0'
);
end entity;
architecture RTL of VHDL_PLANB is
component PLL is
port
(
inclk0:in std_logic;
c0,c1,c2:out std_logic
);
end component;
component DECODER is
generic
(
constant fpr:integer:=360
);
port
(
inclk,rst:in std_logic;
control_begin:out std_logic:='0';
load_next:in std_logic;
fifo_aclr:out std_logic:='0';
fifo_en_w_1:out std_logic:='0';
fifo_en_w_2:out std_logic:='0';
fifo_en_w_3:out std_logic:='0';
fifo_data_1:out std_logic_vector(127 downto 0);
fifo_data_2:out std_logic_vector(127 downto 0);
fifo_data_3:out std_logic_vector(127 downto 0)
);
end component;
component LED is
generic
(
constant cpd:integer:=6666 ------------count per one degree（inclk下）
);
port
(
inclk:in std_logic;
rst:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
control_begin:in std_logic;
fifo_change:out std_logic;
fifo_en_r:out std_logic;
fifo_data_1:in std_logic_vector(127 downto 0);
fifo_data_2:in std_logic_vector(127 downto 0);
fifo_data_3:in std_logic_vector(127 downto 0)
);
end component;
component FIFO is
port
(
aclr:in std_logic:= '0';
data:in std_logic_vector(127 downto 0);
rdclk:in std_logic;
rdreq:in std_logic;
wrclk:in std_logic;
wrreq:in std_logic;
q:out std_logic_vector(127 downto 0)
);
end component;
signal rst:std_logic:='0';
signal clk_decoder,clk_led,clk_main:std_logic;
signal control_begin:std_logic;
signal load_next:std_logic:='0';
signal fifo_change,fifo_change_last:std_logic;
signal fifo_aclr:std_logic:='0';
signal fifo_clk_w:std_logic:='0';
signal fifo_en_w_1:std_logic:='0';
signal fifo_en_w_2:std_logic:='0';
signal fifo_en_w_3:std_logic:='0';
signal fifo_data_dec_1:std_logic_vector(127 downto 0);
signal fifo_data_dec_2:std_logic_vector(127 downto 0);
signal fifo_data_dec_3:std_logic_vector(127 downto 0);
signal fifo_en_r:std_logic:='0';
signal fifo_clk_r:std_logic:='0';
signal fifo_data_led_1:std_logic_vector(127 downto 0);
signal fifo_data_led_2:std_logic_vector(127 downto 0);
signal fifo_data_led_3:std_logic_vector(127 downto 0);
signal fifo_aclr_a:std_logic:='0';
signal fifo_en_w_1_a:std_logic:='0';
signal fifo_en_w_2_a:std_logic:='0';
signal fifo_en_w_3_a:std_logic:='0';
signal fifo_data_dec_1_a:std_logic_vector(127 downto 0);
signal fifo_data_dec_2_a:std_logic_vector(127 downto 0);
signal fifo_data_dec_3_a:std_logic_vector(127 downto 0);
signal fifo_en_r_a:std_logic:='0';
signal fifo_data_led_1_a:std_logic_vector(127 downto 0);
signal fifo_data_led_2_a:std_logic_vector(127 downto 0);
signal fifo_data_led_3_a:std_logic_vector(127 downto 0);
signal fifo_aclr_b:std_logic:='0';
signal fifo_en_w_1_b:std_logic:='0';
signal fifo_en_w_2_b:std_logic:='0';
signal fifo_en_w_3_b:std_logic:='0';
signal fifo_data_dec_1_b:std_logic_vector(127 downto 0);
signal fifo_data_dec_2_b:std_logic_vector(127 downto 0);
signal fifo_data_dec_3_b:std_logic_vector(127 downto 0);
signal fifo_en_r_b:std_logic:='0';
signal fifo_data_led_1_b:std_logic_vector(127 downto 0);
signal fifo_data_led_2_b:std_logic_vector(127 downto 0);
signal fifo_data_led_3_b:std_logic_vector(127 downto 0);
begin
CLOCK:PLL
port map
(
inclk0=>inclk,
c0=>clk_led,
c1=>clk_decoder,
c2=>clk_main
);
DECODER1:DECODER
port map
(
inclk=>clk_decoder,
rst=>rst,
control_begin=>control_begin,
load_next=>load_next,
fifo_aclr=>fifo_aclr,
fifo_en_w_1=>fifo_en_w_1,
fifo_en_w_2=>fifo_en_w_2,
fifo_en_w_3=>fifo_en_w_3,
fifo_data_1=>fifo_data_dec_1,
fifo_data_2=>fifo_data_dec_2,
fifo_data_3=>fifo_data_dec_3
);
LED1:LED
port map
(
inclk=>clk_led,
rst=>rst,
data_buffer_a=>data_buffer_a,
data_buffer_b=>data_buffer_b,
data_buffer_c=>data_buffer_c,
en_row_a=>en_row_a,
en_row_b=>en_row_b,
en_row_c=>en_row_c,
en_col_a_1=>en_col_a_1,en_col_a_2=>en_col_a_2,en_col_a_3=>en_col_a_3,
en_col_b_1=>en_col_b_1,en_col_b_2=>en_col_b_2,en_col_b_3=>en_col_b_3,
en_col_c_1=>en_col_c_1,en_col_c_2=>en_col_c_2,en_col_c_3=>en_col_c_3,
control_begin=>control_begin,
fifo_change=>fifo_change,
fifo_en_r=>fifo_en_r,
fifo_data_1=>fifo_data_led_1,
fifo_data_2=>fifo_data_led_2,
fifo_data_3=>fifo_data_led_3
);
FIFO1A:FIFO
port map
(
aclr=>fifo_aclr_a,
data=>fifo_data_dec_1_a,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_a,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_1_a,
q=>fifo_data_led_1_a
);
FIFO2A:FIFO
port map
(
aclr=>fifo_aclr_a,
data=>fifo_data_dec_2_a,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_a,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_2_a,
q=>fifo_data_led_2_a
);
FIFO3A:FIFO
port map
(
aclr=>fifo_aclr_a,
data=>fifo_data_dec_3_a,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_a,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_3_a,
q=>fifo_data_led_3_a
);
FIFO1B:FIFO
port map
(
aclr=>fifo_aclr_b,
data=>fifo_data_dec_1_b,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_b,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_1_b,
q=>fifo_data_led_1_b
);
FIFO2B:FIFO
port map
(
aclr=>fifo_aclr_b,
data=>fifo_data_dec_2_b,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_b,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_2_b,
q=>fifo_data_led_2_b
);
FIFO3B:FIFO
port map
(
aclr=>fifo_aclr_b,
data=>fifo_data_dec_3_b,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_b,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_3_b,
q=>fifo_data_led_3_b
);
fifo_data_dec_1_a<=fifo_data_dec_1;
fifo_data_dec_2_a<=fifo_data_dec_2;
fifo_data_dec_3_a<=fifo_data_dec_3;
fifo_data_dec_1_b<=fifo_data_dec_1;
fifo_data_dec_2_b<=fifo_data_dec_2;
fifo_data_dec_3_b<=fifo_data_dec_3;
fifo_clk_w<=clk_decoder;
fifo_clk_r<=clk_led;
MAIN:process(clk_main,rst)
begin
if rst='1' then
fifo_aclr_a<=fifo_aclr;
fifo_en_r_a<=fifo_en_r;
fifo_en_w_1_a<=fifo_en_w_1;
fifo_en_w_2_a<=fifo_en_w_2;
fifo_en_w_3_a<=fifo_en_w_3;
fifo_data_led_1<=fifo_data_led_1_a;
fifo_data_led_2<=fifo_data_led_2_a;
fifo_data_led_3<=fifo_data_led_3_a;
elsif rising_edge(clk_main) then
fifo_change_last<=fifo_change;
if control_begin='0' then
fifo_aclr_a<=fifo_aclr;
fifo_en_r_a<=fifo_en_r;
fifo_en_w_1_a<=fifo_en_w_1;
fifo_en_w_2_a<=fifo_en_w_2;
fifo_en_w_3_a<=fifo_en_w_3;
fifo_data_led_1<=fifo_data_led_1_a;
fifo_data_led_2<=fifo_data_led_2_a;
fifo_data_led_3<=fifo_data_led_3_a;
elsif fifo_change='1' then
fifo_en_r_b<=fifo_en_r;
fifo_data_led_1<=fifo_data_led_1_b;
fifo_data_led_2<=fifo_data_led_2_b;
fifo_data_led_3<=fifo_data_led_3_b;
fifo_aclr_b<='0';
fifo_en_w_1_b<='0';
fifo_en_w_2_b<='0';
fifo_en_w_3_b<='0';
fifo_aclr_a<=fifo_aclr;
fifo_en_w_1_a<=fifo_en_w_1;
fifo_en_w_2_a<=fifo_en_w_2;
fifo_en_w_3_a<=fifo_en_w_3;
fifo_en_r_a<='0';
elsif fifo_change='0' then
fifo_en_r_a<=fifo_en_r;
fifo_data_led_1<=fifo_data_led_1_a;
fifo_data_led_2<=fifo_data_led_2_a;
fifo_data_led_3<=fifo_data_led_3_a;
fifo_aclr_a<='0';
fifo_en_w_1_a<='0';
fifo_en_w_2_a<='0';
fifo_en_w_3_a<='0';
fifo_aclr_b<=fifo_aclr;
fifo_en_w_1_b<=fifo_en_w_1;
fifo_en_w_2_b<=fifo_en_w_2;
fifo_en_w_3_b<=fifo_en_w_3;
fifo_en_r_b<='0';
end if;
if fifo_change_last/=fifo_change then
load_next<='1';
else
load_next<='0';
end if;
end if;
end process;
end RTL; |
-- Address decoder
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.memory_map.all;
entity addrdec is
port(A : in addr_t;
cs : out memchipsel_t);
end addrdec;
architecture behav of addrdec is
begin
-- FIXME use a loop over the mmap array instead
cs <= mmap(0).chip_select when inside(A, mmap(0).base, mmap(0).size) else -- RAM
mmap(1).chip_select when inside(A, mmap(1).base, mmap(1).size) else -- ROM
mmap(2).chip_select when inside(A, mmap(2).base, mmap(2).size) else -- LEDs
mmap(3).chip_select when inside(A, mmap(3).base, mmap(3).size) else -- DIP-Switch
mmap(4).chip_select when inside(A, mmap(4).base, mmap(4).size) else -- Pushbuttons
mmap(5).chip_select when inside(A, mmap(5).base, mmap(5).size) else -- UART
mmap(6).chip_select when inside(A, mmap(6).base, mmap(6).size) else -- VRAM
mmap(7).chip_select when inside(A, mmap(7).base, mmap(7).size); -- Video configuration
-- We need dual-ported RAM for the framebuffer,
-- lest we've to deal with bus arbitration.
-- That's why the VRAM is separate from the RAM
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity pcu_tb is
end pcu_tb;
architecture Behavior of pcu_tb is
constant I_clk_period : time := 10 ns;
signal I_clk, I_reset : std_logic := '0';
signal I_en: std_logic := '1';
signal I_op: pcuops_t;
signal I_data, O_data, O_trapret: std_logic_vector(XLEN-1 downto 0);
begin
-- instantiate unit under test
uut: entity work.pcu port map(
I_clk => I_clk,
I_en => I_en,
I_reset => I_reset,
I_op => I_op,
I_data => I_data,
O_data => O_data,
O_trapret => O_trapret
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- test setting the program counter
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
-- test entering and returning from a trap
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
I_data <= X"BEEFCAFE";
I_op <= PCU_ENTERTRAP;
wait until falling_edge(I_clk);
assert O_data = TRAP_VECTOR report "wrong value" severity failure;
I_op <= PCU_RETTRAP;
wait until falling_edge(I_clk);
assert O_data = X"BEEFCAFE" report "wrong value" severity failure;
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
assert O_trapret = X"BEEFCAFE" report "wrong value" severity failure;
-- test entering and returning from an interrupt
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
I_data <= X"BEEFCAFE";
I_op <= PCU_ENTERINT;
wait until falling_edge(I_clk);
assert O_data = INTERRUPT_VECTOR report "wrong value" severity failure;
I_op <= PCU_RETINT;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture; |
entity top_vhdl is
generic (WIDTH : integer := 1; INIT : bit := '1'; greeting : string(1 to 9) := "hello ");
port (clk : in bit; i : in bit_vector(WIDTH-1 downto 0); o : out bit := INIT);
end entity;
architecture rtl of top_vhdl is
begin
process
begin
report greeting;
--wait;
end process;
process (clk)
begin
if rising_edge(clk) then
o <= xor i;
end if;
end process;
end rtl;
|
entity top_vhdl is
generic (WIDTH : integer := 1; INIT : bit := '1'; greeting : string(1 to 9) := "hello ");
port (clk : in bit; i : in bit_vector(WIDTH-1 downto 0); o : out bit := INIT);
end entity;
architecture rtl of top_vhdl is
begin
process
begin
report greeting;
--wait;
end process;
process (clk)
begin
if rising_edge(clk) then
o <= xor i;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- $Id: gcpad_comp-p.vhd,v 1.1 2004-10-10 10:09:15 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package gcpad_comp is
component gcpad_basic
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
pad_data_io : inout std_logic;
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_z_o : out std_logic;
but_start_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
ana_joy_x_o : out std_logic_vector(7 downto 0);
ana_joy_y_o : out std_logic_vector(7 downto 0);
ana_c_x_o : out std_logic_vector(7 downto 0);
ana_c_y_o : out std_logic_vector(7 downto 0);
ana_l_o : out std_logic_vector(7 downto 0);
ana_r_o : out std_logic_vector(7 downto 0)
);
end component;
component gcpad_full
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
pad_timeout_o : out std_logic;
tx_size_i : in std_logic_vector( 1 downto 0);
tx_command_i : in std_logic_vector(23 downto 0);
rx_size_i : in std_logic_vector( 3 downto 0);
rx_data_o : out std_logic_vector(63 downto 0);
pad_data_io : inout std_logic
);
end component;
end gcpad_comp;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: LIST.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY LIST IS
PORT
(
address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END LIST;
ARCHITECTURE SYN OF list IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./VHDL/VOICE/LIST.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 9,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./VHDL/VOICE/LIST.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./VHDL/VOICE/LIST.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL LIST.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL LIST.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL LIST.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL LIST.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL LIST_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- $Id: pdp11_decode.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_decode - syn
-- Description: pdp11: instruction decoder
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.0.8 rename _gpr -> _gr
-- 2022-10-03 1301 1.0.7 add STAT.is_dstpcmode1
-- 2011-11-18 427 1.0.6 now numeric_std clean
-- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit
-- 2008-11-30 174 1.0.4 BUGFIX: add updt_dstadsrc; set for MFP(I/D)
-- 2008-05-03 143 1.0.3 get fork_srcr,fork_dstr,fork_dsta assign out of if
-- 2008-04-27 139 1.0.2 BUGFIX: mtp now via do_fork_op; is_dsta logic mods
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end pdp11_decode;
architecture syn of pdp11_decode is
begin
proc_idecode: process (IREG)
alias OPCODE : slv4 is IREG(15 downto 12); -- basic opcode (upper 4 bits)
alias OPPRIM : slv3 is IREG(14 downto 12); -- basic opcode without B bit
alias OPBYTE : slbit is IREG(15); -- byte flag of basic opcode
alias OPEXT1 : slv3 is IREG(11 downto 9); -- extended opcode, part 1
alias OPEXT2 : slv3 is IREG(8 downto 6); -- extended opcode, part 2
alias OPEXT3 : slv3 is IREG(5 downto 3); -- extended opcode, part 3
alias OPEXT4 : slv3 is IREG(2 downto 0); -- extended opcode, part 4
alias SRCMODF : slv3 is IREG(11 downto 9); -- src register full mode
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
variable nstat : decode_stat_type;
variable is_srcr : slbit := '0'; -- source is read
variable is_dstr : slbit := '0'; -- destination is read
variable is_dstm : slbit := '0'; -- destination is modified
variable is_dstw : slbit := '0'; -- destination is written
variable is_srcmode0 : slbit := '0'; -- source is register mode
variable is_dstmode0notpc : slbit := '0'; -- dest. is register mode, not PC
begin
is_srcr := '0';
is_dstr := '0';
is_dstm := '0';
is_dstw := '0';
is_srcmode0 := '0';
is_dstmode0notpc := '0';
nstat.is_dstmode0 := '0';
nstat.is_srcpc := '0';
nstat.is_srcpcmode1 := '0';
nstat.is_dstpc := '0';
nstat.is_dstpcmode1 := '0';
nstat.is_dstw_reg := '0';
nstat.is_dstw_pc := '0';
nstat.is_rmwop := '0';
nstat.is_bytop := '0';
nstat.is_res := '1';
nstat.op_rtt := '0';
nstat.op_mov := '0';
nstat.trap_vec := "000";
nstat.force_srcsp := '0';
nstat.updt_dstadsrc := '0';
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
nstat.aunit_cc1op := '0';
nstat.aunit_ccmode := IREG(8 downto 6); -- STATIC
nstat.lunit_func := (others=>'0');
nstat.munit_func := (others=>'0');
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_op := (others=>'0');
nstat.fork_srcr := (others=>'0');
nstat.fork_dstr := (others=>'0');
nstat.fork_dsta := (others=>'0');
nstat.fork_opg := (others=>'0');
nstat.fork_opa := (others=>'0');
nstat.do_fork_op := '0';
nstat.do_fork_srcr := '0';
nstat.do_fork_dstr := '0';
nstat.do_fork_dsta := '0';
nstat.do_fork_opg := '0';
nstat.do_pref_dec := '0';
if SRCMODF = "000" then
is_srcmode0 := '1';
end if;
if DSTMODF = "000" then
nstat.is_dstmode0 := '1';
if DSTREG /= c_gr_pc then
is_dstmode0notpc := '1';
end if;
end if;
if SRCREG = c_gr_pc then
nstat.is_srcpc := '1';
if SRCMODF = "001" then
nstat.is_srcpcmode1 := '1';
end if;
end if;
if DSTREG = c_gr_pc then
nstat.is_dstpc := '1';
if DSTMODF = "001" then
nstat.is_dstpcmode1 := '1';
end if;
end if;
if OPPRIM = "000" then
if OPBYTE='0' and OPEXT1="000" then
if OPEXT2="000" and OPEXT3="000" then -- HALT,...,RTT
nstat.is_res := '0';
case OPEXT4 is
when "000" => -- HALT
nstat.fork_op := c_fork_op_halt;
nstat.do_fork_op := '1';
when "001" => -- WAIT
nstat.fork_op := c_fork_op_wait;
nstat.do_fork_op := '1';
when "010" => -- RTI
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
when "011" => -- BPT (trap to 14)
nstat.trap_vec := "011";
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
when "100" => -- IOT (trap to 20)
nstat.trap_vec := "100";
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
when "101" => -- RESET
nstat.fork_op := c_fork_op_reset;
nstat.do_fork_op := '1';
when "110" => -- RTT
nstat.op_rtt := '1';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
when others =>
nstat.is_res := '1';
end case;
end if;
if OPEXT2 = "001" then -- JMP
nstat.is_res := '0';
nstat.fork_opa := c_fork_opa_jmp;
nstat.do_fork_dsta := '1';
end if;
if OPEXT2 = "010" then
if OPEXT3 = "000" then -- RTS
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rts;
nstat.do_fork_op := '1';
end if;
if OPEXT3 = "011" then -- SPL
nstat.is_res := '0';
nstat.fork_op := c_fork_op_spl;
nstat.do_fork_op := '1';
end if;
end if;
if OPEXT2 = "010" then
if OPEXT3(2) = '1' then -- SEx/CLx
nstat.is_res := '0';
nstat.fork_op := c_fork_op_mcc;
nstat.do_fork_op := '1';
--!!!nstat.do_pref_dec := '1'; --??? ensure ireg_we ....
end if;
end if;
if OPEXT2 = "011" then -- SWAP
nstat.is_res := '0';
is_dstm := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lunit_func := c_lunit_func_swap;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if; -- OPBYTE='0' and OPEXT1="000"
if OPEXT1(2)='0' and -- BR class instructions
((OPBYTE='0' and OPEXT2(2)='1') or -- BR
(OPBYTE='0' and (OPEXT1(0)='1' or OPEXT1(1)='1')) or -- BNE,..,BLE
OPBYTE='1') then -- BPL,..,BCS
nstat.is_res := '0';
nstat.fork_op := c_fork_op_br;
nstat.do_fork_op := '1';
end if;
if OPBYTE='0' and OPEXT1="100" then -- JSR
nstat.is_res := '0';
nstat.fork_opa := c_fork_opa_jsr;
nstat.do_fork_dsta := '1';
end if;
if OPBYTE='1' and OPEXT1="100" then -- EMT, TRAP
nstat.is_res := '0';
if OPEXT2(2) = '0' then -- EMT (trap tp 30)
nstat.trap_vec := "110";
else -- TRAP (trap to 34)
nstat.trap_vec := "111";
end if;
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
end if;
if OPEXT1 = "101" then -- CLR(B),...,TST(B)
nstat.is_res := '0';
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.aunit_cc1op := '1';
case OPEXT2 is
when "000" => -- CLR: 0 + 0 + 0 (0)
is_dstw := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_zero;
nstat.aunit_cimod := c_aunit_mod_zero;
when "001" => -- COM: 0 + ~DST + 0 (~dst)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_zero;
when "010" => -- INC: 0 + DST + 1 (dst+1)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
when "011" => -- DEC: ~0 + DST + 0 (dst-1)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when "100" => -- NEG: 0 + ~DST + 1 (-dst)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
when "101" => -- ADC: 0 + DST + CI (dst+ci)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
when "110" => -- SBC: ~0 + DST + ~CI (dst-ci)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_inv;
when "111" => -- TST: 0 + DST + 0 (dst)
is_dstr := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when others => null;
end case;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
end if;
if OPEXT1 = "110" then
if OPEXT2(2) = '0' then -- ROR(B),...,ASL(B)
nstat.is_res := '0';
is_dstm := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.res_sel := c_dpath_res_lunit;
case OPEXT2(1 downto 0) is
when "00" => -- ROR
nstat.lunit_func := c_lunit_func_ror;
when "01" => -- ROL
nstat.lunit_func := c_lunit_func_rol;
when "10" => -- ASR
nstat.lunit_func := c_lunit_func_asr;
when "11" => -- ASL
nstat.lunit_func := c_lunit_func_asl;
when others => null;
end case;
end if;
if OPBYTE='0' and OPEXT2="100" then -- MARK
nstat.is_res := '0';
nstat.fork_op := c_fork_op_mark;
nstat.do_fork_op := '1';
end if;
if OPEXT2 = "101" then -- MFP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
if DSTREG = c_gr_sp then -- is dst reg == sp ?
nstat.updt_dstadsrc := '1'; -- ensure DSRC update in dsta flow
end if;
nstat.res_sel := c_dpath_res_ounit;
if nstat.is_dstmode0 = '1' then
nstat.fork_opa := c_fork_opa_mfp_reg;
else
nstat.fork_opa := c_fork_opa_mfp_mem;
end if;
nstat.do_fork_dsta := '1';
end if;
if OPEXT2 = "110" then -- MTP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_opa := c_fork_opa_mtp;
nstat.fork_op := c_fork_op_mtp;
nstat.do_fork_op := '1';
end if;
if OPBYTE='0' and OPEXT2="111" then -- SXT
nstat.is_res := '0';
is_dstw := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lunit_func := c_lunit_func_sxt;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if;
end if; -- OPPRIM="000"
if OPPRIM/="000" and OPPRIM/="111" then
nstat.is_res := '0';
case OPPRIM is
when "001" => -- MOV
is_srcr := '1';
is_dstw := '1';
nstat.op_mov := '1';
nstat.lunit_func := c_lunit_func_mov;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "010" => -- CMP
is_srcr := '1';
is_dstr := '1';
nstat.res_sel := c_dpath_res_aunit;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
nstat.is_bytop := OPBYTE;
when "011" => -- BIT
is_srcr := '1';
is_dstr := '1';
nstat.lunit_func := c_lunit_func_bit;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "100" => -- BIC
is_srcr := '1';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_bic;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "101" => -- BIS
is_srcr := '1';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_bis;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "110" =>
is_srcr := '1';
is_dstm := '1';
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '0' then -- ADD
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
else -- SUB
nstat.aunit_srcmod := c_aunit_mod_inv;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
end if;
when others => null;
end case;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_srcmode0 and is_dstmode0notpc;
end if;
if OPBYTE='0' and OPPRIM="111" then
case OPEXT1 is
when "000" => -- MUL
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_mul;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_mul;
nstat.do_fork_opg := '1';
when "001" => -- DIV
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_div;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_div;
nstat.do_fork_opg := '1';
when "010" => -- ASH
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_ash;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ash;
nstat.do_fork_opg := '1';
when "011" => -- ASHC
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_ashc;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ashc;
nstat.do_fork_opg := '1';
when "100" => -- XOR
nstat.is_res := '0';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_xor;
nstat.res_sel := c_dpath_res_lunit;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
when "111" => -- SOB: SRC + ~0 + 0 (src-1)
nstat.is_res := '0';
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_one;
nstat.aunit_cimod := c_aunit_mod_zero;
nstat.res_sel := c_dpath_res_aunit;
nstat.fork_op := c_fork_op_sob;
nstat.do_fork_op := '1';
when others => null;
end case;
end if;
if OPBYTE='1' and OPPRIM="111" then -- FPU
nstat.is_res := '1'; -- ??? FPU not yet handled
end if;
case SRCMOD is
when "00" => nstat.fork_srcr := c_fork_srcr_def;
when "01" => nstat.fork_srcr := c_fork_srcr_inc;
when "10" => nstat.fork_srcr := c_fork_srcr_dec;
when "11" => nstat.fork_srcr := c_fork_srcr_ind;
when others => null;
end case;
if is_srcr='1' and SRCMODF /="000" then
nstat.do_fork_srcr := '1';
end if;
case DSTMOD is
when "00" => nstat.fork_dstr := c_fork_dstr_def;
when "01" => nstat.fork_dstr := c_fork_dstr_inc;
when "10" => nstat.fork_dstr := c_fork_dstr_dec;
when "11" => nstat.fork_dstr := c_fork_dstr_ind;
when others => null;
end case;
if (is_dstr or is_dstm)='1' and nstat.is_dstmode0='0' then
nstat.do_fork_dstr := '1';
end if;
if is_dstw='1' and nstat.is_dstmode0='0' then
case DSTMOD is
when "00" => nstat.fork_opg := c_fork_opg_wdef;
when "01" => nstat.fork_opg := c_fork_opg_winc;
when "10" => nstat.fork_opg := c_fork_opg_wdec;
when "11" => nstat.fork_opg := c_fork_opg_wind;
when others => null;
end case;
end if;
if is_dstm='1' and nstat.is_dstmode0='0' then
nstat.is_rmwop := '1';
end if;
case DSTMOD is
when "00" => nstat.fork_dsta := c_fork_dsta_def;
when "01" => nstat.fork_dsta := c_fork_dsta_inc;
when "10" => nstat.fork_dsta := c_fork_dsta_dec;
when "11" => nstat.fork_dsta := c_fork_dsta_ind;
when others => null;
end case;
if (is_dstw or is_dstm)='1' and nstat.is_dstmode0='1' then
nstat.is_dstw_reg := '1';
if DSTREG = c_gr_pc then
nstat.is_dstw_pc := '1'; --??? hack rename -> is_dstw_pc
end if;
end if;
STAT <= nstat;
end process proc_idecode;
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag_bsd is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end;
architecture struct of ahbjtag_bsd is
-- Set REREAD to 1 to include support for re-read operation when host reads
-- out data register before jtagcom has completed the current AMBA access and
-- returned to state 'shft'.
constant REREAD : integer := 1;
constant REVISION : integer := REREAD;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal trst: std_ulogic;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG, version => REVISION)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
jtagcom0 : jtagcom generic map (isel => 1, nsync => nsync, ainst => ainst, dinst => dinst, reread => REREAD)
port map (rst, clk, ltapo, ltapi, dmao, dmai, tck, trst);
ltapo.asel <= asel;
ltapo.dsel <= dsel;
ltapo.tck <= tck;
ltapo.tdi <= regi;
ltapo.shift <= shift;
ltapo.reset <= '0';
ltapo.inst <= (others => '0');
rego <= ltapi.tdo;
trst <= '1';
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2552.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02552ent IS
END c07s03b06x00p02n01i02552ent;
ARCHITECTURE c07s03b06x00p02n01i02552arch OF c07s03b06x00p02n01i02552ent IS
BEGIN
TESTING: PROCESS
type CELL;
type LINK is access CELL;
type CELL is
record
VALUE : Integer;
SUCC : LINK;
PRED : LINK;
end record;
variable HEAD : LINK := CELL'(0,null,null); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02552 - Missing keyword 'new'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02552arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2552.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02552ent IS
END c07s03b06x00p02n01i02552ent;
ARCHITECTURE c07s03b06x00p02n01i02552arch OF c07s03b06x00p02n01i02552ent IS
BEGIN
TESTING: PROCESS
type CELL;
type LINK is access CELL;
type CELL is
record
VALUE : Integer;
SUCC : LINK;
PRED : LINK;
end record;
variable HEAD : LINK := CELL'(0,null,null); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02552 - Missing keyword 'new'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02552arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2552.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02552ent IS
END c07s03b06x00p02n01i02552ent;
ARCHITECTURE c07s03b06x00p02n01i02552arch OF c07s03b06x00p02n01i02552ent IS
BEGIN
TESTING: PROCESS
type CELL;
type LINK is access CELL;
type CELL is
record
VALUE : Integer;
SUCC : LINK;
PRED : LINK;
end record;
variable HEAD : LINK := CELL'(0,null,null); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02552 - Missing keyword 'new'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02552arch;
|
architecture rtl of fifo is
variable sig8 : record_type_3(
element1
(7 downto 0),
element2
(4 downto 0)
(7 downto 0)
(
elementA
(7 downto 0)
,
elementB
(3 downto 0)
),
element3
(3 downto 0)(elementC
(4 downto 1), elementD
(1 downto 0)),
element5(
elementE
(3 downto 0)
(6 downto 0)
,
elementF
(7 downto 0)
),
element6
(4 downto 0),
element7
(7 downto 0));
variable sig9 : t_data_struct(data
(7 downto 0));
variable sig9 : t_data_struct(
data
(7 downto 0)
);
begin
end architecture rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JbNPBNpXbzuCwqgfHXUo0CKKEKC3Ho/iDaBCfitnTvxhsxRdUSR+0FKa3WYZUyjB2Z1sYIx38tJN
kYcRKuulNw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Xrp9ZJjhK/C3GJtMOsmRzTUEbRl2EBjbyuEuTSHK7VnCStmz9bwb1qqcx42ppFcN4Q+NNJ6flNsF
w+jn1v7FOyUPatbu8FGMX0d+7XgBqyxTKHsKB7a8WxQdj3m7kZ+0Lt8HeEQmDSm1hf92P2UK/lMz
DTJSXRKzQLVDGFy3FhE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pUhTZHUcvfC0l0Wv/zVU2R+sEdbuTgRSFqizxBK1jXfPlevnfJLxD3mPcqZUIjfxMcwejwCYoHW9
FUYBs6+JwoKOPVs1+ZtAuD8DD6EmogGPiXZkcv8L6x2RsSmHTS92H6VaLwDblyw/WMIUSUuLdQts
I88fEgHdySUUq6WrYpIXQD0EBJPmKqZJbrFuTtq1PS/qjMol3SEnURJS/dau1Xpd1wWMINfb0/1m
BPYG7W1FMHUQTtD7SXTGmku2M5Y9wTu8Y8ljP+Ge2Ce16NhY+X2ydX53MFvu7ecWL1XvMuBMC4gO
Na0Pg0TU0opPWLn10PDv0Xr1YLpRvRmrKKIShw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
zDVnhZy4E1e3OP9tU497xmUl33nFyu4HKQVE5eObofuMxmGgfby/SvrhmKykT8NrMGtDeBz1dh1/
jNN2T3aJreiokb9l70PMKrlWgJ6R0+xdwt6Y/OEdOvzF4ZEQgdoKWv6J0FOh2ONqNXdjAsaY1X6h
tstFqFix9OWh7UOdO/U=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a8kHOuTZginpjHtILcVNhLunRQwOe1ES2keYAvWwbqJ1/dP2HR58Y2qrfgkPfgJOhs1Sz8tBpdaz
3b3GZ3CGFdTkcQ6Np1zFLsz5LxqN9CH8/ss5eAKk+0AxCP/1J5ucoIHvImEp6FKZyoT4MujGdzeu
nXKRv9WouxkemNVX5yz0MldORdKM84AbVTMuB7I3XneDsIcti8nMI9aK3STpjhr4OIItlK0MMUQC
JsGn834Bn/QDrR8OKwbRI5OmH6SQkrQ4i+cj9syMNkoNHD1l6squ/XMbUPmco9memZGKhFlj2mF9
yRU/qY/Z3xn3q5sMyZmsaDVrjwUVDyh9RUxqZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 46416)
`protect data_block
GiO+1IkKzJyEJ+IJWiVmoV4gKBbfRRqYKYuHP41xaRjCAVFpBTNUhFCRuXFXZXA+c6jCPalEf6JW
0LLuYqG/4vkVNpkeINmqEzQwklQbqEwnY2ebzRws6X38Y/qmAHjiwVSCI/ugn+dps77j6iJ7CW5K
ByjN9SXqL+6uuCNYIwAwn8ZShi1dh0sH1xu4zOsBEziKWKLKmpJwoys44AA6PBeekJg1MlarIDN4
KcF9rQ1eYmOrnzvVOMmtxKygkQOhvP4QWvoE/AxchNk0zVbH+zfKVOAqg7ywppVupN9Eb4hbHxgq
44acIa4CXZudAokIwI+yOTQCsL8xAui2C/W53Hx4bHqFXiG2p2kUfBVuY3cUAssT4aAbj7AATZLE
ilbLSYF3INfdAjtUiUsuY1P+3rydlOh51h7bq7HVppvj56HNvpO+O5wGb67EAbmiFcvCskL6GErv
FrhtM/TGoRPSksRHFd1BUuNg4Chc8l1MHtQlbfb5Wp6hj3m/U6I7kp9TtqJG3P2zNXEaE0ce/YAs
Z2IiBaW+stkx8BHYsA6QE1V5e8yxwJDT4op2/WmMnzwHVYS1p3C+HTlpZW+KatQlb/A7AjOGGTkT
NcLxASPSoORnne2ZrGIIEl/X3h23X4WCqRCXK9CX/PE43/1YJnCBsrsDl2QG7TMtRF///86fduBN
pmaUctRXl4VSDgCnrtkhYHwND3eSUtT0j6/JQveVQrn36Za6vKIlbzB6p3xrstQW9jNphvul30Sd
gnQ9IDaLCB8lrIOVRP8gYHskjLDHMKsr8NImg5vqRir6st6lU4Yx8bTAyFyyLM/uWANP1MKu2NtK
WyPuPOjx+PXK0gsArwwyslytwXqkX7nL0GE3o8gfPP+86tB9lYkgy21eAFcIW2bKD5xk/7crk4rd
s3xE9N7cLq1/IPq8hlTSh9YSfVxesyXd17EykwyKZFziM6X7Q01UPA/knAS8WxnncgqbMcrzMHv3
5N0YjsAYYGr/WsL2vBC72HH9tus17ppuwCOPjuT34gxsuXsM3ufqnO+Bf1WACppKH10+wiib0xsI
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IBYPnrlZ5hRgXbQNzjBgwobjogIkfePQTS3BiwXVWbPxFZoP3jQJ3W5LpkQW/VttWBDijqQNKSr7
SEK+cIakI3U7Fu9KCOzRtlkNyXY2nfGJo0Hsm8R57F1krIvTEB1J4BjSqkF2HCYvmYkxNK4wsZUs
agj/jRftAa8ijOC2PI7GdE6uffZpnsNa+EZH538z/p7Jpsk0Jzx5ag02HiNUn3cFPEF3eCj+7Bgf
5Wb/cMXi2GVdzlXkChaG7VHQztrzy8DWVuwdcelouy8799uResge91xH8GZIKEMUgEcuEfwHob9t
0mA25Y5GqONljkU6Lo7IVUiTVnRZH6lQj2ih1oTdgXWafXmkCQYx5+fd7ugfHwcCFmSjLLFZvYmO
oYr2Wxb3Y3AWf6iJakx7syFIP+5xpR2DJQWMrpIc77eQBqo+vnlFQmv7wu1HpRjS1iut6Qb8FPCN
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stgX9EgEGQC5az8arfUIxkvlmH+4zFYSqpVJocgjQPZlxh2gEIkuxbTMPodNQFYWqpvtevLK5x0U
Ge/lK4klxgK8i+SFhwbi5be/iMUbFK/MNTbiM/hKFvXxdJXgZdwHGuSmBWtZdufqt5whWpufczmm
c2XaX2q+B9mSwaWECBdLzk3MA8nypHKiUqPgprH1Sc9GiqItRE7Mjue7wL2NVPOm6wvuOHm1BP9h
ZiL0MO7n+hPLdMVz+fDRYgcbI3LbW6aUwfqa+eb2X0WKgoo8l+Fn/h+kDmSwva0PiPVkldkOdNwA
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
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-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END design_1_axi_gpio_0_0;
ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_gpio_0_0_arch : ARCHITECTURE IS "design_1_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "design_1_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_0_0_arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
signal write : std_logic;
begin
write <= '1' when (gprf_i.wre_i = '1') and (unsigned(gprf_i.adr_w_i) /= 0) else '0';
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
end arch;
|
----------------------------------------------------------------------------------------------
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
signal write : std_logic;
begin
write <= '1' when (gprf_i.wre_i = '1') and (unsigned(gprf_i.adr_w_i) /= 0) else '0';
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
end arch;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;
library bitvis_vip_uart;
context bitvis_vip_uart.vvc_context;
library bitvis_vip_spec_cov;
use bitvis_vip_spec_cov.spec_cov_pkg.all;
use bitvis_vip_spec_cov.local_adaptations_pkg.all;
--hdlunit:tb
-- Test bench entity
entity uart_vvc_tb is
generic (GC_TESTCASE : natural := 0);
end entity;
-- Test bench architecture
architecture func of uart_vvc_tb is
-- Assuming that the testbench is run from the sim folder
constant C_REQ_LIST_FILE : string := "../demo/advanced_usage/req_list_advanced_demo.csv";
constant C_PARTIAL_COV_FILE : string := "../sim/partial_cov_advanced_demo_T" & to_string(GC_TESTCASE) & ".csv";
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
-- Clock and bit period settings
constant C_CLK_PERIOD : time := 10 ns;
constant C_BIT_PERIOD : time := 16 * C_CLK_PERIOD;
-- Predefined SBI addresses
constant C_ADDR_RX_DATA : unsigned(2 downto 0) := "000";
constant C_ADDR_RX_DATA_VALID : unsigned(2 downto 0) := "001";
constant C_ADDR_TX_DATA : unsigned(2 downto 0) := "010";
constant C_ADDR_TX_READY : unsigned(2 downto 0) := "011";
begin
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and Executors
-----------------------------------------------------------------------------
i_test_harness : entity work.uart_vvc_th;
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_FILE_OPEN_CLOSE); -- Enable the Spec Cov IDs
enable_log_msg(ID_FILE_PARSER); -- Enable the Spec Cov IDs
enable_log_msg(ID_SPEC_COV); -- Enable the Spec Cov IDs
disable_log_msg(SBI_VVCT, 1, ALL_MESSAGES);
enable_log_msg(SBI_VVCT, 1, ID_BFM);
disable_log_msg(UART_VVCT, 1, RX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, RX, ID_BFM);
disable_log_msg(UART_VVCT, 1, TX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, TX, ID_BFM);
log(ID_LOG_HDR, "Starting simulation of TB for UART using VVCs", C_SCOPE);
------------------------------------------------------------
log("Wait 10 clock period for reset to be turned off");
wait for (10 * C_CLK_PERIOD); -- for reset to be turned off
log(ID_LOG_HDR, "Configure UART VVC 1", C_SCOPE);
------------------------------------------------------------
shared_uart_vvc_config(RX,1).bfm_config.bit_time := C_BIT_PERIOD;
shared_uart_vvc_config(TX,1).bfm_config.bit_time := C_BIT_PERIOD;
-- If statement to determine which testcase to run
if (GC_TESTCASE = 0) then
log("Starting the requirement coverage process");
initialize_req_cov("T_UART_DEFAULTS", C_REQ_LIST_FILE, C_PARTIAL_COV_FILE);
log(ID_LOG_HDR, "T_UART_DEFAULTS - Check register defaults", C_SCOPE);
------------------------------------------------------------
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA, x"00", "RX_DATA default");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
-- Log the requirement FPGA_SPEC_1.a after test has completed
tick_off_req_cov("FPGA_SPEC_1.a");
sbi_check(SBI_VVCT, 1, C_ADDR_TX_READY, x"01", "TX_READY default");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
-- Log the requirement FPGA_SPEC_1.b after test has completed
tick_off_req_cov("FPGA_SPEC_1.b");
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA_VALID, x"00", "RX_DATA_VALID default");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
-- Log the requirement FPGA_SPEC_1.c after test has completed
tick_off_req_cov("FPGA_SPEC_1.c");
-- End the requirement coverage process
finalize_req_cov(VOID);
elsif (GC_TESTCASE = 1) then
log("Starting the requirement coverage process");
initialize_req_cov("T_UART_TX", C_REQ_LIST_FILE, C_PARTIAL_COV_FILE);
log(ID_LOG_HDR, "T_UART_TX - Check simple transmit", C_SCOPE);
------------------------------------------------------------
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"55", "TX_DATA");
uart_expect(UART_VVCT,1,RX, x"55", "Expecting data on UART RX");
await_completion(UART_VVCT,1,RX, 13 * C_BIT_PERIOD);
-- Log the requirement FPGA_SPEC_2 after test has completed
tick_off_req_cov("FPGA_SPEC_2");
wait for 200 ns; -- margin
-- End the requirement coverage process
finalize_req_cov(VOID);
elsif (GC_TESTCASE = 2) then
log("Starting the requirement coverage process");
initialize_req_cov("T_UART_RX", C_REQ_LIST_FILE, C_PARTIAL_COV_FILE);
log(ID_LOG_HDR, "T_UART_RX - Check simple receive", C_SCOPE);
------------------------------------------------------------
uart_transmit(UART_VVCT,1,TX, x"AA", "UART TX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"AA", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
-- Log the requirement FPGA_SPEC_3 after test has completed
tick_off_req_cov("FPGA_SPEC_3");
-- End the requirement coverage process
finalize_req_cov(VOID);
elsif (GC_TESTCASE = 3) then
log("Starting the requirement coverage process");
initialize_req_cov("T_UART_SIMULTANEOUS", C_REQ_LIST_FILE, C_PARTIAL_COV_FILE);
log(ID_LOG_HDR, "T_UART_SIMULTANEOUS - Check single simultaneous transmit and receive", C_SCOPE);
------------------------------------------------------------
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"B4", "TX_DATA");
uart_transmit(UART_VVCT,1,TX, x"87", "UART TX");
uart_expect(UART_VVCT,1,RX, x"B4", "Expecting data on UART RX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"87", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
-- Log the requirement FPGA_SPEC_4 after test has completed
tick_off_req_cov("FPGA_SPEC_4");
-- End the requirement coverage process
finalize_req_cov(VOID);
end if;
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func; |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_elem_behav_minimal of tb_elem is
for behav
for dut_b : chip
use configuration work.chip_minimal_c0;
end for;
for card_b : card
use configuration work.card_behav_c0;
end for;
end for;
end tb_elem_behav_minimal;
|
-- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test file_open() function.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity vhdl_file_open is
port(active : in std_logic;
ok : out std_logic);
end vhdl_file_open;
architecture test of vhdl_file_open is
begin
process(active)
file ok_file, bad_file : text;
variable ok_status, bad_status : FILE_OPEN_STATUS;
begin
if rising_edge(active) then
file_open(ok_status, ok_file, "ivltests/vhdl_file_open.vhd", read_mode);
file_open(bad_status, bad_file, "not_existing_file", read_mode);
if ok_status = OPEN_OK and bad_status = NAME_ERROR then
ok := '1';
else
ok := '0';
end if;
file_close(ok_file);
end if;
end process;
end test;
|
-- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test file_open() function.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity vhdl_file_open is
port(active : in std_logic;
ok : out std_logic);
end vhdl_file_open;
architecture test of vhdl_file_open is
begin
process(active)
file ok_file, bad_file : text;
variable ok_status, bad_status : FILE_OPEN_STATUS;
begin
if rising_edge(active) then
file_open(ok_status, ok_file, "ivltests/vhdl_file_open.vhd", read_mode);
file_open(bad_status, bad_file, "not_existing_file", read_mode);
if ok_status = OPEN_OK and bad_status = NAME_ERROR then
ok := '1';
else
ok := '0';
end if;
file_close(ok_file);
end if;
end process;
end test;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sat Mar 19 19:16:24 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/repo/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/dcfifo_32in_32out_8kb_cnt_stub.vhdl
-- Design : dcfifo_32in_32out_8kb_cnt
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcfifo_32in_32out_8kb_cnt is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end dcfifo_32in_32out_8kb_cnt;
architecture stub of dcfifo_32in_32out_8kb_cnt is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sat Mar 19 19:16:24 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/SKL/Desktop/ECE532/repo/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/dcfifo_32in_32out_8kb_cnt_stub.vhdl
-- Design : dcfifo_32in_32out_8kb_cnt
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dcfifo_32in_32out_8kb_cnt is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end dcfifo_32in_32out_8kb_cnt;
architecture stub of dcfifo_32in_32out_8kb_cnt is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
--
-- Definition of a single port ROM for KCPSM3 program defined by picocode.psm
--
-- Generated by KCPSM3 Assembler 16Aug2015-19:51:29.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity picocode is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end picocode;
--
architecture low_level_definition of picocode is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "001AC0000010001AC0000008001AC0000004001AC0000002001AC0000001C000";
attribute INIT_01 of ram_1024_x_18 : label is "8001000081010100820102004001001AC0000080001AC0000040001AC0000020";
attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000008001A000541B425E541D4100541F";
attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "4026000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000003B77444F8E38E38E38E3";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "C000000000000000000000000000000000000000000000000000000000000000";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"001AC0000010001AC0000008001AC0000004001AC0000002001AC0000001C000",
INIT_01 => X"8001000081010100820102004001001AC0000080001AC0000040001AC0000020",
INIT_02 => X"0000000000000000000000000000000000008001A000541B425E541D4100541F",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"4026000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"000000000000000000000000000000000000000000003B77444F8E38E38E38E3",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE picocode.vhd
--
------------------------------------------------------------------------------------
|
--! @file fir_ea.vhd
--! @brief Pipelined FIR filter
--! @author Scott Teal ([email protected])
--! @date 2013-12-16
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use work.fixed_pkg.all;
use work.util_pkg.all;
--! Pipelined FIR filter. Can be configured to be a symmetric filter, and takes
--! in coefficients as it runs. The upper and lower bits of the fixed-point
--! accumulators must be set by the user. The recommended values of these are
--! vendor- and application-dependent, and thus cannot be calculated within this
--! entity.
--!
--! If using the symmetric option, make sure to correctly set whether there is
--! an even or odd **total** number of coefficients. The entity will not function as
--! expected otherwise.
--!
--! Example: 64-tap filter can be described with 32 coefficients if it is
--! symmetric. Set EVEN to true so that the entity knows it was originally
--! a 64-tap filter.
--!
--! Example: 63-tap filter can also be described with 32 coefficients if it is
--! symmetric. Set EVEN to false so that the entity knows it was originally
--! a 63-tap filter, and not a 64-tap.
--!
entity fir is
generic (
SYMMETRIC : boolean := false; --! Symmetric filter
EVEN : boolean := false; --! Even or odd number of total coefficients
UPPER_BIT : integer; --! Upper bit of accumulator
LOWER_BIT : integer --! Lower bit of accumulator
);
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset line
coeff : in sfixed_vector; --! Coefficient vector
din : in sfixed; --! Data into FIR filter
dout : out sfixed --! Filtered data
);
end entity fir;
architecture rtl of fir is
signal in_line : sfixed_vector(coeff'range)(din'range);
signal delay0 : sfixed_vector(coeff'range)(din'range);
signal coeff_reg : sfixed_vector(coeff'range)(coeff'element'range);
signal mul_reg : sfixed_vector(coeff'range)(UPPER_BIT downto LOWER_BIT);
signal add_reg : sfixed_vector(coeff'range)(UPPER_BIT downto LOWER_BIT);
signal symmetric_delay : sfixed_vector(0 to (coeff'high * 2 + 1))(din'range);
signal symmetric_input : sfixed_vector(coeff'range)(din'range);
signal preadd_reg : sfixed_vector(coeff'range)(
sfixed_high(din'high, din'low, '+', din'high, din'low) downto
sfixed_low(din'high, din'low, '+', din'high, din'low));
begin
pipeline : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
-- Zero everything out
in_line <= (others => to_sfixed(0,
in_line'element'high, in_line'element'low));
delay0 <= (others => to_sfixed(0,
delay0'element'high, delay0'element'low));
coeff_reg <= (others => to_sfixed(0,
coeff_reg'element'high, coeff_reg'element'low));
mul_reg <= (others => to_sfixed(0,
mul_reg'element'high, mul_reg'element'low));
add_reg <= (others => to_sfixed(0,
add_reg'element'high, add_reg'element'low));
else
for i in coeff'range loop
-- Input data pipeline
if i = 0 then
in_line(i) <= din; -- Feed data in to delay line
else
in_line(i) <= delay0(i-1); -- Build up delay line registers
end if;
delay0(i) <= in_line(i); -- Delay input by 1
coeff_reg(i) <= coeff(i); -- Register all coefficients
-- Multiplier & preadder are different depending on whether the filter
-- is symmetric or not
if SYMMETRIC then
if ((not EVEN) and (i = coeff'high)) then
preadd_reg(i) <= resize(delay0(i),
preadd_reg'element'high,
preadd_reg'element'low);
else
preadd_reg(i) <= delay0(i) + symmetric_input(i);
end if;
-- Multiply data by coefficients
mul_reg(i) <= resize(preadd_reg(i) * coeff_reg(i),
UPPER_BIT, LOWER_BIT);
else
-- Multiply data by coefficients
mul_reg(i) <= resize(delay0(i) * coeff_reg(i),
UPPER_BIT, LOWER_BIT);
end if;
-- Adders
if i = 0 then
-- First adder has no previous adder output
add_reg(i) <= resize(mul_reg(i),
UPPER_BIT, LOWER_BIT);
else
-- Build up adder chain
add_reg(i) <= resize(mul_reg(i) + add_reg(i-1),
UPPER_BIT, LOWER_BIT);
end if;
end loop;
end if;
end if;
end process;
symmetric_delay_pipeline_gen : if SYMMETRIC generate
symmetric_delay_pipeline : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
symmetric_delay <= (others => to_sfixed(0,
symmetric_delay'element'high,
symmetric_delay'element'low));
symmetric_input <= (others => to_sfixed(0,
symmetric_input'element'high,
symmetric_input'element'low));
else
for i in symmetric_delay'range loop
if i = 0 then
symmetric_delay(i) <= din;
else
symmetric_delay(i) <= symmetric_delay(i - 1);
end if;
end loop;
for i in symmetric_input'range loop
if EVEN then
symmetric_input(i) <= symmetric_delay(symmetric_delay'high);
else
symmetric_input(i) <= symmetric_delay(symmetric_delay'high-1);
end if;
end loop;
end if; -- rst
end if; -- clk
end process; -- pipeline
end generate; -- generate
--! Final output is output from highest adder
dout <= add_reg(add_reg'high(1))(dout'high downto dout'low);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of sample_buffer_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of sample_buffer_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity fractional_clock_divider_tb is
end fractional_clock_divider_tb;
architecture tb of fractional_clock_divider_tb is
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : fractional_clock_divider
generic map (
MUL => 41,
DIV => 31250)
port map(
clk_out_p => output,
clk => clk);
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_382 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_382;
architecture augh of add_382 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_382 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_382;
architecture augh of add_382 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date: 06/29/2017 07:16:10 PM
-- Design Name:
-- Module Name: BRAM
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- This is a single port BRAM
entity BRAM_SP is
generic ( WIDTH : integer := 32;
DEPTH : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(DEPTH_LOG-1 downto 0);
di : in std_logic_vector(WIDTH-1 downto 0);
do : out std_logic_vector(WIDTH-1 downto 0)
);
end BRAM_SP;
-- This is a write first memory which should be inferred as a BRAM
architecture syn of BRAM_SP is
type ram_type is array(DEPTH-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal data: ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
data(to_integer(unsigned(addr))) <= di;
do <= di;
else
do <= data(to_integer(unsigned(addr)));
end if;
end if;
end if;
end process;
end syn;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- This is a dual port BRAM
entity BRAM_DP is
generic ( WIDTH : integer := 32;
DEPTH : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
awe : in std_logic;
aen : in std_logic;
aaddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
adi : in std_logic_vector(WIDTH-1 downto 0);
ado : out std_logic_vector(WIDTH-1 downto 0);
bwe : in std_logic;
ben : in std_logic;
baddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
bdi : in std_logic_vector(WIDTH-1 downto 0);
bdo : out std_logic_vector(WIDTH-1 downto 0)
);
end BRAM_DP;
architecture syn of BRAM_DP is
type ram_type is array(DEPTH-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal RAM: ram_type;
signal read_addra, read_addrb : std_logic_vector(DEPTH_LOG-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (aen = '1') then
if (awe = '1') then
RAM(to_integer(unsigned(aaddr))) <= adi;
end if;
read_addra <= aaddr;
end if;
if (ben = '1') then
if (bwe = '1') then
RAM(to_integer(unsigned(baddr))) <= bdi;
end if;
read_addrb <= baddr;
end if;
end if;
end process;
ado <= RAM(to_integer(unsigned(read_addra)));
bdo <= RAM(to_integer(unsigned(read_addrb)));
end architecture syn;
-- architecture syn of BRAM_DP is
-- type ram_type is array(DEPTH-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
-- signal data: ram_type;
-- begin
-- portA : process (clk)
-- begin
-- if clk'event and clk = '1' then
-- if aen = '1' then
-- if awe = '1' then
-- data(to_integer(unsigned(aaddr))) <= adi;
-- ado <= adi;
-- else
-- ado <= data(to_integer(unsigned(aaddr)));
-- end if;
-- end if;
-- end if;
-- end process portA;
-- portB : process (clk)
-- begin
-- if clk'event and clk = '1' then
-- if ben = '1' then
-- if bwe = '1' then
-- data(to_integer(unsigned(baddr))) <= bdi;
-- bdo <= bdi;
-- else
-- bdo <= data(to_integer(unsigned(baddr)));
-- end if;
-- end if;
-- end if;
-- end process portB;
-- end architecture syn;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1978.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01978ent IS
END c07s02b02x00p01n02i01978ent;
ARCHITECTURE c07s02b02x00p01n02i01978arch OF c07s02b02x00p01n02i01978ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s02b02x00p01n02i01978"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s02b02x00p01n02i01978"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s02b02x00p01n02i01978arch;
-- CONFIGURATION c07s02b02x00p01n02i01978cfg OF c07s02b02x00p01n02i01978ent IS
-- FOR c07s02b02x00p01n02i01978arch
-- END FOR;
-- END c07s02b02x00p01n02i01978cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1978.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01978ent IS
END c07s02b02x00p01n02i01978ent;
ARCHITECTURE c07s02b02x00p01n02i01978arch OF c07s02b02x00p01n02i01978ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s02b02x00p01n02i01978"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s02b02x00p01n02i01978"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s02b02x00p01n02i01978arch;
-- CONFIGURATION c07s02b02x00p01n02i01978cfg OF c07s02b02x00p01n02i01978ent IS
-- FOR c07s02b02x00p01n02i01978arch
-- END FOR;
-- END c07s02b02x00p01n02i01978cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1978.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n02i01978ent IS
END c07s02b02x00p01n02i01978ent;
ARCHITECTURE c07s02b02x00p01n02i01978arch OF c07s02b02x00p01n02i01978ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s02b02x00p01n02i01978"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s02b02x00p01n02i01978"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s02b02x00p01n02i01978arch;
-- CONFIGURATION c07s02b02x00p01n02i01978cfg OF c07s02b02x00p01n02i01978ent IS
-- FOR c07s02b02x00p01n02i01978arch
-- END FOR;
-- END c07s02b02x00p01n02i01978cfg;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 1K program for KCPSM6 in a 7-Series device using a
RAMB18E1 primitive.
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 1K program for KCPSM6 in a 7-Series device using a
-- RAMB18E1 primitive.
--
-- Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code
-- expansion with minimum changes being required to the hardware description.
-- Only the lower 10-bits of the address are actually used for the 1K address range
-- 000 to 3FF hex.
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_7S_1K_14March13.vhd
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(13 downto 0);
signal data_in_a : std_logic_vector(17 downto 0);
signal data_out_a : std_logic_vector(17 downto 0);
signal address_b : std_logic_vector(13 downto 0);
signal data_in_b : std_logic_vector(17 downto 0);
signal data_out_b : std_logic_vector(17 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(3 downto 0);
--
begin
--
address_a <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a <= "0000000000000000" & address(11 downto 10);
--
address_b <= "11111111111111";
data_in_b <= data_out_b(17 downto 0);
enable_b <= '0';
we_b <= "0000";
clk_b <= '0';
--
--
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:06:03)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_wsga_entity;
ARCHITECTURE hal_wsga_description OF hal_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 * register2;
register2 := input3 * 3;
register3 := input4 + 4;
WHEN "00000011" =>
register2 := register2 * 6;
register1 := register1 - 8;
register4 := input5 * 9;
IF (register3 < 10) THEN
output1 <= register3;
ELSE
output1 <= "01010";
END IF;
WHEN "00000100" =>
output2 <= register4 + 11;
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_wsga_description; |
package CORE is
type STATUS_TYPE is record
error_count : integer;
end record;
end CORE;
library WORK;
use WORK.CORE.STATUS_TYPE;
entity TEST_1 is
generic (
EXP_STATUS : STATUS_TYPE
);
end TEST_1;
architecture MODEL of TEST_1 is
begin
end MODEL;
library WORK;
use WORK.CORE.STATUS_TYPE;
entity TEST_1_1 is
end TEST_1_1;
architecture MODEL of TEST_1_1 is
constant EXP_STATUS : STATUS_TYPE := (error_count => 0);
component TEST_1
generic (
EXP_STATUS : STATUS_TYPE
);
end component;
begin
U: TEST_1 generic map(EXP_STATUS);
end MODEL;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_aa
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:21 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-rtl-conf-c.vhd,v 1.1 2007/03/05 10:01:23 wig Exp $
-- $Date: 2007/03/05 10:01:23 $
-- $Log: ent_aa-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 10:01:23 wig
-- Create all lowercase filenames since 2007-03-03
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_aa_RTL_CONF / ent_aa
--
configuration ent_aa_RTL_CONF of ent_aa is
for rtl
-- Generated Configuration
end for;
end ent_aa_RTL_CONF;
--
-- End of Generated Configuration ent_aa_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: avnet:zedboard:zed_hdmi_out:2.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.zed_hdmi_out;
ENTITY tutorial_zed_hdmi_out_0_0 IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END tutorial_zed_hdmi_out_0_0;
ARCHITECTURE tutorial_zed_hdmi_out_0_0_arch OF tutorial_zed_hdmi_out_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_zed_hdmi_out_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi_out IS
GENERIC (
C_DATA_WIDTH : INTEGER; -- Video Data Width
C_FAMILY : STRING
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END COMPONENT zed_hdmi_out;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_zed_hdmi_out_0_0_arch: ARCHITECTURE IS "zed_hdmi_out,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_zed_hdmi_out_0_0_arch : ARCHITECTURE IS "tutorial_zed_hdmi_out_0_0,zed_hdmi_out,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF video_vsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_hsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_de: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF video_data: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_spdif: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO SPDIF";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_video: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_vsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_hsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_de: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DE";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_clk: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO CLK";
BEGIN
U0 : zed_hdmi_out
GENERIC MAP (
C_DATA_WIDTH => 16,
C_FAMILY => "zynq"
)
PORT MAP (
clk => clk,
reset => reset,
audio_spdif => audio_spdif,
video_vsync => video_vsync,
video_hsync => video_hsync,
video_de => video_de,
video_data => video_data,
io_hdmio_spdif => io_hdmio_spdif,
io_hdmio_video => io_hdmio_video,
io_hdmio_vsync => io_hdmio_vsync,
io_hdmio_hsync => io_hdmio_hsync,
io_hdmio_de => io_hdmio_de,
io_hdmio_clk => io_hdmio_clk
);
END tutorial_zed_hdmi_out_0_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity MRAM is
port (
RW: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DIN: in std_logic_vector (7 downto 0);
DOUT: out std_logic_vector (7 downto 0)
);
end MRAM;
architecture Beh_Max of MRAM is
subtype byte is std_logic_vector(7 downto 0);
type tRAM is array (0 to 63) of byte;
signal RAM : tRAM :=(
"00000101", -- 5 | 000000 | array length
"00000011", -- 3 | 000001 | a[0]
"00000001", -- 1 | 000010 | a[1]
"00000010", -- 2 | 000011 | a[2]
"00000100", -- 4 | 000100 | a[3]
"00000101", -- 5 | 000101 | a[4]
"00000000", -- 0 | 000110 | result
"00000001", -- 1 | 000111 | 1 for add and sub
others => "00000000"
);
signal data_in: byte;
signal data_out: byte;
Begin
data_in <= Din;
WRITE: process (RW, ADR, data_in)
begin
if (RW = '0') then
RAM(conv_integer(adr)) <= data_in;
end if;
end process;
data_out <= RAM (conv_integer(adr));
ZBUFS: process (RW, data_out)
begin
if (RW = '1') then
DOUT <= data_out;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh_Max;
architecture Beh_Zer of MRAM is
subtype byte is std_logic_vector(7 downto 0);
type tRAM is array (0 to 63) of byte;
signal RAM : tRAM :=(
"00000101", -- 5 | 000000 | array length
"00000000", -- 0 | 000001 | a[0]
"00000001", -- 1 | 000010 | a[1]
"00000000", -- 0 | 000011 | a[2]
"00000100", -- 4 | 000100 | a[3]
"00000000", -- 5 | 000101 | a[4]
"00000000", -- 0 | 000110 | result
"00000001", -- 1 | 000111 | 1 for add and sub
others => "00000000"
);
signal data_in: byte;
signal data_out: byte;
Begin
data_in <= Din;
WRITE: process (RW, ADR, data_in)
begin
if (RW = '0') then
RAM(conv_integer(adr)) <= data_in;
end if;
end process;
data_out <= RAM (conv_integer(adr));
ZBUFS: process (RW, data_out)
begin
if (RW = '1') then
DOUT <= data_out;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh_Zer; |
-------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(2 downto 0);
signal AsconInput : std_logic_vector(63 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput(63 downto 0);
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "1000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:03:31 07/13/2015
-- Design Name:
-- Module Name: fpgamemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fpgamemory is
Port ( k0 : in STD_LOGIC_VECTOR (7 downto 0);
k1 : in STD_LOGIC_VECTOR (7 downto 0);
k2 : in STD_LOGIC_VECTOR (7 downto 0);
k3 : in STD_LOGIC_VECTOR (7 downto 0);
k4 : in STD_LOGIC_VECTOR (7 downto 0);
addr : inout STD_LOGIC_VECTOR (15 downto 0);
datain : inout STD_LOGIC_VECTOR (15 downto 0);
cs : out STD_LOGIC;
wr : out STD_LOGIC;
rd : out STD_LOGIC;
bh : out STD_LOGIC;
bl : out STD_LOGIC;
s0 : out std_logic_vector(7 downto 0);
s1 : out std_logic_vector(7 downto 0));
end fpgamemory;
architecture Behavioral of fpgamemory is
begin
addr<=k3&k2;
cs<=k4(1);
wr<=k4(4);
rd<=k4(0);
bh<=k4(2);
bl<=k4(3);
write_process:process(k0,k1,k2,k3,k4)
begin
if k4(1) = '0' and k4(0) = '1' and k4(4)='0' and k4(3) = '0' and k4(2) = '0' then
datain(7 downto 0) <=k0;
datain(15 downto 8)<=k1;
elsif k4(1) = '0' and k4(0) = '1' and k4(3) = '0' and k4(4)='0' and k4(2) = '1' then
datain(7 downto 0)<=k0;
datain(15 downto 8)<= "ZZZZZZZZ";
elsif k4(1) = '0' and k4(0) = '1' and k4(3) = '1' and k4(4)='0' and k4(2) = '0' then
datain(7 downto 0)<="ZZZZZZZZ";
datain(15 downto 8)<=k1;
else
datain<="ZZZZZZZZZZZZZZZZ";
end if;
end process write_process;
read_process:process(k0,k1,k2,k3,k4)
begin
if k4(1) = '0' and k4(0) = '0' and k4(4)='1' and k4(3) = '0' and k4(2) = '0' then
s0 <= datain(7 downto 0);
s1 <= datain(15 downto 8);
elsif k4(1) = '0' and k4(0) = '0' and k4(3) = '0' and k4(4)='1' and k4(2) = '1' then
s0 <= datain(7 downto 0);
s1 <= "ZZZZZZZZ";
elsif k4(1) = '0' and k4(0) = '0' and k4(3) = '1' and k4(4)='1' and k4(2) = '0' then
s0 <= "ZZZZZZZZ";
s1 <= datain(15 downto 8);
else
s0<="ZZZZZZZZ";
s1<="ZZZZZZZZ";
end if;
end process read_process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
u0 : virtex_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage) port map (padp(i), padn(i), o(i));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
u0 : virtex_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage) port map (padp(i), padn(i), o(i));
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity sdb_rom is
generic(
g_layout : t_sdb_record_array;
g_bus_end : unsigned(63 downto 0));
port(
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end sdb_rom;
architecture rtl of sdb_rom is
alias c_layout : t_sdb_record_array(g_layout'length downto 1) is g_layout;
-- The ROM must describe all slaves, the crossbar itself and the optional information records
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_words : natural := c_sdb_device_length / c_wishbone_data_width;
constant c_rom_words : natural := c_rom_entries * c_sdb_words;
constant c_rom_depth : natural := f_ceil_log2(c_rom_words);
constant c_rom_lowbits : natural := f_ceil_log2(c_wishbone_data_width / 8);
type t_rom is array(c_rom_words-1 downto 0) of t_wishbone_data;
function f_build_rom
return t_rom
is
variable res : t_rom := (others => (others => '0'));
variable sdb_device : std_logic_vector(c_sdb_device_length-1 downto 0) := (others => '0');
variable sdb_component : t_sdb_component;
begin
sdb_device(511 downto 480) := x"5344422D" ; -- sdb_magic
sdb_device(479 downto 464) := std_logic_vector(to_unsigned(c_used_entries, 16)); -- sdb_records
sdb_device(463 downto 456) := x"01"; -- sdb_version
sdb_device(455 downto 448) := x"00"; -- sdb_bus_type = sdb_wishbone
sdb_device( 7 downto 0) := x"00"; -- record_type = sdb_interconnect
sdb_component.addr_first := (others => '0');
sdb_component.addr_last := std_logic_vector(g_bus_end);
sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
sdb_component.product.device_id := x"e6a542c9";
sdb_component.product.version := x"00000002";
sdb_component.product.date := x"20120511";
sdb_component.product.name := "WB4-Crossbar-GSI ";
sdb_device(447 downto 8) := f_sdb_embed_component(sdb_component, (others => '0'));
for i in 0 to c_sdb_words-1 loop
res(c_sdb_words-1-i) :=
sdb_device((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
end loop;
for slave in 1 to c_used_entries-1 loop
sdb_device(511 downto 0) := c_layout(slave);
for i in 0 to c_sdb_words-1 loop
res((slave+1)*c_sdb_words-1-i) :=
sdb_device((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
end loop;
end loop;
return res;
end f_build_rom;
signal rom : t_rom := f_build_rom;
signal adr_reg : unsigned(c_rom_depth-1 downto 0);
begin
-- Simple ROM; ignore we/sel/dat
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.stall <= '0';
slave_o.int <= '0'; -- Tom sucks! This should not be here.
slave_o.dat <= rom(to_integer(adr_reg));
slave_clk : process(clk_sys_i)
begin
if (rising_edge(clk_sys_i)) then
adr_reg <= unsigned(slave_i.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
slave_o.ack <= slave_i.cyc and slave_i.stb;
end if;
end process;
end rtl;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_uart;
use bitvis_vip_uart.uart_bfm_pkg.all;
use bitvis_vip_uart.vvc_cmd_pkg.all;
use bitvis_vip_uart.vvc_methods_pkg.all;
use bitvis_vip_uart.td_vvc_framework_common_methods_pkg.all;
end context; |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity @entity.txt@ is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity @entity.txt@;
architecture Xilinx of @entity.txt@ is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
@rom.dat@
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: @entity.txt@
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eac_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eac_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:58 wig Exp $
-- $Date: 2004/04/06 10:49:58 $
-- $Log: inst_eac_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:58 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eac_e
--
architecture rtl of inst_eac_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2lib
-- Description: Cypress ez-usb fx2 support
--
-- Dependencies: -
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
-- 2011-07-07 389 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package fx2lib is
constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
type fx2ctl_moni_type is record -- fx2ctl monitor port
fifo_ep4 : slbit; -- fifo 1 (ep4) active;
fifo_ep6 : slbit; -- fifo 2 (ep6) active;
fifo_ep8 : slbit; -- fifo 3 (ep8) active;
flag_ep4_empty : slbit; -- ep4 empty flag (latched);
flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
flag_ep6_full : slbit; -- ep6 full flag (latched);
flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
flag_ep8_full : slbit; -- ep8 full flag (latched);
flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
slrd : slbit; -- read strobe
slwr : slbit; -- write strobe
pktend : slbit; -- pktend strobe
end record fx2ctl_moni_type;
constant fx2ctl_moni_init : fx2ctl_moni_type := (
'0','0','0', -- fifo_ep[468]
'0','0', -- flag_ep4_(empty|almost)
'0','0', -- flag_ep6_(full|almost)
'0','0', -- flag_ep8_(full|almost)
'0','0','0' -- slrd, slwr, pktend
);
-- -------------------------------------
component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package fx2lib;
|
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