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--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Instruction_Memory_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF Instruction_Memory_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.Instruction_Memory_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_12_3_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END RAT_slice_12_3_0;
ARCHITECTURE RAT_slice_12_3_0_arch OF RAT_slice_12_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_12_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 17,
DIN_TO => 13
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_12_3_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_12_3_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END RAT_slice_12_3_0;
ARCHITECTURE RAT_slice_12_3_0_arch OF RAT_slice_12_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_12_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 17,
DIN_TO => 13
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_12_3_0_arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity pads is
generic (
padtech : integer := 0;
padlevel : integer := 0;
padvoltage : integer := 0;
padfilter : integer := 0;
padstrength : integer := 0;
padslew : integer := 0;
padclkarch : integer := 0;
padhf : integer := 0;
spw_input_type : integer := 0;
jtag_padfilter : integer := 0;
testen_padfilter : integer := 0;
resetn_padfilter : integer := 0;
clk_padfilter : integer := 0;
spw_padstrength : integer := 0;
jtag_padstrength : integer := 0;
uart_padstrength : integer := 0;
dsu_padstrength : integer := 0;
oepol : integer := 0
);
port (
----------------------------------------------------------------------------
--to chip boundary
----------------------------------------------------------------------------
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : inout std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
---------------------------------------------------------------------------
--to core
---------------------------------------------------------------------------
lresetn : out std_ulogic;
lclksel : out std_logic_vector (1 downto 0);
lclk : out std_ulogic;
llock : in std_ulogic;
lerrorn : in std_ulogic;
laddress : in std_logic_vector(27 downto 0);
ldatain : out std_logic_vector(31 downto 0);
ldataout : in std_logic_vector(31 downto 0);
ldataen : in std_logic_vector(31 downto 0);
lcbin : out std_logic_vector(7 downto 0);
lcbout : in std_logic_vector(7 downto 0);
lcben : in std_logic_vector(7 downto 0);
lsdclk : in std_ulogic;
lsdcsn : in std_logic_vector (1 downto 0);
lsdwen : in std_ulogic;
lsdrasn : in std_ulogic;
lsdcasn : in std_ulogic;
lsddqm : in std_logic_vector (3 downto 0);
ldsutx : in std_ulogic;
ldsurx : out std_ulogic;
ldsuen : out std_ulogic;
ldsubre : out std_ulogic;
ldsuact : in std_ulogic;
ltxd1 : in std_ulogic;
lrxd1 : out std_ulogic;
ltxd2 : in std_ulogic;
lrxd2 : out std_ulogic;
lramsn : in std_logic_vector (4 downto 0);
lramoen : in std_logic_vector (4 downto 0);
lrwen : in std_logic_vector (3 downto 0);
loen : in std_ulogic;
lwriten : in std_ulogic;
lread : in std_ulogic;
liosn : in std_ulogic;
lromsn : in std_logic_vector (1 downto 0);
lbrdyn : out std_ulogic;
lbexcn : out std_ulogic;
lwdogn : in std_ulogic;
lgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
li2c_sclout : in std_ulogic;
li2c_sclen : in std_ulogic;
li2c_sclin : out std_ulogic;
li2c_sdaout : in std_ulogic;
li2c_sdaen : in std_ulogic;
li2c_sdain : out std_ulogic;
lspi_miso : out std_ulogic;
lspi_mosi : in std_ulogic;
lspi_sck : in std_ulogic;
lspi_slvsel : in std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
lprom32 : out std_ulogic;
lspw_clksel : out std_logic_vector (1 downto 0);
lspw_clk : out std_ulogic;
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
lgtx_clk : out std_ulogic;
lerx_clk : out std_ulogic;
lerxd : out std_logic_vector(7 downto 0);
lerx_dv : out std_ulogic;
letx_clk : out std_ulogic;
letxd : in std_logic_vector(7 downto 0);
letx_en : in std_ulogic;
letx_er : in std_ulogic;
lerx_er : out std_ulogic;
lerx_col : out std_ulogic;
lerx_crs : out std_ulogic;
lemdint : out std_ulogic;
lemdioin : out std_logic;
lemdioout : in std_logic;
lemdioen : in std_logic;
lemdc : in std_ulogic;
ltesten : out std_ulogic;
ltrst : out std_ulogic;
ltck : out std_ulogic;
ltms : out std_ulogic;
ltdi : out std_ulogic;
ltdo : in std_ulogic;
ltdoen : in std_ulogic
);
end;
architecture rtl of pads is
signal vcc,gnd : std_logic;
begin
vcc <= '1';
gnd <= '0';
------------------------------------------------------------------------------
-- Clocking and clock pads
------------------------------------------------------------------------------
reset_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => resetn_padfilter,
strength => padstrength)
port map (
pad => resetn,
o => lresetn);
clk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => clk,
o => lclk);
clksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => clksel,
o => lclksel);
spwclk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => spw_clk,
o => lspw_clk);
spwclksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => spw_clksel,
o => lspw_clksel);
------------------------------------------------------------------------------
-- Test / Misc pads
------------------------------------------------------------------------------
wdogn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => wdogn,
en => gnd,
i => lwdogn);
testen_pad : inpad
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => testen_padfilter,
strength => padstrength)
port map(
pad => testen,
o => ltesten);
lockpad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => lock,
i => llock);
errorn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => errorn,
en => gnd,
i => lerrorn);
------------------------------------------------------------------------------
-- JTAG pads
------------------------------------------------------------------------------
trst_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => trst,
o => ltrst);
tck_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tck,
o => ltck);
tms_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tms,
o => ltms);
tdi_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tdi,
o => ltdi);
tdo_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => jtag_padstrength)
port map (
pad => tdo,
i => ltdo);
------------------------------------------------------------------------------
-- DSU pads
------------------------------------------------------------------------------
dsuen_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsuen,
o => ldsuen);
dsubre_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsubre,
o => ldsubre);
dsuact_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsuact,
i => ldsuact);
dsurx_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsurx,
o => ldsurx);
dsutx_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsutx,
i => ldsutx);
------------------------------------------------------------------------------
-- UART pads
------------------------------------------------------------------------------
rxd1_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd1,
o => lrxd1);
txd1_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd1,
i => ltxd1);
rxd2_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd2,
o => lrxd2);
txd2_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd2,
i => ltxd2);
------------------------------------------------------------------------------
-- SPI pads
------------------------------------------------------------------------------
miso_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map(
pad => spi_miso,
o => lspi_miso);
mosi_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_mosi,
i => lspi_mosi);
sck_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_sck,
i => lspi_sck);
slvsel_pad : outpadv
generic map (
width => CFG_SPICTRL_SLVS,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => spi_slvsel,
i => lspi_slvsel);
------------------------------------------------------------------------------
-- I2C pads
------------------------------------------------------------------------------
scl_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_scl,
i => li2c_sclout,
en => li2c_sclen,
o => li2c_sclin);
sda_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_sda,
i => li2c_sdaout,
en => li2c_sdaen,
o => li2c_sdain);
------------------------------------------------------------------------------
-- Memory Interface pads
------------------------------------------------------------------------------
addr_pad : outpadv generic map (width => 28, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (address, laddress);
data_pad : iopadvv generic map (width => 32, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => data, i => ldataout, en => ldataen, o => ldatain);
rams_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramsn, lramsn);
roms_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (romsn, lromsn);
ramoen_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramoen, lramoen);
rwen_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (rwen, lrwen);
oen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (oen, loen);
wri_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (writen, lwriten);
read_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (read, lread);
iosn_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (iosn, liosn);
cb_pad : iopadvv generic map (width => 8, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => cb, i => lcbout, en => lcben, o => lcbin);
sdpads : if CFG_MCTRL_SDEN = 1 generate
sdclk_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdclk, lsdclk);
sdwen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdwen, lsdwen);
sdras_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdrasn, lsdrasn);
sdcas_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcasn, lsdcasn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sddqm, lsddqm);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcsn, lsdcsn);
end generate;
brdyn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => brdyn,
o => lbrdyn);
bexcn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => bexcn,
o => lbexcn);
prom32_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => prom32,
o => lprom32);
------------------------------------------------------------------------------
-- GPIO pads
------------------------------------------------------------------------------
gpio_pads : iopadvv
generic map (
width => CFG_GRGPIO_WIDTH,
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => gpio,
i => lgpioout,
en => lgpioen,
o => lgpioin);
------------------------------------------------------------------------------
-- SpW pads
------------------------------------------------------------------------------
spwpads0 : if CFG_SPW_EN > 0 generate
spwlvttl_pads : entity work.spw_lvttl_pads
generic map(
padtech => padtech,
strength => spw_padstrength,
input_type => spw_input_type,
voltage => padvoltage,
level => padlevel)
port map(
spw_rxd => spw_rxd,
spw_rxs => spw_rxs,
spw_txd => spw_txd,
spw_txs => spw_txs,
lspw_rxd => lspw_rxd,
lspw_rxs => lspw_rxs,
lspw_txd => lspw_txd,
lspw_txs => lspw_txs);
end generate;
------------------------------------------------------------------------------
-- ETHERNET
------------------------------------------------------------------------------
greth1g: if CFG_GRETH1G = 1 generate
gtx_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => gtx_clk,
o => lgtx_clk);
end generate;
nogreth1g: if CFG_GRETH1G = 0 generate
lgtx_clk <= '0';
end generate;
ethpads : if (CFG_GRETH = 1) generate
etxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (etx_clk, letx_clk);
erxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (erx_clk, lerx_clk);
erxd_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 8)
port map (erxd, lerxd);
erxdv_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_dv, lerx_dv);
erxer_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_er, lerx_er);
erxco_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_col, lerx_col);
erxcr_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_crs, lerx_crs);
etxd_pad : outpadv
generic map(
width => 8,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (etxd, letxd);
etxen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_en, letx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_er, letx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdc, lemdc);
emdio_pad : iopad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdio, lemdioout, lemdioen, lemdioin);
emdint_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (emdint, lemdint);
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3inadd is
generic(
NUM_BITS: positive := 163
);
port (
I: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
C: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3inadd is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
constant a : std_logic_vector(NUM_BITS-1 downto 0):= "1111011011010001000001011001010101011101111101010000100111110010101010101001111111110000100001010001011110110001000111000100100011011010010011110000010101011100010";
begin
D(0) <= I(0) xor B(0) xor C(0) xor a(0);
D(1) <= I(1) xor B(1) xor C(1) xor a(1);
D(2) <= I(2) xor B(2) xor C(2) xor a(2);
D(3) <= I(3) xor B(3) xor C(3) xor a(3);
D(4) <= I(4) xor B(4) xor C(4) xor a(4);
D(5) <= I(5) xor B(5) xor C(5) xor a(5);
D(6) <= I(6) xor B(6) xor C(6) xor a(6);
D(7) <= I(7) xor B(7) xor C(7) xor a(7);
D(8) <= I(8) xor B(8) xor C(8) xor a(8);
D(9) <= I(9) xor B(9) xor C(9) xor a(9);
D(10) <= I(10) xor B(10) xor C(10) xor a(10);
D(11) <= I(11) xor B(11) xor C(11) xor a(11);
D(12) <= I(12) xor B(12) xor C(12) xor a(12);
D(13) <= I(13) xor B(13) xor C(13) xor a(13);
D(14) <= I(14) xor B(14) xor C(14) xor a(14);
D(15) <= I(15) xor B(15) xor C(15) xor a(15);
D(16) <= I(16) xor B(16) xor C(16) xor a(16);
D(17) <= I(17) xor B(17) xor C(17) xor a(17);
D(18) <= I(18) xor B(18) xor C(18) xor a(18);
D(19) <= I(19) xor B(19) xor C(19) xor a(19);
D(20) <= I(20) xor B(20) xor C(20) xor a(20);
D(21) <= I(21) xor B(21) xor C(21) xor a(21);
D(22) <= I(22) xor B(22) xor C(22) xor a(22);
D(23) <= I(23) xor B(23) xor C(23) xor a(23);
D(24) <= I(24) xor B(24) xor C(24) xor a(24);
D(25) <= I(25) xor B(25) xor C(25) xor a(25);
D(26) <= I(26) xor B(26) xor C(26) xor a(26);
D(27) <= I(27) xor B(27) xor C(27) xor a(27);
D(28) <= I(28) xor B(28) xor C(28) xor a(28);
D(29) <= I(29) xor B(29) xor C(29) xor a(29);
D(30) <= I(30) xor B(30) xor C(30) xor a(30);
D(31) <= I(31) xor B(31) xor C(31) xor a(31);
D(32) <= I(32) xor B(32) xor C(32) xor a(32);
D(33) <= I(33) xor B(33) xor C(33) xor a(33);
D(34) <= I(34) xor B(34) xor C(34) xor a(34);
D(35) <= I(35) xor B(35) xor C(35) xor a(35);
D(36) <= I(36) xor B(36) xor C(36) xor a(36);
D(37) <= I(37) xor B(37) xor C(37) xor a(37);
D(38) <= I(38) xor B(38) xor C(38) xor a(38);
D(39) <= I(39) xor B(39) xor C(39) xor a(39);
D(40) <= I(40) xor B(40) xor C(40) xor a(40);
D(41) <= I(41) xor B(41) xor C(41) xor a(41);
D(42) <= I(42) xor B(42) xor C(42) xor a(42);
D(43) <= I(43) xor B(43) xor C(43) xor a(43);
D(44) <= I(44) xor B(44) xor C(44) xor a(44);
D(45) <= I(45) xor B(45) xor C(45) xor a(45);
D(46) <= I(46) xor B(46) xor C(46) xor a(46);
D(47) <= I(47) xor B(47) xor C(47) xor a(47);
D(48) <= I(48) xor B(48) xor C(48) xor a(48);
D(49) <= I(49) xor B(49) xor C(49) xor a(49);
D(50) <= I(50) xor B(50) xor C(50) xor a(50);
D(51) <= I(51) xor B(51) xor C(51) xor a(51);
D(52) <= I(52) xor B(52) xor C(52) xor a(52);
D(53) <= I(53) xor B(53) xor C(53) xor a(53);
D(54) <= I(54) xor B(54) xor C(54) xor a(54);
D(55) <= I(55) xor B(55) xor C(55) xor a(55);
D(56) <= I(56) xor B(56) xor C(56) xor a(56);
D(57) <= I(57) xor B(57) xor C(57) xor a(57);
D(58) <= I(58) xor B(58) xor C(58) xor a(58);
D(59) <= I(59) xor B(59) xor C(59) xor a(59);
D(60) <= I(60) xor B(60) xor C(60) xor a(60);
D(61) <= I(61) xor B(61) xor C(61) xor a(61);
D(62) <= I(62) xor B(62) xor C(62) xor a(62);
D(63) <= I(63) xor B(63) xor C(63) xor a(63);
D(64) <= I(64) xor B(64) xor C(64) xor a(64);
D(65) <= I(65) xor B(65) xor C(65) xor a(65);
D(66) <= I(66) xor B(66) xor C(66) xor a(66);
D(67) <= I(67) xor B(67) xor C(67) xor a(67);
D(68) <= I(68) xor B(68) xor C(68) xor a(68);
D(69) <= I(69) xor B(69) xor C(69) xor a(69);
D(70) <= I(70) xor B(70) xor C(70) xor a(70);
D(71) <= I(71) xor B(71) xor C(71) xor a(71);
D(72) <= I(72) xor B(72) xor C(72) xor a(72);
D(73) <= I(73) xor B(73) xor C(73) xor a(73);
D(74) <= I(74) xor B(74) xor C(74) xor a(74);
D(75) <= I(75) xor B(75) xor C(75) xor a(75);
D(76) <= I(76) xor B(76) xor C(76) xor a(76);
D(77) <= I(77) xor B(77) xor C(77) xor a(77);
D(78) <= I(78) xor B(78) xor C(78) xor a(78);
D(79) <= I(79) xor B(79) xor C(79) xor a(79);
D(80) <= I(80) xor B(80) xor C(80) xor a(80);
D(81) <= I(81) xor B(81) xor C(81) xor a(81);
D(82) <= I(82) xor B(82) xor C(82) xor a(82);
D(83) <= I(83) xor B(83) xor C(83) xor a(83);
D(84) <= I(84) xor B(84) xor C(84) xor a(84);
D(85) <= I(85) xor B(85) xor C(85) xor a(85);
D(86) <= I(86) xor B(86) xor C(86) xor a(86);
D(87) <= I(87) xor B(87) xor C(87) xor a(87);
D(88) <= I(88) xor B(88) xor C(88) xor a(88);
D(89) <= I(89) xor B(89) xor C(89) xor a(89);
D(90) <= I(90) xor B(90) xor C(90) xor a(90);
D(91) <= I(91) xor B(91) xor C(91) xor a(91);
D(92) <= I(92) xor B(92) xor C(92) xor a(92);
D(93) <= I(93) xor B(93) xor C(93) xor a(93);
D(94) <= I(94) xor B(94) xor C(94) xor a(94);
D(95) <= I(95) xor B(95) xor C(95) xor a(95);
D(96) <= I(96) xor B(96) xor C(96) xor a(96);
D(97) <= I(97) xor B(97) xor C(97) xor a(97);
D(98) <= I(98) xor B(98) xor C(98) xor a(98);
D(99) <= I(99) xor B(99) xor C(99) xor a(99);
D(100) <= I(100) xor B(100) xor C(100) xor a(100);
D(101) <= I(101) xor B(101) xor C(101) xor a(101);
D(102) <= I(102) xor B(102) xor C(102) xor a(102);
D(103) <= I(103) xor B(103) xor C(103) xor a(103);
D(104) <= I(104) xor B(104) xor C(104) xor a(104);
D(105) <= I(105) xor B(105) xor C(105) xor a(105);
D(106) <= I(106) xor B(106) xor C(106) xor a(106);
D(107) <= I(107) xor B(107) xor C(107) xor a(107);
D(108) <= I(108) xor B(108) xor C(108) xor a(108);
D(109) <= I(109) xor B(109) xor C(109) xor a(109);
D(110) <= I(110) xor B(110) xor C(110) xor a(110);
D(111) <= I(111) xor B(111) xor C(111) xor a(111);
D(112) <= I(112) xor B(112) xor C(112) xor a(112);
D(113) <= I(113) xor B(113) xor C(113) xor a(113);
D(114) <= I(114) xor B(114) xor C(114) xor a(114);
D(115) <= I(115) xor B(115) xor C(115) xor a(115);
D(116) <= I(116) xor B(116) xor C(116) xor a(116);
D(117) <= I(117) xor B(117) xor C(117) xor a(117);
D(118) <= I(118) xor B(118) xor C(118) xor a(118);
D(119) <= I(119) xor B(119) xor C(119) xor a(119);
D(120) <= I(120) xor B(120) xor C(120) xor a(120);
D(121) <= I(121) xor B(121) xor C(121) xor a(121);
D(122) <= I(122) xor B(122) xor C(122) xor a(122);
D(123) <= I(123) xor B(123) xor C(123) xor a(123);
D(124) <= I(124) xor B(124) xor C(124) xor a(124);
D(125) <= I(125) xor B(125) xor C(125) xor a(125);
D(126) <= I(126) xor B(126) xor C(126) xor a(126);
D(127) <= I(127) xor B(127) xor C(127) xor a(127);
D(128) <= I(128) xor B(128) xor C(128) xor a(128);
D(129) <= I(129) xor B(129) xor C(129) xor a(129);
D(130) <= I(130) xor B(130) xor C(130) xor a(130);
D(131) <= I(131) xor B(131) xor C(131) xor a(131);
D(132) <= I(132) xor B(132) xor C(132) xor a(132);
D(133) <= I(133) xor B(133) xor C(133) xor a(133);
D(134) <= I(134) xor B(134) xor C(134) xor a(134);
D(135) <= I(135) xor B(135) xor C(135) xor a(135);
D(136) <= I(136) xor B(136) xor C(136) xor a(136);
D(137) <= I(137) xor B(137) xor C(137) xor a(137);
D(138) <= I(138) xor B(138) xor C(138) xor a(138);
D(139) <= I(139) xor B(139) xor C(139) xor a(139);
D(140) <= I(140) xor B(140) xor C(140) xor a(140);
D(141) <= I(141) xor B(141) xor C(141) xor a(141);
D(142) <= I(142) xor B(142) xor C(142) xor a(142);
D(143) <= I(143) xor B(143) xor C(143) xor a(143);
D(144) <= I(144) xor B(144) xor C(144) xor a(144);
D(145) <= I(145) xor B(145) xor C(145) xor a(145);
D(146) <= I(146) xor B(146) xor C(146) xor a(146);
D(147) <= I(147) xor B(147) xor C(147) xor a(147);
D(148) <= I(148) xor B(148) xor C(148) xor a(148);
D(149) <= I(149) xor B(149) xor C(149) xor a(149);
D(150) <= I(150) xor B(150) xor C(150) xor a(150);
D(151) <= I(151) xor B(151) xor C(151) xor a(151);
D(152) <= I(152) xor B(152) xor C(152) xor a(152);
D(153) <= I(153) xor B(153) xor C(153) xor a(153);
D(154) <= I(154) xor B(154) xor C(154) xor a(154);
D(155) <= I(155) xor B(155) xor C(155) xor a(155);
D(156) <= I(156) xor B(156) xor C(156) xor a(156);
D(157) <= I(157) xor B(157) xor C(157) xor a(157);
D(158) <= I(158) xor B(158) xor C(158) xor a(158);
D(159) <= I(159) xor B(159) xor C(159) xor a(159);
D(160) <= I(160) xor B(160) xor C(160) xor a(160);
D(161) <= I(161) xor B(161) xor C(161) xor a(161);
D(162) <= I(162) xor B(162) xor C(162) xor a(162);
end; |
----------------------------------------------------------------------------------
-- Description: Driver for 4-digit 7-segment display.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_UNSIGNED.ALL;
entity SegmentDriver is
Port ( disp1 : in std_logic_vector (6 downto 0);
disp2 : in std_logic_vector (6 downto 0);
disp3 : in std_logic_vector (6 downto 0);
disp4 : in std_logic_vector (6 downto 0);
clk : in std_logic;
display_seg : out std_logic_vector (6 downto 0);
display_ena : out std_logic_vector (3 downto 0));
end SegmentDriver;
architecture Behavioral of SegmentDriver is
signal cnt : std_logic_vector (1 downto 0);
begin
process (clk) begin
if (rising_edge(clk)) then
cnt <= cnt + 1;
if (cnt = "11") then
cnt <= "00";
end if;
case (cnt) is
when "00" =>
display_seg <= disp1;
display_ena <= "1110";
when "01" =>
display_seg <= disp2;
display_ena <= "1101";
when "10" =>
display_seg <= disp3;
display_ena <= "1011";
when "11" =>
display_seg <= disp4;
display_ena <= "0111";
when others =>
display_seg <= (others => '0');
display_ena <= "0000";
end case;
end if;
end process;
end Behavioral; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Testbench: Tests global constants, functions and settings
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
use PoC.config.all;
use PoC.utils.all;
-- simulation only packages
use PoC.sim_types.all;
use PoC.simulation.all;
entity config_tb is
end config_tb;
architecture tb of config_tb is
signal SimQuiet : boolean := true;
begin
procChecker : process
constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker");
begin
if not SimQuiet then
report "is simulation?: " & boolean'image(SIMULATION) severity note;
report "Vendor: " & T_VENDOR'image(VENDOR) severity note;
report "Device: " & T_DEVICE'image(DEVICE) severity note;
report "Device Family: " & T_DEVICE_FAMILY'image(DEVICE_FAMILY) severity note;
report "Device Subtype: " & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) severity note;
report "Device Series: " & T_DEVICE_SERIES'image(DEVICE_SERIES) severity note;
report "Device Generation: " & integer'image(DEVICE_GENERATION) severity note;
report "Device Number: " & integer'image(DEVICE_NUMBER) severity note;
report "--------------------------------------------------" severity note;
report "LUT fan-in: " & integer'image(LUT_FANIN) severity note;
report "Transceiver: " & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) severity note;
end if;
simAssertion((SIMULATION = TRUE), "SIMULATION=" & boolean'image(SIMULATION) & " Expected=TRUE");
simAssertion((VENDOR = VENDOR_GENERIC), "VENDOR= " & T_VENDOR'image(VENDOR) & " Expected=VENDOR_XILINX");
simAssertion((DEVICE = DEVICE_GENERIC), "DEVICE=" & T_DEVICE'image(DEVICE) & " Expected=DEVICE_KINTEX7");
simAssertion((DEVICE_FAMILY = DEVICE_FAMILY_GENERIC), "DEVICE_FAMILY=" & T_DEVICE_FAMILY'image(DEVICE_FAMILY) & " Expected=DEVICE_FAMILY_KINTEX");
simAssertion((DEVICE_NUMBER = 0), "DEVICE_NUMBER=" & integer'image(DEVICE_NUMBER) & " Expected=325");
simAssertion((DEVICE_SUBTYPE = DEVICE_SUBTYPE_GENERIC), "DEVICE_SUBTYPE=" & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) & " Expected=DEVICE_SUBTYPE_T");
simAssertion((DEVICE_GENERATION = 0), "DEVICE_GENERATION=" & integer'image(DEVICE_GENERATION) & " Expected=7");
simAssertion((DEVICE_SERIES = DEVICE_SERIES_GENERIC), "DEVICE_SERIES=" & T_DEVICE_SERIES'image(DEVICE_SERIES) & " Expected=DEVICE_SERIES_7_SERIES");
simAssertion((LUT_FANIN = 6), "LUT_FANIN=" & integer'image(LUT_FANIN) & " Expected=6");
simAssertion((TRANSCEIVER_TYPE = TRANSCEIVER_GENERIC), "TRANSCEIVER_TYPE=" & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) & " Expected=TRANSCEIVER_GTXE2");
-- This process is finished
simDeactivateProcess(simProcessID);
wait; -- forever
end process;
end architecture;
|
###################################################################
# Makefile for Virtual Processor testcode in Modelsim
#
# Copyright (c) 2005-2021 Simon Southwell.
#
# This file is part of VProc.
#
# VProc is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# VProc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with VProc. If not, see <http://www.gnu.org/licenses/>.
#
# $Id: makefile.vhd,v 1.2 2021/05/05 08:07:40 simon Exp $
# $Source: /home/simon/CVS/src/HDL/VProc/makefile.vhd,v $
#
###################################################################
# MODELSIM and MODEL_TECH environment variables must be set
# Define the maximum number of supported VProcs in the compile pli library
MAX_NUM_VPROC = 64
SRCDIR = code
USRCDIR = usercode
VOBJDIR = obj
# VPROC C source code
VPROC_C = VSched.c \
VUser.c
# Test user code
USER_C = VUserMain0.c VUserMain1.c
VOBJS = ${addprefix ${VOBJDIR}/, ${VPROC_C:%.c=%.o} ${USER_C:%.c=%.o}}
# Generated PLI C library
VPROC_PLI = VProc.so
VLIB = libvproc.a
VPROC_TOP = test
# Get OS type
OSTYPE:=$(shell uname)
# Set OS specific variables between Linux and Windows (MinGW)
ifeq (${OSTYPE}, Linux)
CFLAGS_SO = -shared -lpthread -lrt -rdynamic
CPPSTD = -std=c++11
else
CFLAGS_SO = -shared -Wl,-export-all-symbols
CPPSTD =
endif
CC = gcc
C++ = g++
CFLAGS = -fPIC \
-m32 \
-g \
-I${SRCDIR} \
-I${USRCDIR} \
-I${MODEL_TECH}/../include \
-DVP_MAX_NODES=${MAX_NUM_VPROC} \
-DMODELSIM \
-DVPROC_VHDL \
-D_REENTRANT
# Comman flags for vsim
VSIMFLAGS = -pli ${VPROC_PLI} ${VPROC_TOP}
#------------------------------------------------------
# BUILD RULES
#------------------------------------------------------
all: ${VPROC_PLI} vhdl
${VOBJDIR}/%.o: ${SRCDIR}/%.c
@${CC} -c ${CFLAGS} $< -o $@
${VOBJDIR}/%.o: ${USRCDIR}/%.c
@${CC} -Wno-write-strings -c ${CFLAGS} $< -o $@
${VOBJDIR}/%.o: ${USRCDIR}/%.cpp
@${C++} ${CPPSTD} -Wno-write-strings -c ${CFLAGS} $< -o $@
${VLIB} : ${VOBJS} ${VOBJDIR}
@ar cr ${VLIB} ${VOBJS}
${VOBJS}: | ${VOBJDIR}
${VOBJDIR}:
@mkdir ${VOBJDIR}
${VPROC_PLI}: ${VLIB} ${VOBJDIR}/veriuser.o ${USER_C:%.c=${VOBJDIR}/%.o}
@${C++} ${CPPSTD} \
${CFLAGS_SO} \
${CFLAGS} \
-Wl,-whole-archive \
${VOBJDIR}/veriuser.o \
-lpthread \
-L${MODEL_TECH} \
-lmtipli \
-L. -lvproc \
-Wl,-no-whole-archive \
-o $@
# Let modelsim decide what's changed in the VHDL
.PHONY: vhdl
vhdl: ${VPROC_PLI}
@if [ ! -d "./work" ]; then \
vlib work; \
fi
@vcom -quiet -2008 -f files.tcl -work work
#------------------------------------------------------
# EXECUTION RULES
#------------------------------------------------------
run: vhdl
@vsim -c ${VSIMFLAGS}
rungui: vhdl
@if [ -e wave.do ]; then \
vsim -gui -do wave.do ${VSIMFLAGS}; \
else \
vsim -gui ${VSIMFLAGS}; \
fi
gui: rungui
#------------------------------------------------------
# CLEANING RULES
#------------------------------------------------------
clean:
@rm -rf ${VPROC_PLI} ${VLIB} ${VOBJS} ${VOBJDIR}/* *.wlf
@if [ -d "./work" ]; then \
vdel -all; \
fi
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux_testbench is end mux_testbench;
architecture behavioral of mux_testbench is
signal d : std_logic_vector(3 downto 0);
signal s : std_logic_vector(1 downto 0);
signal m : std_logic;
component mux
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
m : out std_logic
);
end component;
begin
process begin
for i in 0 to 3 loop
s <= std_logic_vector(to_unsigned(i,2));
for j in 0 to 15 loop
d <= std_logic_vector(to_unsigned(j,4));
wait for 10 ns;
end loop;
end loop;
end process;
uut1 : mux
port map (
a => d(0),
b => d(1),
c => d(2),
d => d(3),
s => s,
m => m
);
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11a is
end entity inline_11a;
----------------------------------------------------------------
architecture test of inline_11a is
-- code from book:
type real_vector is array (natural range <>) of real;
--
subtype gains is real_vector(15 downto 0);
--
quantity max_temperatures : real_vector(1 to 10);
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11a is
end entity inline_11a;
----------------------------------------------------------------
architecture test of inline_11a is
-- code from book:
type real_vector is array (natural range <>) of real;
--
subtype gains is real_vector(15 downto 0);
--
quantity max_temperatures : real_vector(1 to 10);
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11a is
end entity inline_11a;
----------------------------------------------------------------
architecture test of inline_11a is
-- code from book:
type real_vector is array (natural range <>) of real;
--
subtype gains is real_vector(15 downto 0);
--
quantity max_temperatures : real_vector(1 to 10);
-- end of code from book
begin
end architecture test;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:50 wig Exp $
-- $Date: 2004/04/06 10:50:50 $
-- $Log: inst_ec_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:50 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ec_e_rtl_conf / inst_ec_e
--
configuration inst_ec_e_rtl_conf of inst_ec_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eca : inst_eca_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eca_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ecb : inst_ecb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ecb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ecc : inst_ecc_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ecc_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ec_e_rtl_conf;
--
-- End of Generated Configuration inst_ec_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief RISC-V "Rocket Core" with enabled L2-cache.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! TileLink interface description.
use rocketlib.types_rocket.all;
--! @brief Rocket Chip Top-level with enabled L2-cache.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uached Tile AXI master index
--! @param[in] rst Reset.Active High. Usually assigned to button "Center".
--! @param[in] clk_sys System clock.
--! @param[in] clk_htif HTIF bus clock.
--! @param[in] msti AXI System bus response.
--! @param[out] msto1 Cached Tile requests converted to AXI system bus.
--! @param[out] msto2 Uncached Tile requests converted to AXI system bus.
--! @param[in] htifo HTIF bus request bus. Device-to-Tile.
--! @param[out] htifi HTIF bus response bus. Tile-to-Device
entity rocket_l2cache is
generic (
xindex1 : integer := 0;
xindex2 : integer := 0
);
port
(
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
--! @}
end rocket_l2cache;
--! @brief Rocket-chip with L2-cache architecture declaration.
architecture arch_rocket_l2cache of rocket_l2cache is
constant xmstconfig1 : nasti_master_config_type := (
xindex => xindex1,
vid => VENDOR_GNSSSENSOR,
did => RISCV_CACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xindex2,
vid => VENDOR_GNSSSENSOR,
did => RISCV_UNCACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
signal rstn : std_logic;
signal init_ena : std_logic;
--! Multiplexed signal of the external HTIF requests and of the
--! 'starter' module.
signal htifo_starter : host_out_type;
signal htifo_mux : host_out_type;
signal htifi_deser : host_in_type;
signal clk_htif : std_logic;
signal cpu2htif : htif_serdes_in_type;
signal htif2cpu : htif_serdes_out_type;
--! @brief Rocket Cores hard-reset initialization module
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allowed to CPU start
--! execution. This reseting cycle is continuing upto external
--! write 0-value into this MRESET register.
--! param[in] core_idx Recipient core index. Multicore not implemented yet.
--! param[in] clk Clock sinal for the HTIFIO bus.
--! param[in] nrst Module reset signal with the active Low level.
--! param[in] hosti HostIO interface input signals.
--! param[out] hosto HostIO interface output signals.
--! param[in] srdi HostIO serialized data input.
--! param[out] srdo HostIO serialized data output.
component htif_serdes is
generic (
core_idx : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
hostoi : in host_out_type;
hostio : out host_in_type;
srdi : in htif_serdes_in_type;
srdo : out htif_serdes_out_type
);
end component;
--! @brief Hard-reset 'Uncore' initializer.
--! @details Rocket-chip is constantly reseting after power-up to start
--! execution we must write into MRESET CSR register.
component starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end component;
--! @brief Rocket NoC Verilog implementation generated by SCALA.
component Top
port (
clk : in std_logic;
reset : in std_logic;
io_host_clk : out std_logic;
io_host_clk_edge : out std_logic;
io_host_in_ready : out std_logic;
io_host_in_valid : in std_logic;
io_host_in_bits : in std_logic_vector(15 downto 0);
io_host_out_ready : in std_logic;
io_host_out_valid : out std_logic;
io_host_out_bits : out std_logic_vector(15 downto 0);
io_host_debug_stats_csr : out std_logic;
io_mem_backup_ctrl_en : in std_logic;
io_mem_backup_ctrl_in_valid : in std_logic;
io_mem_backup_ctrl_out_ready : in std_logic;
io_mem_backup_ctrl_out_valid : out std_logic;
io_mem_0_aw_ready : in std_logic;
io_mem_0_aw_valid : out std_logic;
io_mem_0_aw_bits_addr : out std_logic_vector(31 downto 0);
io_mem_0_aw_bits_len : out std_logic_vector(7 downto 0);
io_mem_0_aw_bits_size : out std_logic_vector(2 downto 0);
io_mem_0_aw_bits_burst : out std_logic_vector(1 downto 0);
io_mem_0_aw_bits_lock : out std_logic;
io_mem_0_aw_bits_cache : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_prot : out std_logic_vector(2 downto 0);
io_mem_0_aw_bits_qos : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_region : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_aw_bits_user : out std_logic;
io_mem_0_w_ready : in std_logic;
io_mem_0_w_valid : out std_logic;
io_mem_0_w_bits_data : out std_logic_vector(127 downto 0);
io_mem_0_w_bits_last : out std_logic;
io_mem_0_w_bits_strb : out std_logic_vector(15 downto 0);
io_mem_0_w_bits_user : out std_logic;
io_mem_0_b_ready : out std_logic;
io_mem_0_b_valid : in std_logic;
io_mem_0_b_bits_resp : in std_logic_vector(1 downto 0);
io_mem_0_b_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_b_bits_user : in std_logic;
io_mem_0_ar_ready : in std_logic;
io_mem_0_ar_valid : out std_logic;
io_mem_0_ar_bits_addr : out std_logic_vector(31 downto 0);
io_mem_0_ar_bits_len : out std_logic_vector(7 downto 0);
io_mem_0_ar_bits_size : out std_logic_vector(2 downto 0);
io_mem_0_ar_bits_burst : out std_logic_vector(1 downto 0);
io_mem_0_ar_bits_lock : out std_logic;
io_mem_0_ar_bits_cache : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_prot : out std_logic_vector(2 downto 0);
io_mem_0_ar_bits_qos : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_region : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_ar_bits_user : out std_logic;
io_mem_0_r_ready : out std_logic;
io_mem_0_r_valid : in std_logic;
io_mem_0_r_bits_resp : in std_logic_vector(1 downto 0);
io_mem_0_r_bits_data : in std_logic_vector(127 downto 0);
io_mem_0_r_bits_last : in std_logic;
io_mem_0_r_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_r_bits_user : in std_logic;
--! mmio
io_mmio_aw_ready : in std_logic;
io_mmio_aw_valid : out std_logic;
io_mmio_aw_bits_addr : out std_logic_vector(31 downto 0);
io_mmio_aw_bits_len : out std_logic_vector(7 downto 0);
io_mmio_aw_bits_size : out std_logic_vector(2 downto 0);
io_mmio_aw_bits_burst : out std_logic_vector(1 downto 0);
io_mmio_aw_bits_lock : out std_logic;
io_mmio_aw_bits_cache : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_prot : out std_logic_vector(2 downto 0);
io_mmio_aw_bits_qos : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_region : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_aw_bits_user : out std_logic;
io_mmio_w_ready : in std_logic;
io_mmio_w_valid : out std_logic;
io_mmio_w_bits_data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
io_mmio_w_bits_last : out std_logic;
io_mmio_w_bits_strb : out std_logic_vector(15 downto 0);
io_mmio_w_bits_user : out std_logic;
io_mmio_b_ready : out std_logic;
io_mmio_b_valid : in std_logic;
io_mmio_b_bits_resp : in std_logic_vector(1 downto 0);
io_mmio_b_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_b_bits_user : in std_logic;
io_mmio_ar_ready : in std_logic;
io_mmio_ar_valid : out std_logic;
io_mmio_ar_bits_addr : out std_logic_vector(31 downto 0);
io_mmio_ar_bits_len : out std_logic_vector(7 downto 0);
io_mmio_ar_bits_size : out std_logic_vector(2 downto 0);
io_mmio_ar_bits_burst : out std_logic_vector(1 downto 0);
io_mmio_ar_bits_lock : out std_logic;
io_mmio_ar_bits_cache : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_prot : out std_logic_vector(2 downto 0);
io_mmio_ar_bits_qos : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_region : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_ar_bits_user : out std_logic;
io_mmio_r_ready : out std_logic;
io_mmio_r_valid : in std_logic;
io_mmio_r_bits_resp : in std_logic_vector(1 downto 0);
io_mmio_r_bits_data : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
io_mmio_r_bits_last : in std_logic;
io_mmio_r_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_r_bits_user : in std_logic
--init : in std_logic
);
end component;
begin
mstcfg1 <= xmstconfig1;
mstcfg2 <= xmstconfig2;
rstn <= not rst;
clk_htif <= clk_sys; -- clock htif not used in Scala generated sources when FPGA define enabled.
------------------------------------
-- Hardware init and MRESET for the CPUs
start0 : starter port map
(
clk => clk_htif,
nrst => rstn,
i_host => htifi_deser,
o_host => htifo_starter,
o_init_ena => init_ena
);
--! Starter HTIF bus has the highest priority because it is
--! unreset CPU/Uncore at the very begining after hard-reset and then
--! doesn't make any action.
htifo_mux <= htifo_starter when init_ena = '1' else htifoi;
serdes0 : htif_serdes generic map (
core_idx => 0
) port map (
clk => clk_htif,
nrst => rstn,
hostoi => htifo_mux,
hostio => htifi_deser,
srdi => cpu2htif,
srdo => htif2cpu
);
htifio <= htifi_deser;
------------------------------------
--! @brief NoC core instance.
rocket0 : Top port map
(
clk => clk_sys, --in
reset => rst, --in
io_host_in_valid => htif2cpu.valid, --in
io_host_in_ready => cpu2htif.ready, --out
io_host_in_bits => htif2cpu.bits, --in[15:0]
io_host_out_valid => cpu2htif.valid, --out
io_host_out_ready => htif2cpu.ready, --in
io_host_out_bits => cpu2htif.bits, --out[15:0] goes to Starter and Memory DeSerializer
io_host_clk => clk_htif, --out
io_host_clk_edge => open, --out
io_host_debug_stats_csr => open, --out (unused)
io_mem_backup_ctrl_en => '0', --in
io_mem_backup_ctrl_in_valid => '0',--mem_bk_in_valid_delay, --in
io_mem_backup_ctrl_out_ready => '0',--mem_bk_out_ready_delay,--in
io_mem_backup_ctrl_out_valid => open,--mem_bk_out_valid_delay,--out
--! mem
io_mem_0_aw_ready => msti.aw_ready,--in
io_mem_0_aw_valid => msto1.aw_valid,--out
io_mem_0_aw_bits_addr => msto1.aw_bits.addr,--out[31:0]
io_mem_0_aw_bits_len => msto1.aw_bits.len,--out[7:0]
io_mem_0_aw_bits_size => msto1.aw_bits.size,--out[2:0]
io_mem_0_aw_bits_burst => msto1.aw_bits.burst,--out[1:0]
io_mem_0_aw_bits_lock => msto1.aw_bits.lock,--out
io_mem_0_aw_bits_cache => msto1.aw_bits.cache,--out[3:0]
io_mem_0_aw_bits_prot => msto1.aw_bits.prot,--out[2:0]
io_mem_0_aw_bits_qos => msto1.aw_bits.qos,--out[3:0]
io_mem_0_aw_bits_region => msto1.aw_bits.region,--out[3:0]
io_mem_0_aw_bits_id => msto1.aw_id,--out[5:0]
io_mem_0_aw_bits_user => msto1.aw_user,--out
io_mem_0_w_ready => msti.w_ready,--in
io_mem_0_w_valid => msto1.w_valid,--out
io_mem_0_w_bits_data => msto1.w_data,--out[127:0]
io_mem_0_w_bits_last => msto1.w_last,--out
io_mem_0_w_bits_strb => msto1.w_strb,--out[15:0]
io_mem_0_w_bits_user => msto1.w_user,--out
io_mem_0_b_ready => msto1.b_ready,--out
io_mem_0_b_valid => msti.b_valid,--in
io_mem_0_b_bits_resp => msti.b_resp,--in[1:0]
io_mem_0_b_bits_id => msti.b_id,--in[5:0]
io_mem_0_b_bits_user => msti.b_user,--in
io_mem_0_ar_ready => msti.ar_ready,--in
io_mem_0_ar_valid => msto1.ar_valid,--out
io_mem_0_ar_bits_addr => msto1.ar_bits.addr,--out[31:0]
io_mem_0_ar_bits_len => msto1.ar_bits.len,--out[7:0]
io_mem_0_ar_bits_size => msto1.ar_bits.size,--out[2:0]
io_mem_0_ar_bits_burst => msto1.ar_bits.burst,--out[1:0]
io_mem_0_ar_bits_lock => msto1.ar_bits.lock,--out
io_mem_0_ar_bits_cache => msto1.ar_bits.cache,--out[3:0]
io_mem_0_ar_bits_prot => msto1.ar_bits.prot,--out[2:0]
io_mem_0_ar_bits_qos => msto1.ar_bits.qos,--out[3:0]
io_mem_0_ar_bits_region => msto1.ar_bits.region,--out[3:0]
io_mem_0_ar_bits_id => msto1.ar_id,--out[5:0]
io_mem_0_ar_bits_user => msto1.ar_user,--out
io_mem_0_r_ready => msto1.r_ready,--out
io_mem_0_r_valid => msti.r_valid,--in
io_mem_0_r_bits_resp => msti.r_resp,--in[1:0]
io_mem_0_r_bits_data => msti.r_data,--in[127:0]
io_mem_0_r_bits_last => msti.r_last,--in
io_mem_0_r_bits_id => msti.r_id,--in[5:0]
io_mem_0_r_bits_user => msti.r_user,--in
--! mmio
io_mmio_aw_ready => msti.aw_ready,--in
io_mmio_aw_valid => msto2.aw_valid,--out
io_mmio_aw_bits_addr => msto2.aw_bits.addr,--out[31:0]
io_mmio_aw_bits_len => msto2.aw_bits.len,--out[7:0]
io_mmio_aw_bits_size => msto2.aw_bits.size,--out[2:0]
io_mmio_aw_bits_burst => msto2.aw_bits.burst,--out[1:0]
io_mmio_aw_bits_lock => msto2.aw_bits.lock,--out
io_mmio_aw_bits_cache => msto2.aw_bits.cache,--out[3:0]
io_mmio_aw_bits_prot => msto2.aw_bits.prot,--out[2:0]
io_mmio_aw_bits_qos => msto2.aw_bits.qos,--out[3:0]
io_mmio_aw_bits_region => msto2.aw_bits.region,--out[3:0]
io_mmio_aw_bits_id => msto2.aw_id,--out[5:0]
io_mmio_aw_bits_user => msto2.aw_user,--out
io_mmio_w_ready => msti.w_ready,--in
io_mmio_w_valid => msto2.w_valid,--out
io_mmio_w_bits_data => msto2.w_data,--out[127:0]
io_mmio_w_bits_last => msto2.w_last,--out
io_mmio_w_bits_strb => msto2.w_strb,--out[15:0]
io_mmio_w_bits_user => msto2.w_user,--out
io_mmio_b_ready => msto2.b_ready,--out
io_mmio_b_valid => msti.b_valid,--in
io_mmio_b_bits_resp => msti.b_resp,--in[1:0]
io_mmio_b_bits_id => msti.b_id,--in[5:0]
io_mmio_b_bits_user => msti.b_user,--in
io_mmio_ar_ready => msti.ar_ready,--in
io_mmio_ar_valid => msto2.ar_valid,--out
io_mmio_ar_bits_addr => msto2.ar_bits.addr,--out[31:0]
io_mmio_ar_bits_len => msto2.ar_bits.len,--out[7:0]
io_mmio_ar_bits_size => msto2.ar_bits.size,--out[2:0]
io_mmio_ar_bits_burst => msto2.ar_bits.burst,--out[1:0]
io_mmio_ar_bits_lock => msto2.ar_bits.lock,--out
io_mmio_ar_bits_cache => msto2.ar_bits.cache,--out[3:0]
io_mmio_ar_bits_prot => msto2.ar_bits.prot,--out[2:0]
io_mmio_ar_bits_qos => msto2.ar_bits.qos,--out[3:0]
io_mmio_ar_bits_region => msto2.ar_bits.region,--out[3:0]
io_mmio_ar_bits_id => msto2.ar_id,--out[5:0]
io_mmio_ar_bits_user => msto2.ar_user,--out
io_mmio_r_ready => msto2.r_ready,--out
io_mmio_r_valid => msti.r_valid,--in
io_mmio_r_bits_resp => msti.r_resp,--in[1:0]
io_mmio_r_bits_data => msti.r_data,--in[127:0]
io_mmio_r_bits_last => msti.r_last,--in
io_mmio_r_bits_id => msti.r_id,--in[5:0]
io_mmio_r_bits_user => msti.r_user--in
);
end arch_rocket_l2cache;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief RISC-V "Rocket Core" with enabled L2-cache.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! TileLink interface description.
use rocketlib.types_rocket.all;
--! @brief Rocket Chip Top-level with enabled L2-cache.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uached Tile AXI master index
--! @param[in] rst Reset.Active High. Usually assigned to button "Center".
--! @param[in] clk_sys System clock.
--! @param[in] clk_htif HTIF bus clock.
--! @param[in] msti AXI System bus response.
--! @param[out] msto1 Cached Tile requests converted to AXI system bus.
--! @param[out] msto2 Uncached Tile requests converted to AXI system bus.
--! @param[in] htifo HTIF bus request bus. Device-to-Tile.
--! @param[out] htifi HTIF bus response bus. Tile-to-Device
entity rocket_l2cache is
generic (
xindex1 : integer := 0;
xindex2 : integer := 0
);
port
(
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
--! @}
end rocket_l2cache;
--! @brief Rocket-chip with L2-cache architecture declaration.
architecture arch_rocket_l2cache of rocket_l2cache is
constant xmstconfig1 : nasti_master_config_type := (
xindex => xindex1,
vid => VENDOR_GNSSSENSOR,
did => RISCV_CACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xindex2,
vid => VENDOR_GNSSSENSOR,
did => RISCV_UNCACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
signal rstn : std_logic;
signal init_ena : std_logic;
--! Multiplexed signal of the external HTIF requests and of the
--! 'starter' module.
signal htifo_starter : host_out_type;
signal htifo_mux : host_out_type;
signal htifi_deser : host_in_type;
signal clk_htif : std_logic;
signal cpu2htif : htif_serdes_in_type;
signal htif2cpu : htif_serdes_out_type;
--! @brief Rocket Cores hard-reset initialization module
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allowed to CPU start
--! execution. This reseting cycle is continuing upto external
--! write 0-value into this MRESET register.
--! param[in] core_idx Recipient core index. Multicore not implemented yet.
--! param[in] clk Clock sinal for the HTIFIO bus.
--! param[in] nrst Module reset signal with the active Low level.
--! param[in] hosti HostIO interface input signals.
--! param[out] hosto HostIO interface output signals.
--! param[in] srdi HostIO serialized data input.
--! param[out] srdo HostIO serialized data output.
component htif_serdes is
generic (
core_idx : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
hostoi : in host_out_type;
hostio : out host_in_type;
srdi : in htif_serdes_in_type;
srdo : out htif_serdes_out_type
);
end component;
--! @brief Hard-reset 'Uncore' initializer.
--! @details Rocket-chip is constantly reseting after power-up to start
--! execution we must write into MRESET CSR register.
component starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end component;
--! @brief Rocket NoC Verilog implementation generated by SCALA.
component Top
port (
clk : in std_logic;
reset : in std_logic;
io_host_clk : out std_logic;
io_host_clk_edge : out std_logic;
io_host_in_ready : out std_logic;
io_host_in_valid : in std_logic;
io_host_in_bits : in std_logic_vector(15 downto 0);
io_host_out_ready : in std_logic;
io_host_out_valid : out std_logic;
io_host_out_bits : out std_logic_vector(15 downto 0);
io_host_debug_stats_csr : out std_logic;
io_mem_backup_ctrl_en : in std_logic;
io_mem_backup_ctrl_in_valid : in std_logic;
io_mem_backup_ctrl_out_ready : in std_logic;
io_mem_backup_ctrl_out_valid : out std_logic;
io_mem_0_aw_ready : in std_logic;
io_mem_0_aw_valid : out std_logic;
io_mem_0_aw_bits_addr : out std_logic_vector(31 downto 0);
io_mem_0_aw_bits_len : out std_logic_vector(7 downto 0);
io_mem_0_aw_bits_size : out std_logic_vector(2 downto 0);
io_mem_0_aw_bits_burst : out std_logic_vector(1 downto 0);
io_mem_0_aw_bits_lock : out std_logic;
io_mem_0_aw_bits_cache : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_prot : out std_logic_vector(2 downto 0);
io_mem_0_aw_bits_qos : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_region : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_aw_bits_user : out std_logic;
io_mem_0_w_ready : in std_logic;
io_mem_0_w_valid : out std_logic;
io_mem_0_w_bits_data : out std_logic_vector(127 downto 0);
io_mem_0_w_bits_last : out std_logic;
io_mem_0_w_bits_strb : out std_logic_vector(15 downto 0);
io_mem_0_w_bits_user : out std_logic;
io_mem_0_b_ready : out std_logic;
io_mem_0_b_valid : in std_logic;
io_mem_0_b_bits_resp : in std_logic_vector(1 downto 0);
io_mem_0_b_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_b_bits_user : in std_logic;
io_mem_0_ar_ready : in std_logic;
io_mem_0_ar_valid : out std_logic;
io_mem_0_ar_bits_addr : out std_logic_vector(31 downto 0);
io_mem_0_ar_bits_len : out std_logic_vector(7 downto 0);
io_mem_0_ar_bits_size : out std_logic_vector(2 downto 0);
io_mem_0_ar_bits_burst : out std_logic_vector(1 downto 0);
io_mem_0_ar_bits_lock : out std_logic;
io_mem_0_ar_bits_cache : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_prot : out std_logic_vector(2 downto 0);
io_mem_0_ar_bits_qos : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_region : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_ar_bits_user : out std_logic;
io_mem_0_r_ready : out std_logic;
io_mem_0_r_valid : in std_logic;
io_mem_0_r_bits_resp : in std_logic_vector(1 downto 0);
io_mem_0_r_bits_data : in std_logic_vector(127 downto 0);
io_mem_0_r_bits_last : in std_logic;
io_mem_0_r_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_r_bits_user : in std_logic;
--! mmio
io_mmio_aw_ready : in std_logic;
io_mmio_aw_valid : out std_logic;
io_mmio_aw_bits_addr : out std_logic_vector(31 downto 0);
io_mmio_aw_bits_len : out std_logic_vector(7 downto 0);
io_mmio_aw_bits_size : out std_logic_vector(2 downto 0);
io_mmio_aw_bits_burst : out std_logic_vector(1 downto 0);
io_mmio_aw_bits_lock : out std_logic;
io_mmio_aw_bits_cache : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_prot : out std_logic_vector(2 downto 0);
io_mmio_aw_bits_qos : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_region : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_aw_bits_user : out std_logic;
io_mmio_w_ready : in std_logic;
io_mmio_w_valid : out std_logic;
io_mmio_w_bits_data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
io_mmio_w_bits_last : out std_logic;
io_mmio_w_bits_strb : out std_logic_vector(15 downto 0);
io_mmio_w_bits_user : out std_logic;
io_mmio_b_ready : out std_logic;
io_mmio_b_valid : in std_logic;
io_mmio_b_bits_resp : in std_logic_vector(1 downto 0);
io_mmio_b_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_b_bits_user : in std_logic;
io_mmio_ar_ready : in std_logic;
io_mmio_ar_valid : out std_logic;
io_mmio_ar_bits_addr : out std_logic_vector(31 downto 0);
io_mmio_ar_bits_len : out std_logic_vector(7 downto 0);
io_mmio_ar_bits_size : out std_logic_vector(2 downto 0);
io_mmio_ar_bits_burst : out std_logic_vector(1 downto 0);
io_mmio_ar_bits_lock : out std_logic;
io_mmio_ar_bits_cache : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_prot : out std_logic_vector(2 downto 0);
io_mmio_ar_bits_qos : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_region : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_ar_bits_user : out std_logic;
io_mmio_r_ready : out std_logic;
io_mmio_r_valid : in std_logic;
io_mmio_r_bits_resp : in std_logic_vector(1 downto 0);
io_mmio_r_bits_data : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
io_mmio_r_bits_last : in std_logic;
io_mmio_r_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_r_bits_user : in std_logic
--init : in std_logic
);
end component;
begin
mstcfg1 <= xmstconfig1;
mstcfg2 <= xmstconfig2;
rstn <= not rst;
clk_htif <= clk_sys; -- clock htif not used in Scala generated sources when FPGA define enabled.
------------------------------------
-- Hardware init and MRESET for the CPUs
start0 : starter port map
(
clk => clk_htif,
nrst => rstn,
i_host => htifi_deser,
o_host => htifo_starter,
o_init_ena => init_ena
);
--! Starter HTIF bus has the highest priority because it is
--! unreset CPU/Uncore at the very begining after hard-reset and then
--! doesn't make any action.
htifo_mux <= htifo_starter when init_ena = '1' else htifoi;
serdes0 : htif_serdes generic map (
core_idx => 0
) port map (
clk => clk_htif,
nrst => rstn,
hostoi => htifo_mux,
hostio => htifi_deser,
srdi => cpu2htif,
srdo => htif2cpu
);
htifio <= htifi_deser;
------------------------------------
--! @brief NoC core instance.
rocket0 : Top port map
(
clk => clk_sys, --in
reset => rst, --in
io_host_in_valid => htif2cpu.valid, --in
io_host_in_ready => cpu2htif.ready, --out
io_host_in_bits => htif2cpu.bits, --in[15:0]
io_host_out_valid => cpu2htif.valid, --out
io_host_out_ready => htif2cpu.ready, --in
io_host_out_bits => cpu2htif.bits, --out[15:0] goes to Starter and Memory DeSerializer
io_host_clk => clk_htif, --out
io_host_clk_edge => open, --out
io_host_debug_stats_csr => open, --out (unused)
io_mem_backup_ctrl_en => '0', --in
io_mem_backup_ctrl_in_valid => '0',--mem_bk_in_valid_delay, --in
io_mem_backup_ctrl_out_ready => '0',--mem_bk_out_ready_delay,--in
io_mem_backup_ctrl_out_valid => open,--mem_bk_out_valid_delay,--out
--! mem
io_mem_0_aw_ready => msti.aw_ready,--in
io_mem_0_aw_valid => msto1.aw_valid,--out
io_mem_0_aw_bits_addr => msto1.aw_bits.addr,--out[31:0]
io_mem_0_aw_bits_len => msto1.aw_bits.len,--out[7:0]
io_mem_0_aw_bits_size => msto1.aw_bits.size,--out[2:0]
io_mem_0_aw_bits_burst => msto1.aw_bits.burst,--out[1:0]
io_mem_0_aw_bits_lock => msto1.aw_bits.lock,--out
io_mem_0_aw_bits_cache => msto1.aw_bits.cache,--out[3:0]
io_mem_0_aw_bits_prot => msto1.aw_bits.prot,--out[2:0]
io_mem_0_aw_bits_qos => msto1.aw_bits.qos,--out[3:0]
io_mem_0_aw_bits_region => msto1.aw_bits.region,--out[3:0]
io_mem_0_aw_bits_id => msto1.aw_id,--out[5:0]
io_mem_0_aw_bits_user => msto1.aw_user,--out
io_mem_0_w_ready => msti.w_ready,--in
io_mem_0_w_valid => msto1.w_valid,--out
io_mem_0_w_bits_data => msto1.w_data,--out[127:0]
io_mem_0_w_bits_last => msto1.w_last,--out
io_mem_0_w_bits_strb => msto1.w_strb,--out[15:0]
io_mem_0_w_bits_user => msto1.w_user,--out
io_mem_0_b_ready => msto1.b_ready,--out
io_mem_0_b_valid => msti.b_valid,--in
io_mem_0_b_bits_resp => msti.b_resp,--in[1:0]
io_mem_0_b_bits_id => msti.b_id,--in[5:0]
io_mem_0_b_bits_user => msti.b_user,--in
io_mem_0_ar_ready => msti.ar_ready,--in
io_mem_0_ar_valid => msto1.ar_valid,--out
io_mem_0_ar_bits_addr => msto1.ar_bits.addr,--out[31:0]
io_mem_0_ar_bits_len => msto1.ar_bits.len,--out[7:0]
io_mem_0_ar_bits_size => msto1.ar_bits.size,--out[2:0]
io_mem_0_ar_bits_burst => msto1.ar_bits.burst,--out[1:0]
io_mem_0_ar_bits_lock => msto1.ar_bits.lock,--out
io_mem_0_ar_bits_cache => msto1.ar_bits.cache,--out[3:0]
io_mem_0_ar_bits_prot => msto1.ar_bits.prot,--out[2:0]
io_mem_0_ar_bits_qos => msto1.ar_bits.qos,--out[3:0]
io_mem_0_ar_bits_region => msto1.ar_bits.region,--out[3:0]
io_mem_0_ar_bits_id => msto1.ar_id,--out[5:0]
io_mem_0_ar_bits_user => msto1.ar_user,--out
io_mem_0_r_ready => msto1.r_ready,--out
io_mem_0_r_valid => msti.r_valid,--in
io_mem_0_r_bits_resp => msti.r_resp,--in[1:0]
io_mem_0_r_bits_data => msti.r_data,--in[127:0]
io_mem_0_r_bits_last => msti.r_last,--in
io_mem_0_r_bits_id => msti.r_id,--in[5:0]
io_mem_0_r_bits_user => msti.r_user,--in
--! mmio
io_mmio_aw_ready => msti.aw_ready,--in
io_mmio_aw_valid => msto2.aw_valid,--out
io_mmio_aw_bits_addr => msto2.aw_bits.addr,--out[31:0]
io_mmio_aw_bits_len => msto2.aw_bits.len,--out[7:0]
io_mmio_aw_bits_size => msto2.aw_bits.size,--out[2:0]
io_mmio_aw_bits_burst => msto2.aw_bits.burst,--out[1:0]
io_mmio_aw_bits_lock => msto2.aw_bits.lock,--out
io_mmio_aw_bits_cache => msto2.aw_bits.cache,--out[3:0]
io_mmio_aw_bits_prot => msto2.aw_bits.prot,--out[2:0]
io_mmio_aw_bits_qos => msto2.aw_bits.qos,--out[3:0]
io_mmio_aw_bits_region => msto2.aw_bits.region,--out[3:0]
io_mmio_aw_bits_id => msto2.aw_id,--out[5:0]
io_mmio_aw_bits_user => msto2.aw_user,--out
io_mmio_w_ready => msti.w_ready,--in
io_mmio_w_valid => msto2.w_valid,--out
io_mmio_w_bits_data => msto2.w_data,--out[127:0]
io_mmio_w_bits_last => msto2.w_last,--out
io_mmio_w_bits_strb => msto2.w_strb,--out[15:0]
io_mmio_w_bits_user => msto2.w_user,--out
io_mmio_b_ready => msto2.b_ready,--out
io_mmio_b_valid => msti.b_valid,--in
io_mmio_b_bits_resp => msti.b_resp,--in[1:0]
io_mmio_b_bits_id => msti.b_id,--in[5:0]
io_mmio_b_bits_user => msti.b_user,--in
io_mmio_ar_ready => msti.ar_ready,--in
io_mmio_ar_valid => msto2.ar_valid,--out
io_mmio_ar_bits_addr => msto2.ar_bits.addr,--out[31:0]
io_mmio_ar_bits_len => msto2.ar_bits.len,--out[7:0]
io_mmio_ar_bits_size => msto2.ar_bits.size,--out[2:0]
io_mmio_ar_bits_burst => msto2.ar_bits.burst,--out[1:0]
io_mmio_ar_bits_lock => msto2.ar_bits.lock,--out
io_mmio_ar_bits_cache => msto2.ar_bits.cache,--out[3:0]
io_mmio_ar_bits_prot => msto2.ar_bits.prot,--out[2:0]
io_mmio_ar_bits_qos => msto2.ar_bits.qos,--out[3:0]
io_mmio_ar_bits_region => msto2.ar_bits.region,--out[3:0]
io_mmio_ar_bits_id => msto2.ar_id,--out[5:0]
io_mmio_ar_bits_user => msto2.ar_user,--out
io_mmio_r_ready => msto2.r_ready,--out
io_mmio_r_valid => msti.r_valid,--in
io_mmio_r_bits_resp => msti.r_resp,--in[1:0]
io_mmio_r_bits_data => msti.r_data,--in[127:0]
io_mmio_r_bits_last => msti.r_last,--in
io_mmio_r_bits_id => msti.r_id,--in[5:0]
io_mmio_r_bits_user => msti.r_user--in
);
end arch_rocket_l2cache;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc947.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00947ent IS
END c06s01b00x00p10n01i00947ent;
ARCHITECTURE c06s01b00x00p10n01i00947arch OF c06s01b00x00p10n01i00947ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R1'(RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00947 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00947arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc947.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00947ent IS
END c06s01b00x00p10n01i00947ent;
ARCHITECTURE c06s01b00x00p10n01i00947arch OF c06s01b00x00p10n01i00947ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R1'(RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00947 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00947arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc947.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00947ent IS
END c06s01b00x00p10n01i00947ent;
ARCHITECTURE c06s01b00x00p10n01i00947arch OF c06s01b00x00p10n01i00947ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R1'(RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00947 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00947arch;
|
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
elsif b = '0' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
else generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
elsif b = '0' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
else generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
end;
|
library ieee;
library ieee;
|
---------------------------------------------------------------------------------------------------
-- TinyBasic ROM image as listed in MPM-203 "Evaluation Kit Manual for the RCA CDP1802"
-- Author: Tom Pittman
-- TinyBasic interpreter Copyright 1976 Itty Bitty Computers, used by permission
-- http://www.ittybittycomputers.com/IttyBitty/TinyBasic/
-- http://www.retrotechnology.com/memship/mship_tbasic.html
---------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tiny_basic is
port(
clock: in std_logic;
cs_n: in std_logic;
rd_n: in std_logic;
address: in std_logic_vector(10 downto 0);
data_out: out std_logic_vector(7 downto 0));
end tiny_basic;
architecture rtl of tiny_basic is
type rom_type is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom : rom_type := (
(X"01"),(X"30"),(X"B0"),(X"C0"),(X"00"),(X"ED"),(X"C0"),(X"06"),
(X"6F"),(X"C0"),(X"06"),(X"76"),(X"C0"),(X"06"),(X"66"),(X"5F"),
(X"18"),(X"82"),(X"80"),(X"20"),(X"30"),(X"22"),(X"30"),(X"20"),
(X"58"),(X"D5"),(X"06"),(X"81"),(X"08"),(X"C8"),(X"00"),(X"08"),
(X"48"),(X"38"),(X"97"),(X"BA"),(X"48"),(X"D5"),(X"C0"),(X"06"),
(X"51"),(X"D3"),(X"BF"),(X"E2"),(X"86"),(X"73"),(X"96"),(X"73"),
(X"83"),(X"A6"),(X"93"),(X"B6"),(X"46"),(X"B3"),(X"46"),(X"A3"),
(X"9F"),(X"30"),(X"29"),(X"D3"),(X"BF"),(X"E2"),(X"96"),(X"B3"),
(X"86"),(X"A3"),(X"12"),(X"42"),(X"B6"),(X"02"),(X"A6"),(X"9F"),
(X"30"),(X"3B"),(X"D3"),(X"43"),(X"AD"),(X"F8"),(X"08"),(X"BD"),
(X"4D"),(X"ED"),(X"30"),(X"4A"),(X"01"),(X"98"),(X"01"),(X"A0"),
(X"02"),(X"1F"),(X"01"),(X"DD"),(X"01"),(X"F0"),(X"01"),(X"D4"),
(X"04"),(X"81"),(X"02"),(X"49"),(X"00"),(X"ED"),(X"04"),(X"4E"),
(X"01"),(X"04"),(X"05"),(X"A2"),(X"01"),(X"D3"),(X"01"),(X"D3"),
(X"04"),(X"AA"),(X"01"),(X"D3"),(X"01"),(X"D3"),(X"02"),(X"C5"),
(X"02"),(X"D5"),(X"03"),(X"03"),(X"02"),(X"79"),(X"03"),(X"18"),
(X"05"),(X"3C"),(X"01"),(X"D3"),(X"04"),(X"29"),(X"03"),(X"6C"),
(X"03"),(X"CB"),(X"03"),(X"A7"),(X"03"),(X"98"),(X"03"),(X"9B"),
(X"04"),(X"0E"),(X"04"),(X"60"),(X"04"),(X"6D"),(X"05"),(X"81"),
(X"01"),(X"B6"),(X"02"),(X"67"),(X"03"),(X"48"),(X"03"),(X"4B"),
(X"01"),(X"D3"),(X"01"),(X"D3"),(X"01"),(X"C9"),(X"01"),(X"C5"),
(X"02"),(X"4E"),(X"02"),(X"44"),(X"02"),(X"41"),(X"01"),(X"D3"),
(X"F8"),(X"B3"),(X"A3"),(X"F8"),(X"00"),(X"B3"),(X"D3"),(X"BA"),
(X"F8"),(X"1C"),(X"AA"),(X"4A"),(X"B2"),(X"4A"),(X"A2"),(X"4A"),
(X"BD"),(X"F8"),(X"00"),(X"AD"),(X"0D"),(X"BF"),(X"E2"),(X"12"),
(X"F0"),(X"AF"),(X"FB"),(X"FF"),(X"52"),(X"F3"),(X"ED"),(X"C6"),
(X"9F"),(X"F3"),(X"FC"),(X"FF"),(X"8F"),(X"52"),(X"3B"),(X"C6"),
(X"22"),(X"0A"),(X"BD"),(X"F8"),(X"23"),(X"AD"),(X"82"),(X"73"),
(X"92"),(X"73"),(X"2A"),(X"2A"),(X"0A"),(X"73"),(X"8D"),(X"FB"),
(X"12"),(X"3A"),(X"E3"),(X"F6"),(X"C8"),(X"FF"),(X"00"),(X"F8"),
(X"F2"),(X"A3"),(X"F8"),(X"00"),(X"B3"),(X"D3"),(X"B4"),(X"B5"),
(X"B7"),(X"F8"),(X"2A"),(X"A4"),(X"F8"),(X"3C"),(X"A5"),(X"F8"),
(X"4B"),(X"A7"),(X"33"),(X"1A"),(X"D7"),(X"20"),(X"BB"),(X"4D"),
(X"AB"),(X"97"),(X"5B"),(X"1B"),(X"5B"),(X"D7"),(X"16"),(X"8B"),
(X"F4"),(X"BF"),(X"D7"),(X"24"),(X"9F"),(X"73"),(X"9B"),(X"7C"),
(X"00"),(X"73"),(X"D7"),(X"22"),(X"B2"),(X"4D"),(X"A2"),(X"D7"),
(X"26"),(X"82"),(X"73"),(X"92"),(X"73"),(X"D4"),(X"02"),(X"CC"),
(X"D7"),(X"1E"),(X"B9"),(X"4D"),(X"A9"),(X"E2"),(X"49"),(X"FF"),
(X"30"),(X"33"),(X"4B"),(X"FD"),(X"D7"),(X"33"),(X"85"),(X"FE"),
(X"FC"),(X"B0"),(X"A6"),(X"F8"),(X"2D"),(X"22"),(X"22"),(X"73"),
(X"93"),(X"73"),(X"97"),(X"B6"),(X"46"),(X"52"),(X"46"),(X"A6"),
(X"F0"),(X"B6"),(X"D5"),(X"FF"),(X"10"),(X"3B"),(X"6A"),(X"A6"),
(X"FA"),(X"1F"),(X"32"),(X"5C"),(X"52"),(X"89"),(X"F4"),(X"73"),
(X"99"),(X"7C"),(X"00"),(X"38"),(X"73"),(X"73"),(X"86"),(X"F6"),
(X"F6"),(X"F6"),(X"F6"),(X"FA"),(X"FE"),(X"FC"),(X"54"),(X"A6"),
(X"30"),(X"42"),(X"FC"),(X"08"),(X"FA"),(X"07"),(X"B6"),(X"49"),
(X"A6"),(X"33"),(X"7A"),(X"89"),(X"73"),(X"99"),(X"73"),(X"D4"),
(X"02"),(X"37"),(X"D7"),(X"1E"),(X"86"),(X"F4"),(X"A9"),(X"96"),
(X"2D"),(X"74"),(X"B9"),(X"30"),(X"2D"),(X"FD"),(X"07"),(X"52"),
(X"D7"),(X"1A"),(X"AD"),(X"E2"),(X"F4"),(X"A6"),(X"9D"),(X"B6"),
(X"0D"),(X"52"),(X"06"),(X"5D"),(X"02"),(X"56"),(X"30"),(X"2D"),
(X"86"),(X"FF"),(X"20"),(X"A6"),(X"96"),(X"7F"),(X"00"),(X"38"),
(X"96"),(X"C2"),(X"02"),(X"7F"),(X"B9"),(X"86"),(X"A9"),(X"30"),
(X"2D"),(X"1B"),(X"0B"),(X"FF"),(X"20"),(X"32"),(X"A9"),(X"FF"),
(X"10"),(X"C7"),(X"FD"),(X"09"),(X"0B"),(X"D5"),(X"D4"),(X"01"),
(X"C5"),(X"4D"),(X"AD"),(X"9A"),(X"5D"),(X"1D"),(X"8A"),(X"5D"),
(X"30"),(X"C9"),(X"D4"),(X"01"),(X"C5"),(X"D4"),(X"01"),(X"C9"),
(X"BA"),(X"D7"),(X"1A"),(X"2D"),(X"FC"),(X"01"),(X"5D"),(X"AD"),
(X"2D"),(X"4D"),(X"AA"),(X"D5"),(X"D4"),(X"01"),(X"AA"),(X"FB"),
(X"0D"),(X"32"),(X"2D"),(X"30"),(X"A0"),(X"D4"),(X"01"),(X"AA"),
(X"FF"),(X"41"),(X"3B"),(X"A0"),(X"FF"),(X"1A"),(X"33"),(X"A0"),
(X"1B"),(X"9F"),(X"FE"),(X"D4"),(X"02"),(X"59"),(X"30"),(X"2D"),
(X"D4"),(X"01"),(X"AA"),(X"3B"),(X"A0"),(X"97"),(X"BA"),(X"AA"),
(X"D4"),(X"02"),(X"54"),(X"4B"),(X"FA"),(X"0F"),(X"AA"),(X"97"),
(X"BA"),(X"F8"),(X"0A"),(X"AF"),(X"ED"),(X"1D"),(X"8A"),(X"F4"),
(X"AA"),(X"9A"),(X"2D"),(X"74"),(X"BA"),(X"2F"),(X"8F"),(X"3A"),
(X"05"),(X"9A"),(X"5D"),(X"1D"),(X"8A"),(X"73"),(X"D4"),(X"01"),
(X"AA"),(X"C3"),(X"01"),(X"FB"),(X"C0"),(X"01"),(X"2D"),(X"9B"),
(X"BA"),(X"8B"),(X"AA"),(X"D4"),(X"01"),(X"AA"),(X"1B"),(X"52"),
(X"49"),(X"F3"),(X"32"),(X"23"),(X"FB"),(X"80"),(X"32"),(X"1C"),
(X"9A"),(X"BB"),(X"8A"),(X"AB"),(X"C0"),(X"01"),(X"A0"),(X"D7"),
(X"24"),(X"82"),(X"F5"),(X"2D"),(X"92"),(X"75"),(X"33"),(X"7F"),
(X"D5"),(X"49"),(X"30"),(X"59"),(X"49"),(X"BA"),(X"49"),(X"30"),
(X"55"),(X"D4"),(X"05"),(X"25"),(X"30"),(X"55"),(X"D4"),(X"01"),
(X"C5"),(X"D4"),(X"02"),(X"54"),(X"8A"),(X"D4"),(X"02"),(X"59"),
(X"9A"),(X"52"),(X"D7"),(X"19"),(X"F7"),(X"33"),(X"7F"),(X"F8"),
(X"01"),(X"F5"),(X"5D"),(X"AD"),(X"02"),(X"5D"),(X"D5"),(X"D4"),
(X"01"),(X"C9"),(X"AD"),(X"4D"),(X"BA"),(X"4D"),(X"30"),(X"55"),
(X"FB"),(X"2F"),(X"32"),(X"66"),(X"FB"),(X"22"),(X"D4"),(X"02"),
(X"F4"),(X"4B"),(X"FB"),(X"0D"),(X"3A"),(X"70"),(X"29"),(X"D7"),
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begin
process(clock)
begin
if(rising_edge(clock))then
if(rd_n = '0' and cs_n = '0')then
data_out <= rom(to_integer(unsigned(address)));
else
data_out <= "00000000";
end if;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transferes registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
Port ( clk : in STD_LOGIC;
resend :in STD_LOGIC;
config_finished : out std_logic;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end ov7670_controller;
architecture Behavioral of ov7670_controller is
COMPONENT ov7670_registers
PORT(
clk : IN std_logic;
advance : IN std_logic;
resend : in STD_LOGIC;
command : OUT std_logic_vector(15 downto 0);
finished : OUT std_logic
);
END COMPONENT;
COMPONENT i2c_sender
PORT(
clk : IN std_logic;
send : IN std_logic;
taken : out std_logic;
id : IN std_logic_vector(7 downto 0);
reg : IN std_logic_vector(7 downto 0);
value : IN std_logic_vector(7 downto 0);
siod : INOUT std_logic;
sioc : OUT std_logic
);
END COMPONENT;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers PORT MAP(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transferes registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
Port ( clk : in STD_LOGIC;
resend :in STD_LOGIC;
config_finished : out std_logic;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end ov7670_controller;
architecture Behavioral of ov7670_controller is
COMPONENT ov7670_registers
PORT(
clk : IN std_logic;
advance : IN std_logic;
resend : in STD_LOGIC;
command : OUT std_logic_vector(15 downto 0);
finished : OUT std_logic
);
END COMPONENT;
COMPONENT i2c_sender
PORT(
clk : IN std_logic;
send : IN std_logic;
taken : out std_logic;
id : IN std_logic_vector(7 downto 0);
reg : IN std_logic_vector(7 downto 0);
value : IN std_logic_vector(7 downto 0);
siod : INOUT std_logic;
sioc : OUT std_logic
);
END COMPONENT;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers PORT MAP(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transferes registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
Port ( clk : in STD_LOGIC;
resend :in STD_LOGIC;
config_finished : out std_logic;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end ov7670_controller;
architecture Behavioral of ov7670_controller is
COMPONENT ov7670_registers
PORT(
clk : IN std_logic;
advance : IN std_logic;
resend : in STD_LOGIC;
command : OUT std_logic_vector(15 downto 0);
finished : OUT std_logic
);
END COMPONENT;
COMPONENT i2c_sender
PORT(
clk : IN std_logic;
send : IN std_logic;
taken : out std_logic;
id : IN std_logic_vector(7 downto 0);
reg : IN std_logic_vector(7 downto 0);
value : IN std_logic_vector(7 downto 0);
siod : INOUT std_logic;
sioc : OUT std_logic
);
END COMPONENT;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers PORT MAP(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1447.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01447ent IS
END c08s07b00x00p02n01i01447ent;
ARCHITECTURE c08s07b00x00p02n01i01447arch OF c08s07b00x00p02n01i01447ent IS
begin
transmit: process
procedure ARITH(z : out integer) is
begin
z := 5;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
if m > 5 then
ARITH(k);
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01447 - Procedure Call statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01447"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01447arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1447.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01447ent IS
END c08s07b00x00p02n01i01447ent;
ARCHITECTURE c08s07b00x00p02n01i01447arch OF c08s07b00x00p02n01i01447ent IS
begin
transmit: process
procedure ARITH(z : out integer) is
begin
z := 5;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
if m > 5 then
ARITH(k);
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01447 - Procedure Call statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01447"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01447arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1447.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01447ent IS
END c08s07b00x00p02n01i01447ent;
ARCHITECTURE c08s07b00x00p02n01i01447arch OF c08s07b00x00p02n01i01447ent IS
begin
transmit: process
procedure ARITH(z : out integer) is
begin
z := 5;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
if m > 5 then
ARITH(k);
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01447 - Procedure Call statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01447"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01447arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FIFO_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity FIFO_exdes is
PORT (
S_ARESETN : IN std_logic;
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic;
M_ACLK : IN std_logic;
S_ACLK : IN std_logic);
end FIFO_exdes;
architecture xilinx of FIFO_exdes is
signal s_aclk_i : std_logic;
signal m_aclk_i : std_logic;
component FIFO is
PORT (
S_ARESETN : IN std_logic;
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic;
M_ACLK : IN std_logic;
S_ACLK : IN std_logic);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => S_ACLK,
o => s_aclk_i
);
m_aclk_buf: bufg
PORT map(
i => M_ACLK,
o => m_aclk_i
);
exdes_inst : FIFO
PORT MAP (
S_ARESETN => s_aresetn,
M_AXIS_TVALID => m_axis_tvalid,
M_AXIS_TREADY => m_axis_tready,
M_AXIS_TDATA => m_axis_tdata,
M_AXIS_TKEEP => m_axis_tkeep,
M_AXIS_TLAST => m_axis_tlast,
S_AXIS_TVALID => s_axis_tvalid,
S_AXIS_TREADY => s_axis_tready,
S_AXIS_TDATA => s_axis_tdata,
S_AXIS_TKEEP => s_axis_tkeep,
S_AXIS_TLAST => s_axis_tlast,
AXIS_OVERFLOW => axis_overflow,
AXIS_UNDERFLOW => axis_underflow,
M_ACLK => m_aclk_i,
S_ACLK => s_aclk_i);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_bank is
port(clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
rd_ack : out std_logic;
addr : in std_logic_vector(15 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd_data : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of mem_bank is
type reg_array is array (4 downto 0) of std_logic_vector(31 downto 0);
function init_reg_array return reg_array is
variable result : reg_array;
begin
result(0) := x"01234567";
result(1) := x"89abcde7";
result(2) := x"0a0b0c0d";
result(3) := x"10203040";
result(4) := x"deadbeef";
return result;
end init_reg_array;
signal mem_bank : reg_array := init_reg_array;
signal true_addr : std_logic_vector(15 downto 0);
signal addr_valid : std_logic;
begin
with addr select
true_addr <= x"0000" when x"0000",
x"0001" when x"0001",
x"0002" when x"0002",
x"0003" when x"0003",
x"0004" when x"00e7",
x"8000" when others;
addr_valid <= not true_addr(15);
process (clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
rd_ack <= '0';
rd_data <= (others => '0');
mem_bank <= init_reg_array;
elsif (wr_en = '1' and addr_valid = '1') then
rd_ack <= '0';
rd_data <= (others => '0');
mem_bank(to_integer(unsigned(true_addr))) <= wr_data;
elsif (rd_en = '1' and addr_valid = '1') then
rd_ack <= '1';
rd_data <= mem_bank(to_integer(unsigned(true_addr)));
else
rd_ack <= '0';
rd_data <= (others => '0');
end if;
end if;
end process;
end architecture rtl; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:05:36 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Segundoprocesador/TbWindownmanager.vhd
-- Project Name: Segundoprocesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: WindowsManager
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbWindownmanager IS
END TbWindownmanager;
ARCHITECTURE behavior OF TbWindownmanager IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT WindowsManager
PORT(
cwp : IN std_logic;
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
cwpout : OUT std_logic;
rs1out : OUT std_logic_vector(5 downto 0);
rs2out : OUT std_logic_vector(5 downto 0);
rdout : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal cwp : std_logic := '0';
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal cwpout : std_logic;
signal rs1out : std_logic_vector(5 downto 0);
signal rs2out : std_logic_vector(5 downto 0);
signal rdout : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: WindowsManager PORT MAP (
cwp => cwp,
rs1 => rs1,
rs2 => rs2,
rd => rd,
op => op,
op3 => op3,
cwpout => cwpout,
rs1out => rs1out,
rs2out => rs2out,
rdout => rdout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 50 ns;
cwp <= '0';
rs1 <= "00000";
rs2 <= "00000";
rd <= "00000";
op <= "00";
op3 <= "000000";
wait for 50 ns;
cwp <= '0';
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
op <= "10";
op3 <= "000000";
wait for 50 ns;
cwp <= '1';
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
op <= "10";
op3 <= "111100";
wait for 50 ns;
cwp <= '1';
rs1 <= "01100";
rs2 <= "01101";
rd <= "00000";
op <= "00";
op3 <= "000000";
wait for 50 ns;
cwp <= '1';
rs1 <= "11000";
rs2 <= "11001";
rd <= "10010";
op <= "10";
op3 <= "000000";
wait for 50 ns;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:05:36 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Segundoprocesador/TbWindownmanager.vhd
-- Project Name: Segundoprocesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: WindowsManager
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbWindownmanager IS
END TbWindownmanager;
ARCHITECTURE behavior OF TbWindownmanager IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT WindowsManager
PORT(
cwp : IN std_logic;
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
cwpout : OUT std_logic;
rs1out : OUT std_logic_vector(5 downto 0);
rs2out : OUT std_logic_vector(5 downto 0);
rdout : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal cwp : std_logic := '0';
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal cwpout : std_logic;
signal rs1out : std_logic_vector(5 downto 0);
signal rs2out : std_logic_vector(5 downto 0);
signal rdout : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: WindowsManager PORT MAP (
cwp => cwp,
rs1 => rs1,
rs2 => rs2,
rd => rd,
op => op,
op3 => op3,
cwpout => cwpout,
rs1out => rs1out,
rs2out => rs2out,
rdout => rdout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 50 ns;
cwp <= '0';
rs1 <= "00000";
rs2 <= "00000";
rd <= "00000";
op <= "00";
op3 <= "000000";
wait for 50 ns;
cwp <= '0';
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
op <= "10";
op3 <= "000000";
wait for 50 ns;
cwp <= '1';
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
op <= "10";
op3 <= "111100";
wait for 50 ns;
cwp <= '1';
rs1 <= "01100";
rs2 <= "01101";
rd <= "00000";
op <= "00";
op3 <= "000000";
wait for 50 ns;
cwp <= '1';
rs1 <= "11000";
rs2 <= "11001";
rd <= "10010";
op <= "10";
op3 <= "000000";
wait for 50 ns;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: Pass-through filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter passes the video signals from input to output.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Pass-through architecture
architecture Behavioral of Video_Box is
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
---- Number of Slave Registers 512
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg40 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg41 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg42 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg43 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg44 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg45 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg46 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg47 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg48 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg49 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg50 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg51 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg52 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg53 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg54 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg55 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg56 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg57 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg58 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg59 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg60 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg61 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg62 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg63 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg64 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg65 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg66 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg67 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg68 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg69 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg70 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg71 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg72 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg73 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg74 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg75 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg76 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg77 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg78 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg79 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg80 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg81 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg82 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg83 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg84 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg85 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg86 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg87 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg88 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg89 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg90 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg91 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg92 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg93 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg94 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg95 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg96 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg97 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg98 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg99 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg100 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg101 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg102 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg103 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg104 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg105 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg106 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg107 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg108 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg109 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg110 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg111 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg112 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg113 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg114 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg115 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg116 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg117 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg118 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg119 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg120 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg121 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg122 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg123 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg124 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg125 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg126 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg127 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg128 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg129 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg130 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg131 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg132 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg133 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg134 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg135 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg136 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg137 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg138 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg139 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg140 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg141 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg142 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg143 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg144 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg145 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg146 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg147 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg148 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg149 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg150 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg151 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg152 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg153 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg154 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg155 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg156 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg157 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg158 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg159 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg160 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg161 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg162 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg163 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg164 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg165 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg166 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg167 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg168 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg169 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg170 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg171 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg172 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg173 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg174 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg175 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg176 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg177 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg178 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg179 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg180 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg181 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg182 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg183 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg184 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg185 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg186 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg187 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg188 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg189 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg190 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg191 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg192 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg193 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg194 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg195 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg196 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg197 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg198 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg199 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg200 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg201 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg202 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg203 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg204 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg205 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg206 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg207 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg208 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg209 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg210 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg211 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg212 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg213 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg214 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg215 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg216 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg217 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg218 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg219 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg220 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg221 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg222 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg223 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg224 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg225 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg226 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg227 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg228 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg229 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg230 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg231 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg232 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg233 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg234 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg235 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg236 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg237 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg238 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg239 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg240 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg241 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg242 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg243 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg244 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg245 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg246 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg247 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg248 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg249 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg250 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg251 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg252 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg253 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg254 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg255 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg256 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg257 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg258 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg259 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg260 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg261 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg262 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg263 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg264 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg265 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg266 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg267 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg268 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg269 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg270 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg271 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg272 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg273 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg274 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg275 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg276 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg277 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg278 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg279 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg280 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg281 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg282 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg283 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg284 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg285 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg286 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg287 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg288 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg289 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg290 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg291 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg292 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg293 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg294 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg295 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg296 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg297 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg298 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg299 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg300 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg301 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg302 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg303 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg304 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg305 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg306 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg307 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg308 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg309 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg310 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg311 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg312 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg313 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg314 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg315 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg316 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg317 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg318 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg319 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg320 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg321 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg322 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg323 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg324 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg325 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg326 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg327 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg328 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg329 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg330 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg331 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg332 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg333 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg334 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg335 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg336 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg337 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg338 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg339 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg340 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg341 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg342 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg343 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg344 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg345 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg346 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg347 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg348 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg349 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg350 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg351 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg352 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg353 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg354 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg355 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg356 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg357 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg358 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg359 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg360 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg361 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg362 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg363 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg364 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg365 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg366 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg367 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg368 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg369 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg370 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg371 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg372 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg373 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg374 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg375 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg376 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg377 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg378 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg379 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg380 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg381 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg382 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg383 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg384 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg385 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg386 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg387 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg388 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg389 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg390 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg391 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg392 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg393 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg394 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg395 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg396 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg397 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg398 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg399 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg400 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg401 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg402 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg403 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg404 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg405 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg406 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg407 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg408 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg409 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg410 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg411 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg412 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg413 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg414 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg415 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg416 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg417 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg418 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg419 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg420 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg421 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg422 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg423 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg424 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg425 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg426 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg427 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg428 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg429 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg430 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg431 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg432 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg433 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg434 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg435 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg436 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg437 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg438 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg439 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg440 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg441 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg442 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg443 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg444 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg445 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg446 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg447 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg448 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg449 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg450 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg451 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg452 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg453 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg454 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg455 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg456 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg457 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg458 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg459 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg460 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg461 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg462 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg463 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg464 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg465 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg466 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg467 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg468 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg469 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg470 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg471 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg472 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg473 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg474 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg475 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg476 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg477 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg478 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg479 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg480 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg481 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg482 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg483 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg484 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg485 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg486 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg487 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg488 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg489 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg490 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg491 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg492 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg493 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg494 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg495 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg496 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg497 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg498 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg499 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg500 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg501 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg502 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg503 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg504 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg505 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg506 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg507 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg508 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg509 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg510 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg511 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--the user can edit the rgb values here
USER_LOGIC <= RGB_IN_reg;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
slv_reg40 <= (others => '0');
slv_reg41 <= (others => '0');
slv_reg42 <= (others => '0');
slv_reg43 <= (others => '0');
slv_reg44 <= (others => '0');
slv_reg45 <= (others => '0');
slv_reg46 <= (others => '0');
slv_reg47 <= (others => '0');
slv_reg48 <= (others => '0');
slv_reg49 <= (others => '0');
slv_reg50 <= (others => '0');
slv_reg51 <= (others => '0');
slv_reg52 <= (others => '0');
slv_reg53 <= (others => '0');
slv_reg54 <= (others => '0');
slv_reg55 <= (others => '0');
slv_reg56 <= (others => '0');
slv_reg57 <= (others => '0');
slv_reg58 <= (others => '0');
slv_reg59 <= (others => '0');
slv_reg60 <= (others => '0');
slv_reg61 <= (others => '0');
slv_reg62 <= (others => '0');
slv_reg63 <= (others => '0');
slv_reg64 <= (others => '0');
slv_reg65 <= (others => '0');
slv_reg66 <= (others => '0');
slv_reg67 <= (others => '0');
slv_reg68 <= (others => '0');
slv_reg69 <= (others => '0');
slv_reg70 <= (others => '0');
slv_reg71 <= (others => '0');
slv_reg72 <= (others => '0');
slv_reg73 <= (others => '0');
slv_reg74 <= (others => '0');
slv_reg75 <= (others => '0');
slv_reg76 <= (others => '0');
slv_reg77 <= (others => '0');
slv_reg78 <= (others => '0');
slv_reg79 <= (others => '0');
slv_reg80 <= (others => '0');
slv_reg81 <= (others => '0');
slv_reg82 <= (others => '0');
slv_reg83 <= (others => '0');
slv_reg84 <= (others => '0');
slv_reg85 <= (others => '0');
slv_reg86 <= (others => '0');
slv_reg87 <= (others => '0');
slv_reg88 <= (others => '0');
slv_reg89 <= (others => '0');
slv_reg90 <= (others => '0');
slv_reg91 <= (others => '0');
slv_reg92 <= (others => '0');
slv_reg93 <= (others => '0');
slv_reg94 <= (others => '0');
slv_reg95 <= (others => '0');
slv_reg96 <= (others => '0');
slv_reg97 <= (others => '0');
slv_reg98 <= (others => '0');
slv_reg99 <= (others => '0');
slv_reg100 <= (others => '0');
slv_reg101 <= (others => '0');
slv_reg102 <= (others => '0');
slv_reg103 <= (others => '0');
slv_reg104 <= (others => '0');
slv_reg105 <= (others => '0');
slv_reg106 <= (others => '0');
slv_reg107 <= (others => '0');
slv_reg108 <= (others => '0');
slv_reg109 <= (others => '0');
slv_reg110 <= (others => '0');
slv_reg111 <= (others => '0');
slv_reg112 <= (others => '0');
slv_reg113 <= (others => '0');
slv_reg114 <= (others => '0');
slv_reg115 <= (others => '0');
slv_reg116 <= (others => '0');
slv_reg117 <= (others => '0');
slv_reg118 <= (others => '0');
slv_reg119 <= (others => '0');
slv_reg120 <= (others => '0');
slv_reg121 <= (others => '0');
slv_reg122 <= (others => '0');
slv_reg123 <= (others => '0');
slv_reg124 <= (others => '0');
slv_reg125 <= (others => '0');
slv_reg126 <= (others => '0');
slv_reg127 <= (others => '0');
slv_reg128 <= (others => '0');
slv_reg129 <= (others => '0');
slv_reg130 <= (others => '0');
slv_reg131 <= (others => '0');
slv_reg132 <= (others => '0');
slv_reg133 <= (others => '0');
slv_reg134 <= (others => '0');
slv_reg135 <= (others => '0');
slv_reg136 <= (others => '0');
slv_reg137 <= (others => '0');
slv_reg138 <= (others => '0');
slv_reg139 <= (others => '0');
slv_reg140 <= (others => '0');
slv_reg141 <= (others => '0');
slv_reg142 <= (others => '0');
slv_reg143 <= (others => '0');
slv_reg144 <= (others => '0');
slv_reg145 <= (others => '0');
slv_reg146 <= (others => '0');
slv_reg147 <= (others => '0');
slv_reg148 <= (others => '0');
slv_reg149 <= (others => '0');
slv_reg150 <= (others => '0');
slv_reg151 <= (others => '0');
slv_reg152 <= (others => '0');
slv_reg153 <= (others => '0');
slv_reg154 <= (others => '0');
slv_reg155 <= (others => '0');
slv_reg156 <= (others => '0');
slv_reg157 <= (others => '0');
slv_reg158 <= (others => '0');
slv_reg159 <= (others => '0');
slv_reg160 <= (others => '0');
slv_reg161 <= (others => '0');
slv_reg162 <= (others => '0');
slv_reg163 <= (others => '0');
slv_reg164 <= (others => '0');
slv_reg165 <= (others => '0');
slv_reg166 <= (others => '0');
slv_reg167 <= (others => '0');
slv_reg168 <= (others => '0');
slv_reg169 <= (others => '0');
slv_reg170 <= (others => '0');
slv_reg171 <= (others => '0');
slv_reg172 <= (others => '0');
slv_reg173 <= (others => '0');
slv_reg174 <= (others => '0');
slv_reg175 <= (others => '0');
slv_reg176 <= (others => '0');
slv_reg177 <= (others => '0');
slv_reg178 <= (others => '0');
slv_reg179 <= (others => '0');
slv_reg180 <= (others => '0');
slv_reg181 <= (others => '0');
slv_reg182 <= (others => '0');
slv_reg183 <= (others => '0');
slv_reg184 <= (others => '0');
slv_reg185 <= (others => '0');
slv_reg186 <= (others => '0');
slv_reg187 <= (others => '0');
slv_reg188 <= (others => '0');
slv_reg189 <= (others => '0');
slv_reg190 <= (others => '0');
slv_reg191 <= (others => '0');
slv_reg192 <= (others => '0');
slv_reg193 <= (others => '0');
slv_reg194 <= (others => '0');
slv_reg195 <= (others => '0');
slv_reg196 <= (others => '0');
slv_reg197 <= (others => '0');
slv_reg198 <= (others => '0');
slv_reg199 <= (others => '0');
slv_reg200 <= (others => '0');
slv_reg201 <= (others => '0');
slv_reg202 <= (others => '0');
slv_reg203 <= (others => '0');
slv_reg204 <= (others => '0');
slv_reg205 <= (others => '0');
slv_reg206 <= (others => '0');
slv_reg207 <= (others => '0');
slv_reg208 <= (others => '0');
slv_reg209 <= (others => '0');
slv_reg210 <= (others => '0');
slv_reg211 <= (others => '0');
slv_reg212 <= (others => '0');
slv_reg213 <= (others => '0');
slv_reg214 <= (others => '0');
slv_reg215 <= (others => '0');
slv_reg216 <= (others => '0');
slv_reg217 <= (others => '0');
slv_reg218 <= (others => '0');
slv_reg219 <= (others => '0');
slv_reg220 <= (others => '0');
slv_reg221 <= (others => '0');
slv_reg222 <= (others => '0');
slv_reg223 <= (others => '0');
slv_reg224 <= (others => '0');
slv_reg225 <= (others => '0');
slv_reg226 <= (others => '0');
slv_reg227 <= (others => '0');
slv_reg228 <= (others => '0');
slv_reg229 <= (others => '0');
slv_reg230 <= (others => '0');
slv_reg231 <= (others => '0');
slv_reg232 <= (others => '0');
slv_reg233 <= (others => '0');
slv_reg234 <= (others => '0');
slv_reg235 <= (others => '0');
slv_reg236 <= (others => '0');
slv_reg237 <= (others => '0');
slv_reg238 <= (others => '0');
slv_reg239 <= (others => '0');
slv_reg240 <= (others => '0');
slv_reg241 <= (others => '0');
slv_reg242 <= (others => '0');
slv_reg243 <= (others => '0');
slv_reg244 <= (others => '0');
slv_reg245 <= (others => '0');
slv_reg246 <= (others => '0');
slv_reg247 <= (others => '0');
slv_reg248 <= (others => '0');
slv_reg249 <= (others => '0');
slv_reg250 <= (others => '0');
slv_reg251 <= (others => '0');
slv_reg252 <= (others => '0');
slv_reg253 <= (others => '0');
slv_reg254 <= (others => '0');
slv_reg255 <= (others => '0');
slv_reg256 <= (others => '0');
slv_reg257 <= (others => '0');
slv_reg258 <= (others => '0');
slv_reg259 <= (others => '0');
slv_reg260 <= (others => '0');
slv_reg261 <= (others => '0');
slv_reg262 <= (others => '0');
slv_reg263 <= (others => '0');
slv_reg264 <= (others => '0');
slv_reg265 <= (others => '0');
slv_reg266 <= (others => '0');
slv_reg267 <= (others => '0');
slv_reg268 <= (others => '0');
slv_reg269 <= (others => '0');
slv_reg270 <= (others => '0');
slv_reg271 <= (others => '0');
slv_reg272 <= (others => '0');
slv_reg273 <= (others => '0');
slv_reg274 <= (others => '0');
slv_reg275 <= (others => '0');
slv_reg276 <= (others => '0');
slv_reg277 <= (others => '0');
slv_reg278 <= (others => '0');
slv_reg279 <= (others => '0');
slv_reg280 <= (others => '0');
slv_reg281 <= (others => '0');
slv_reg282 <= (others => '0');
slv_reg283 <= (others => '0');
slv_reg284 <= (others => '0');
slv_reg285 <= (others => '0');
slv_reg286 <= (others => '0');
slv_reg287 <= (others => '0');
slv_reg288 <= (others => '0');
slv_reg289 <= (others => '0');
slv_reg290 <= (others => '0');
slv_reg291 <= (others => '0');
slv_reg292 <= (others => '0');
slv_reg293 <= (others => '0');
slv_reg294 <= (others => '0');
slv_reg295 <= (others => '0');
slv_reg296 <= (others => '0');
slv_reg297 <= (others => '0');
slv_reg298 <= (others => '0');
slv_reg299 <= (others => '0');
slv_reg300 <= (others => '0');
slv_reg301 <= (others => '0');
slv_reg302 <= (others => '0');
slv_reg303 <= (others => '0');
slv_reg304 <= (others => '0');
slv_reg305 <= (others => '0');
slv_reg306 <= (others => '0');
slv_reg307 <= (others => '0');
slv_reg308 <= (others => '0');
slv_reg309 <= (others => '0');
slv_reg310 <= (others => '0');
slv_reg311 <= (others => '0');
slv_reg312 <= (others => '0');
slv_reg313 <= (others => '0');
slv_reg314 <= (others => '0');
slv_reg315 <= (others => '0');
slv_reg316 <= (others => '0');
slv_reg317 <= (others => '0');
slv_reg318 <= (others => '0');
slv_reg319 <= (others => '0');
slv_reg320 <= (others => '0');
slv_reg321 <= (others => '0');
slv_reg322 <= (others => '0');
slv_reg323 <= (others => '0');
slv_reg324 <= (others => '0');
slv_reg325 <= (others => '0');
slv_reg326 <= (others => '0');
slv_reg327 <= (others => '0');
slv_reg328 <= (others => '0');
slv_reg329 <= (others => '0');
slv_reg330 <= (others => '0');
slv_reg331 <= (others => '0');
slv_reg332 <= (others => '0');
slv_reg333 <= (others => '0');
slv_reg334 <= (others => '0');
slv_reg335 <= (others => '0');
slv_reg336 <= (others => '0');
slv_reg337 <= (others => '0');
slv_reg338 <= (others => '0');
slv_reg339 <= (others => '0');
slv_reg340 <= (others => '0');
slv_reg341 <= (others => '0');
slv_reg342 <= (others => '0');
slv_reg343 <= (others => '0');
slv_reg344 <= (others => '0');
slv_reg345 <= (others => '0');
slv_reg346 <= (others => '0');
slv_reg347 <= (others => '0');
slv_reg348 <= (others => '0');
slv_reg349 <= (others => '0');
slv_reg350 <= (others => '0');
slv_reg351 <= (others => '0');
slv_reg352 <= (others => '0');
slv_reg353 <= (others => '0');
slv_reg354 <= (others => '0');
slv_reg355 <= (others => '0');
slv_reg356 <= (others => '0');
slv_reg357 <= (others => '0');
slv_reg358 <= (others => '0');
slv_reg359 <= (others => '0');
slv_reg360 <= (others => '0');
slv_reg361 <= (others => '0');
slv_reg362 <= (others => '0');
slv_reg363 <= (others => '0');
slv_reg364 <= (others => '0');
slv_reg365 <= (others => '0');
slv_reg366 <= (others => '0');
slv_reg367 <= (others => '0');
slv_reg368 <= (others => '0');
slv_reg369 <= (others => '0');
slv_reg370 <= (others => '0');
slv_reg371 <= (others => '0');
slv_reg372 <= (others => '0');
slv_reg373 <= (others => '0');
slv_reg374 <= (others => '0');
slv_reg375 <= (others => '0');
slv_reg376 <= (others => '0');
slv_reg377 <= (others => '0');
slv_reg378 <= (others => '0');
slv_reg379 <= (others => '0');
slv_reg380 <= (others => '0');
slv_reg381 <= (others => '0');
slv_reg382 <= (others => '0');
slv_reg383 <= (others => '0');
slv_reg384 <= (others => '0');
slv_reg385 <= (others => '0');
slv_reg386 <= (others => '0');
slv_reg387 <= (others => '0');
slv_reg388 <= (others => '0');
slv_reg389 <= (others => '0');
slv_reg390 <= (others => '0');
slv_reg391 <= (others => '0');
slv_reg392 <= (others => '0');
slv_reg393 <= (others => '0');
slv_reg394 <= (others => '0');
slv_reg395 <= (others => '0');
slv_reg396 <= (others => '0');
slv_reg397 <= (others => '0');
slv_reg398 <= (others => '0');
slv_reg399 <= (others => '0');
slv_reg400 <= (others => '0');
slv_reg401 <= (others => '0');
slv_reg402 <= (others => '0');
slv_reg403 <= (others => '0');
slv_reg404 <= (others => '0');
slv_reg405 <= (others => '0');
slv_reg406 <= (others => '0');
slv_reg407 <= (others => '0');
slv_reg408 <= (others => '0');
slv_reg409 <= (others => '0');
slv_reg410 <= (others => '0');
slv_reg411 <= (others => '0');
slv_reg412 <= (others => '0');
slv_reg413 <= (others => '0');
slv_reg414 <= (others => '0');
slv_reg415 <= (others => '0');
slv_reg416 <= (others => '0');
slv_reg417 <= (others => '0');
slv_reg418 <= (others => '0');
slv_reg419 <= (others => '0');
slv_reg420 <= (others => '0');
slv_reg421 <= (others => '0');
slv_reg422 <= (others => '0');
slv_reg423 <= (others => '0');
slv_reg424 <= (others => '0');
slv_reg425 <= (others => '0');
slv_reg426 <= (others => '0');
slv_reg427 <= (others => '0');
slv_reg428 <= (others => '0');
slv_reg429 <= (others => '0');
slv_reg430 <= (others => '0');
slv_reg431 <= (others => '0');
slv_reg432 <= (others => '0');
slv_reg433 <= (others => '0');
slv_reg434 <= (others => '0');
slv_reg435 <= (others => '0');
slv_reg436 <= (others => '0');
slv_reg437 <= (others => '0');
slv_reg438 <= (others => '0');
slv_reg439 <= (others => '0');
slv_reg440 <= (others => '0');
slv_reg441 <= (others => '0');
slv_reg442 <= (others => '0');
slv_reg443 <= (others => '0');
slv_reg444 <= (others => '0');
slv_reg445 <= (others => '0');
slv_reg446 <= (others => '0');
slv_reg447 <= (others => '0');
slv_reg448 <= (others => '0');
slv_reg449 <= (others => '0');
slv_reg450 <= (others => '0');
slv_reg451 <= (others => '0');
slv_reg452 <= (others => '0');
slv_reg453 <= (others => '0');
slv_reg454 <= (others => '0');
slv_reg455 <= (others => '0');
slv_reg456 <= (others => '0');
slv_reg457 <= (others => '0');
slv_reg458 <= (others => '0');
slv_reg459 <= (others => '0');
slv_reg460 <= (others => '0');
slv_reg461 <= (others => '0');
slv_reg462 <= (others => '0');
slv_reg463 <= (others => '0');
slv_reg464 <= (others => '0');
slv_reg465 <= (others => '0');
slv_reg466 <= (others => '0');
slv_reg467 <= (others => '0');
slv_reg468 <= (others => '0');
slv_reg469 <= (others => '0');
slv_reg470 <= (others => '0');
slv_reg471 <= (others => '0');
slv_reg472 <= (others => '0');
slv_reg473 <= (others => '0');
slv_reg474 <= (others => '0');
slv_reg475 <= (others => '0');
slv_reg476 <= (others => '0');
slv_reg477 <= (others => '0');
slv_reg478 <= (others => '0');
slv_reg479 <= (others => '0');
slv_reg480 <= (others => '0');
slv_reg481 <= (others => '0');
slv_reg482 <= (others => '0');
slv_reg483 <= (others => '0');
slv_reg484 <= (others => '0');
slv_reg485 <= (others => '0');
slv_reg486 <= (others => '0');
slv_reg487 <= (others => '0');
slv_reg488 <= (others => '0');
slv_reg489 <= (others => '0');
slv_reg490 <= (others => '0');
slv_reg491 <= (others => '0');
slv_reg492 <= (others => '0');
slv_reg493 <= (others => '0');
slv_reg494 <= (others => '0');
slv_reg495 <= (others => '0');
slv_reg496 <= (others => '0');
slv_reg497 <= (others => '0');
slv_reg498 <= (others => '0');
slv_reg499 <= (others => '0');
slv_reg500 <= (others => '0');
slv_reg501 <= (others => '0');
slv_reg502 <= (others => '0');
slv_reg503 <= (others => '0');
slv_reg504 <= (others => '0');
slv_reg505 <= (others => '0');
slv_reg506 <= (others => '0');
slv_reg507 <= (others => '0');
slv_reg508 <= (others => '0');
slv_reg509 <= (others => '0');
slv_reg510 <= (others => '0');
slv_reg511 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 32
slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 33
slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 34
slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 35
slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 36
slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 37
slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 38
slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 39
slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 40
slv_reg40(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 41
slv_reg41(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 42
slv_reg42(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 43
slv_reg43(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 44
slv_reg44(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 45
slv_reg45(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 46
slv_reg46(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 47
slv_reg47(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 48
slv_reg48(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 49
slv_reg49(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 50
slv_reg50(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 51
slv_reg51(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 52
slv_reg52(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 53
slv_reg53(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 54
slv_reg54(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 55
slv_reg55(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 56
slv_reg56(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 57
slv_reg57(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 58
slv_reg58(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 59
slv_reg59(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 60
slv_reg60(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 61
slv_reg61(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 62
slv_reg62(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 63
slv_reg63(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 64
slv_reg64(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 65
slv_reg65(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 66
slv_reg66(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 67
slv_reg67(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 68
slv_reg68(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 69
slv_reg69(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 70
slv_reg70(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 71
slv_reg71(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 72
slv_reg72(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 73
slv_reg73(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 74
slv_reg74(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 75
slv_reg75(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 76
slv_reg76(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 77
slv_reg77(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 78
slv_reg78(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 79
slv_reg79(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 80
slv_reg80(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 81
slv_reg81(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 82
slv_reg82(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 83
slv_reg83(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 84
slv_reg84(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 85
slv_reg85(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 86
slv_reg86(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 87
slv_reg87(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 88
slv_reg88(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 89
slv_reg89(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 90
slv_reg90(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 91
slv_reg91(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 92
slv_reg92(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 93
slv_reg93(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 94
slv_reg94(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 95
slv_reg95(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 96
slv_reg96(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 97
slv_reg97(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 98
slv_reg98(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 99
slv_reg99(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 100
slv_reg100(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 101
slv_reg101(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 102
slv_reg102(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 103
slv_reg103(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 104
slv_reg104(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 105
slv_reg105(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 106
slv_reg106(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 107
slv_reg107(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 108
slv_reg108(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 109
slv_reg109(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 110
slv_reg110(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 111
slv_reg111(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 112
slv_reg112(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 113
slv_reg113(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 114
slv_reg114(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 115
slv_reg115(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 116
slv_reg116(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 117
slv_reg117(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 118
slv_reg118(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 119
slv_reg119(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 120
slv_reg120(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 121
slv_reg121(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 122
slv_reg122(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 123
slv_reg123(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 124
slv_reg124(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 125
slv_reg125(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 126
slv_reg126(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 127
slv_reg127(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 128
slv_reg128(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 129
slv_reg129(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 130
slv_reg130(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 131
slv_reg131(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 132
slv_reg132(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 133
slv_reg133(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 134
slv_reg134(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 135
slv_reg135(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 136
slv_reg136(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 137
slv_reg137(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 138
slv_reg138(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 139
slv_reg139(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 140
slv_reg140(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 141
slv_reg141(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 142
slv_reg142(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 143
slv_reg143(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 144
slv_reg144(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 145
slv_reg145(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 146
slv_reg146(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 147
slv_reg147(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 148
slv_reg148(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 149
slv_reg149(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 150
slv_reg150(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 151
slv_reg151(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 152
slv_reg152(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 153
slv_reg153(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 154
slv_reg154(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 155
slv_reg155(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 156
slv_reg156(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 157
slv_reg157(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 158
slv_reg158(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 159
slv_reg159(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 160
slv_reg160(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 161
slv_reg161(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 162
slv_reg162(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 163
slv_reg163(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 164
slv_reg164(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 165
slv_reg165(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 166
slv_reg166(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 167
slv_reg167(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 168
slv_reg168(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 169
slv_reg169(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 170
slv_reg170(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 171
slv_reg171(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 172
slv_reg172(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 173
slv_reg173(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 174
slv_reg174(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 175
slv_reg175(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 176
slv_reg176(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 177
slv_reg177(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 178
slv_reg178(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 179
slv_reg179(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 180
slv_reg180(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 181
slv_reg181(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 182
slv_reg182(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 183
slv_reg183(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 184
slv_reg184(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 185
slv_reg185(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 186
slv_reg186(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 187
slv_reg187(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 188
slv_reg188(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 189
slv_reg189(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 190
slv_reg190(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 191
slv_reg191(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 192
slv_reg192(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 193
slv_reg193(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 194
slv_reg194(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 195
slv_reg195(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 196
slv_reg196(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 197
slv_reg197(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 198
slv_reg198(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 199
slv_reg199(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 200
slv_reg200(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 201
slv_reg201(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 202
slv_reg202(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 203
slv_reg203(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 204
slv_reg204(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 205
slv_reg205(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 206
slv_reg206(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 207
slv_reg207(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 208
slv_reg208(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 209
slv_reg209(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 210
slv_reg210(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 211
slv_reg211(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 212
slv_reg212(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 213
slv_reg213(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 214
slv_reg214(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 215
slv_reg215(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 216
slv_reg216(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 217
slv_reg217(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 218
slv_reg218(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 219
slv_reg219(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 220
slv_reg220(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 221
slv_reg221(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 222
slv_reg222(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 223
slv_reg223(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 224
slv_reg224(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 225
slv_reg225(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 226
slv_reg226(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 227
slv_reg227(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 228
slv_reg228(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 229
slv_reg229(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 230
slv_reg230(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 231
slv_reg231(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 232
slv_reg232(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 233
slv_reg233(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 234
slv_reg234(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 235
slv_reg235(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 236
slv_reg236(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 237
slv_reg237(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 238
slv_reg238(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 239
slv_reg239(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 240
slv_reg240(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 241
slv_reg241(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 242
slv_reg242(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 243
slv_reg243(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 244
slv_reg244(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 245
slv_reg245(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 246
slv_reg246(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 247
slv_reg247(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 248
slv_reg248(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 249
slv_reg249(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 250
slv_reg250(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 251
slv_reg251(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 252
slv_reg252(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 253
slv_reg253(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 254
slv_reg254(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 255
slv_reg255(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 256
slv_reg256(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 257
slv_reg257(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 258
slv_reg258(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 259
slv_reg259(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 260
slv_reg260(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 261
slv_reg261(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 262
slv_reg262(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 263
slv_reg263(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 264
slv_reg264(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 265
slv_reg265(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 266
slv_reg266(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 267
slv_reg267(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 268
slv_reg268(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 269
slv_reg269(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 270
slv_reg270(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 271
slv_reg271(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 272
slv_reg272(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 273
slv_reg273(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 274
slv_reg274(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 275
slv_reg275(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 276
slv_reg276(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 277
slv_reg277(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 278
slv_reg278(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 279
slv_reg279(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 280
slv_reg280(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 281
slv_reg281(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 282
slv_reg282(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 283
slv_reg283(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 284
slv_reg284(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 285
slv_reg285(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 286
slv_reg286(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 287
slv_reg287(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 288
slv_reg288(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 289
slv_reg289(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 290
slv_reg290(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 291
slv_reg291(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 292
slv_reg292(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 293
slv_reg293(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 294
slv_reg294(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 295
slv_reg295(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 296
slv_reg296(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 297
slv_reg297(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 298
slv_reg298(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 299
slv_reg299(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 300
slv_reg300(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 301
slv_reg301(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 302
slv_reg302(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 303
slv_reg303(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 304
slv_reg304(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 305
slv_reg305(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 306
slv_reg306(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 307
slv_reg307(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 308
slv_reg308(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 309
slv_reg309(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 310
slv_reg310(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 311
slv_reg311(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 312
slv_reg312(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 313
slv_reg313(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 314
slv_reg314(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 315
slv_reg315(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 316
slv_reg316(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 317
slv_reg317(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 318
slv_reg318(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 319
slv_reg319(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 320
slv_reg320(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 321
slv_reg321(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 322
slv_reg322(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 323
slv_reg323(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 324
slv_reg324(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 325
slv_reg325(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 326
slv_reg326(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 327
slv_reg327(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 328
slv_reg328(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 329
slv_reg329(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 330
slv_reg330(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 331
slv_reg331(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 332
slv_reg332(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 333
slv_reg333(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 334
slv_reg334(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 335
slv_reg335(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 336
slv_reg336(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 337
slv_reg337(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 338
slv_reg338(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 339
slv_reg339(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 340
slv_reg340(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 341
slv_reg341(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 342
slv_reg342(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 343
slv_reg343(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 344
slv_reg344(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 345
slv_reg345(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 346
slv_reg346(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 347
slv_reg347(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 348
slv_reg348(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 349
slv_reg349(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 350
slv_reg350(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 351
slv_reg351(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 352
slv_reg352(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 353
slv_reg353(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 354
slv_reg354(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 355
slv_reg355(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 356
slv_reg356(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 357
slv_reg357(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 358
slv_reg358(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 359
slv_reg359(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 360
slv_reg360(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 361
slv_reg361(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 362
slv_reg362(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 363
slv_reg363(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 364
slv_reg364(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 365
slv_reg365(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 366
slv_reg366(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 367
slv_reg367(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 368
slv_reg368(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 369
slv_reg369(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 370
slv_reg370(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 371
slv_reg371(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 372
slv_reg372(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 373
slv_reg373(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 374
slv_reg374(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 375
slv_reg375(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 376
slv_reg376(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 377
slv_reg377(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 378
slv_reg378(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 379
slv_reg379(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 380
slv_reg380(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 381
slv_reg381(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 382
slv_reg382(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 383
slv_reg383(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 384
slv_reg384(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 385
slv_reg385(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 386
slv_reg386(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 387
slv_reg387(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 388
slv_reg388(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 389
slv_reg389(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 390
slv_reg390(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 391
slv_reg391(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 392
slv_reg392(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 393
slv_reg393(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 394
slv_reg394(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 395
slv_reg395(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 396
slv_reg396(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 397
slv_reg397(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 398
slv_reg398(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 399
slv_reg399(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 400
slv_reg400(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 401
slv_reg401(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 402
slv_reg402(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 403
slv_reg403(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 404
slv_reg404(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 405
slv_reg405(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 406
slv_reg406(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 407
slv_reg407(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 408
slv_reg408(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 409
slv_reg409(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 410
slv_reg410(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 411
slv_reg411(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 412
slv_reg412(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 413
slv_reg413(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 414
slv_reg414(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 415
slv_reg415(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 416
slv_reg416(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 417
slv_reg417(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 418
slv_reg418(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 419
slv_reg419(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 420
slv_reg420(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 421
slv_reg421(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 422
slv_reg422(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 423
slv_reg423(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 424
slv_reg424(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 425
slv_reg425(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 426
slv_reg426(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 427
slv_reg427(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 428
slv_reg428(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 429
slv_reg429(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 430
slv_reg430(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 431
slv_reg431(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 432
slv_reg432(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 433
slv_reg433(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 434
slv_reg434(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 435
slv_reg435(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 436
slv_reg436(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 437
slv_reg437(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 438
slv_reg438(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 439
slv_reg439(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 440
slv_reg440(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 441
slv_reg441(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 442
slv_reg442(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 443
slv_reg443(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 444
slv_reg444(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 445
slv_reg445(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 446
slv_reg446(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 447
slv_reg447(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 448
slv_reg448(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 449
slv_reg449(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 450
slv_reg450(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 451
slv_reg451(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 452
slv_reg452(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 453
slv_reg453(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 454
slv_reg454(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 455
slv_reg455(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 456
slv_reg456(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 457
slv_reg457(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 458
slv_reg458(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 459
slv_reg459(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 460
slv_reg460(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 461
slv_reg461(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 462
slv_reg462(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 463
slv_reg463(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 464
slv_reg464(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 465
slv_reg465(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 466
slv_reg466(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 467
slv_reg467(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 468
slv_reg468(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 469
slv_reg469(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 470
slv_reg470(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 471
slv_reg471(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 472
slv_reg472(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 473
slv_reg473(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 474
slv_reg474(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 475
slv_reg475(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 476
slv_reg476(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 477
slv_reg477(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 478
slv_reg478(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 479
slv_reg479(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 480
slv_reg480(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 481
slv_reg481(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 482
slv_reg482(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 483
slv_reg483(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 484
slv_reg484(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 485
slv_reg485(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 486
slv_reg486(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 487
slv_reg487(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 488
slv_reg488(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 489
slv_reg489(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 490
slv_reg490(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 491
slv_reg491(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 492
slv_reg492(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 493
slv_reg493(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 494
slv_reg494(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 495
slv_reg495(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 496
slv_reg496(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 497
slv_reg497(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 498
slv_reg498(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 499
slv_reg499(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 500
slv_reg500(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 501
slv_reg501(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 502
slv_reg502(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 503
slv_reg503(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 504
slv_reg504(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 505
slv_reg505(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 506
slv_reg506(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 507
slv_reg507(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 508
slv_reg508(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 509
slv_reg509(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 510
slv_reg510(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 511
slv_reg511(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
slv_reg32 <= slv_reg32;
slv_reg33 <= slv_reg33;
slv_reg34 <= slv_reg34;
slv_reg35 <= slv_reg35;
slv_reg36 <= slv_reg36;
slv_reg37 <= slv_reg37;
slv_reg38 <= slv_reg38;
slv_reg39 <= slv_reg39;
slv_reg40 <= slv_reg40;
slv_reg41 <= slv_reg41;
slv_reg42 <= slv_reg42;
slv_reg43 <= slv_reg43;
slv_reg44 <= slv_reg44;
slv_reg45 <= slv_reg45;
slv_reg46 <= slv_reg46;
slv_reg47 <= slv_reg47;
slv_reg48 <= slv_reg48;
slv_reg49 <= slv_reg49;
slv_reg50 <= slv_reg50;
slv_reg51 <= slv_reg51;
slv_reg52 <= slv_reg52;
slv_reg53 <= slv_reg53;
slv_reg54 <= slv_reg54;
slv_reg55 <= slv_reg55;
slv_reg56 <= slv_reg56;
slv_reg57 <= slv_reg57;
slv_reg58 <= slv_reg58;
slv_reg59 <= slv_reg59;
slv_reg60 <= slv_reg60;
slv_reg61 <= slv_reg61;
slv_reg62 <= slv_reg62;
slv_reg63 <= slv_reg63;
slv_reg64 <= slv_reg64;
slv_reg65 <= slv_reg65;
slv_reg66 <= slv_reg66;
slv_reg67 <= slv_reg67;
slv_reg68 <= slv_reg68;
slv_reg69 <= slv_reg69;
slv_reg70 <= slv_reg70;
slv_reg71 <= slv_reg71;
slv_reg72 <= slv_reg72;
slv_reg73 <= slv_reg73;
slv_reg74 <= slv_reg74;
slv_reg75 <= slv_reg75;
slv_reg76 <= slv_reg76;
slv_reg77 <= slv_reg77;
slv_reg78 <= slv_reg78;
slv_reg79 <= slv_reg79;
slv_reg80 <= slv_reg80;
slv_reg81 <= slv_reg81;
slv_reg82 <= slv_reg82;
slv_reg83 <= slv_reg83;
slv_reg84 <= slv_reg84;
slv_reg85 <= slv_reg85;
slv_reg86 <= slv_reg86;
slv_reg87 <= slv_reg87;
slv_reg88 <= slv_reg88;
slv_reg89 <= slv_reg89;
slv_reg90 <= slv_reg90;
slv_reg91 <= slv_reg91;
slv_reg92 <= slv_reg92;
slv_reg93 <= slv_reg93;
slv_reg94 <= slv_reg94;
slv_reg95 <= slv_reg95;
slv_reg96 <= slv_reg96;
slv_reg97 <= slv_reg97;
slv_reg98 <= slv_reg98;
slv_reg99 <= slv_reg99;
slv_reg100 <= slv_reg100;
slv_reg101 <= slv_reg101;
slv_reg102 <= slv_reg102;
slv_reg103 <= slv_reg103;
slv_reg104 <= slv_reg104;
slv_reg105 <= slv_reg105;
slv_reg106 <= slv_reg106;
slv_reg107 <= slv_reg107;
slv_reg108 <= slv_reg108;
slv_reg109 <= slv_reg109;
slv_reg110 <= slv_reg110;
slv_reg111 <= slv_reg111;
slv_reg112 <= slv_reg112;
slv_reg113 <= slv_reg113;
slv_reg114 <= slv_reg114;
slv_reg115 <= slv_reg115;
slv_reg116 <= slv_reg116;
slv_reg117 <= slv_reg117;
slv_reg118 <= slv_reg118;
slv_reg119 <= slv_reg119;
slv_reg120 <= slv_reg120;
slv_reg121 <= slv_reg121;
slv_reg122 <= slv_reg122;
slv_reg123 <= slv_reg123;
slv_reg124 <= slv_reg124;
slv_reg125 <= slv_reg125;
slv_reg126 <= slv_reg126;
slv_reg127 <= slv_reg127;
slv_reg128 <= slv_reg128;
slv_reg129 <= slv_reg129;
slv_reg130 <= slv_reg130;
slv_reg131 <= slv_reg131;
slv_reg132 <= slv_reg132;
slv_reg133 <= slv_reg133;
slv_reg134 <= slv_reg134;
slv_reg135 <= slv_reg135;
slv_reg136 <= slv_reg136;
slv_reg137 <= slv_reg137;
slv_reg138 <= slv_reg138;
slv_reg139 <= slv_reg139;
slv_reg140 <= slv_reg140;
slv_reg141 <= slv_reg141;
slv_reg142 <= slv_reg142;
slv_reg143 <= slv_reg143;
slv_reg144 <= slv_reg144;
slv_reg145 <= slv_reg145;
slv_reg146 <= slv_reg146;
slv_reg147 <= slv_reg147;
slv_reg148 <= slv_reg148;
slv_reg149 <= slv_reg149;
slv_reg150 <= slv_reg150;
slv_reg151 <= slv_reg151;
slv_reg152 <= slv_reg152;
slv_reg153 <= slv_reg153;
slv_reg154 <= slv_reg154;
slv_reg155 <= slv_reg155;
slv_reg156 <= slv_reg156;
slv_reg157 <= slv_reg157;
slv_reg158 <= slv_reg158;
slv_reg159 <= slv_reg159;
slv_reg160 <= slv_reg160;
slv_reg161 <= slv_reg161;
slv_reg162 <= slv_reg162;
slv_reg163 <= slv_reg163;
slv_reg164 <= slv_reg164;
slv_reg165 <= slv_reg165;
slv_reg166 <= slv_reg166;
slv_reg167 <= slv_reg167;
slv_reg168 <= slv_reg168;
slv_reg169 <= slv_reg169;
slv_reg170 <= slv_reg170;
slv_reg171 <= slv_reg171;
slv_reg172 <= slv_reg172;
slv_reg173 <= slv_reg173;
slv_reg174 <= slv_reg174;
slv_reg175 <= slv_reg175;
slv_reg176 <= slv_reg176;
slv_reg177 <= slv_reg177;
slv_reg178 <= slv_reg178;
slv_reg179 <= slv_reg179;
slv_reg180 <= slv_reg180;
slv_reg181 <= slv_reg181;
slv_reg182 <= slv_reg182;
slv_reg183 <= slv_reg183;
slv_reg184 <= slv_reg184;
slv_reg185 <= slv_reg185;
slv_reg186 <= slv_reg186;
slv_reg187 <= slv_reg187;
slv_reg188 <= slv_reg188;
slv_reg189 <= slv_reg189;
slv_reg190 <= slv_reg190;
slv_reg191 <= slv_reg191;
slv_reg192 <= slv_reg192;
slv_reg193 <= slv_reg193;
slv_reg194 <= slv_reg194;
slv_reg195 <= slv_reg195;
slv_reg196 <= slv_reg196;
slv_reg197 <= slv_reg197;
slv_reg198 <= slv_reg198;
slv_reg199 <= slv_reg199;
slv_reg200 <= slv_reg200;
slv_reg201 <= slv_reg201;
slv_reg202 <= slv_reg202;
slv_reg203 <= slv_reg203;
slv_reg204 <= slv_reg204;
slv_reg205 <= slv_reg205;
slv_reg206 <= slv_reg206;
slv_reg207 <= slv_reg207;
slv_reg208 <= slv_reg208;
slv_reg209 <= slv_reg209;
slv_reg210 <= slv_reg210;
slv_reg211 <= slv_reg211;
slv_reg212 <= slv_reg212;
slv_reg213 <= slv_reg213;
slv_reg214 <= slv_reg214;
slv_reg215 <= slv_reg215;
slv_reg216 <= slv_reg216;
slv_reg217 <= slv_reg217;
slv_reg218 <= slv_reg218;
slv_reg219 <= slv_reg219;
slv_reg220 <= slv_reg220;
slv_reg221 <= slv_reg221;
slv_reg222 <= slv_reg222;
slv_reg223 <= slv_reg223;
slv_reg224 <= slv_reg224;
slv_reg225 <= slv_reg225;
slv_reg226 <= slv_reg226;
slv_reg227 <= slv_reg227;
slv_reg228 <= slv_reg228;
slv_reg229 <= slv_reg229;
slv_reg230 <= slv_reg230;
slv_reg231 <= slv_reg231;
slv_reg232 <= slv_reg232;
slv_reg233 <= slv_reg233;
slv_reg234 <= slv_reg234;
slv_reg235 <= slv_reg235;
slv_reg236 <= slv_reg236;
slv_reg237 <= slv_reg237;
slv_reg238 <= slv_reg238;
slv_reg239 <= slv_reg239;
slv_reg240 <= slv_reg240;
slv_reg241 <= slv_reg241;
slv_reg242 <= slv_reg242;
slv_reg243 <= slv_reg243;
slv_reg244 <= slv_reg244;
slv_reg245 <= slv_reg245;
slv_reg246 <= slv_reg246;
slv_reg247 <= slv_reg247;
slv_reg248 <= slv_reg248;
slv_reg249 <= slv_reg249;
slv_reg250 <= slv_reg250;
slv_reg251 <= slv_reg251;
slv_reg252 <= slv_reg252;
slv_reg253 <= slv_reg253;
slv_reg254 <= slv_reg254;
slv_reg255 <= slv_reg255;
slv_reg256 <= slv_reg256;
slv_reg257 <= slv_reg257;
slv_reg258 <= slv_reg258;
slv_reg259 <= slv_reg259;
slv_reg260 <= slv_reg260;
slv_reg261 <= slv_reg261;
slv_reg262 <= slv_reg262;
slv_reg263 <= slv_reg263;
slv_reg264 <= slv_reg264;
slv_reg265 <= slv_reg265;
slv_reg266 <= slv_reg266;
slv_reg267 <= slv_reg267;
slv_reg268 <= slv_reg268;
slv_reg269 <= slv_reg269;
slv_reg270 <= slv_reg270;
slv_reg271 <= slv_reg271;
slv_reg272 <= slv_reg272;
slv_reg273 <= slv_reg273;
slv_reg274 <= slv_reg274;
slv_reg275 <= slv_reg275;
slv_reg276 <= slv_reg276;
slv_reg277 <= slv_reg277;
slv_reg278 <= slv_reg278;
slv_reg279 <= slv_reg279;
slv_reg280 <= slv_reg280;
slv_reg281 <= slv_reg281;
slv_reg282 <= slv_reg282;
slv_reg283 <= slv_reg283;
slv_reg284 <= slv_reg284;
slv_reg285 <= slv_reg285;
slv_reg286 <= slv_reg286;
slv_reg287 <= slv_reg287;
slv_reg288 <= slv_reg288;
slv_reg289 <= slv_reg289;
slv_reg290 <= slv_reg290;
slv_reg291 <= slv_reg291;
slv_reg292 <= slv_reg292;
slv_reg293 <= slv_reg293;
slv_reg294 <= slv_reg294;
slv_reg295 <= slv_reg295;
slv_reg296 <= slv_reg296;
slv_reg297 <= slv_reg297;
slv_reg298 <= slv_reg298;
slv_reg299 <= slv_reg299;
slv_reg300 <= slv_reg300;
slv_reg301 <= slv_reg301;
slv_reg302 <= slv_reg302;
slv_reg303 <= slv_reg303;
slv_reg304 <= slv_reg304;
slv_reg305 <= slv_reg305;
slv_reg306 <= slv_reg306;
slv_reg307 <= slv_reg307;
slv_reg308 <= slv_reg308;
slv_reg309 <= slv_reg309;
slv_reg310 <= slv_reg310;
slv_reg311 <= slv_reg311;
slv_reg312 <= slv_reg312;
slv_reg313 <= slv_reg313;
slv_reg314 <= slv_reg314;
slv_reg315 <= slv_reg315;
slv_reg316 <= slv_reg316;
slv_reg317 <= slv_reg317;
slv_reg318 <= slv_reg318;
slv_reg319 <= slv_reg319;
slv_reg320 <= slv_reg320;
slv_reg321 <= slv_reg321;
slv_reg322 <= slv_reg322;
slv_reg323 <= slv_reg323;
slv_reg324 <= slv_reg324;
slv_reg325 <= slv_reg325;
slv_reg326 <= slv_reg326;
slv_reg327 <= slv_reg327;
slv_reg328 <= slv_reg328;
slv_reg329 <= slv_reg329;
slv_reg330 <= slv_reg330;
slv_reg331 <= slv_reg331;
slv_reg332 <= slv_reg332;
slv_reg333 <= slv_reg333;
slv_reg334 <= slv_reg334;
slv_reg335 <= slv_reg335;
slv_reg336 <= slv_reg336;
slv_reg337 <= slv_reg337;
slv_reg338 <= slv_reg338;
slv_reg339 <= slv_reg339;
slv_reg340 <= slv_reg340;
slv_reg341 <= slv_reg341;
slv_reg342 <= slv_reg342;
slv_reg343 <= slv_reg343;
slv_reg344 <= slv_reg344;
slv_reg345 <= slv_reg345;
slv_reg346 <= slv_reg346;
slv_reg347 <= slv_reg347;
slv_reg348 <= slv_reg348;
slv_reg349 <= slv_reg349;
slv_reg350 <= slv_reg350;
slv_reg351 <= slv_reg351;
slv_reg352 <= slv_reg352;
slv_reg353 <= slv_reg353;
slv_reg354 <= slv_reg354;
slv_reg355 <= slv_reg355;
slv_reg356 <= slv_reg356;
slv_reg357 <= slv_reg357;
slv_reg358 <= slv_reg358;
slv_reg359 <= slv_reg359;
slv_reg360 <= slv_reg360;
slv_reg361 <= slv_reg361;
slv_reg362 <= slv_reg362;
slv_reg363 <= slv_reg363;
slv_reg364 <= slv_reg364;
slv_reg365 <= slv_reg365;
slv_reg366 <= slv_reg366;
slv_reg367 <= slv_reg367;
slv_reg368 <= slv_reg368;
slv_reg369 <= slv_reg369;
slv_reg370 <= slv_reg370;
slv_reg371 <= slv_reg371;
slv_reg372 <= slv_reg372;
slv_reg373 <= slv_reg373;
slv_reg374 <= slv_reg374;
slv_reg375 <= slv_reg375;
slv_reg376 <= slv_reg376;
slv_reg377 <= slv_reg377;
slv_reg378 <= slv_reg378;
slv_reg379 <= slv_reg379;
slv_reg380 <= slv_reg380;
slv_reg381 <= slv_reg381;
slv_reg382 <= slv_reg382;
slv_reg383 <= slv_reg383;
slv_reg384 <= slv_reg384;
slv_reg385 <= slv_reg385;
slv_reg386 <= slv_reg386;
slv_reg387 <= slv_reg387;
slv_reg388 <= slv_reg388;
slv_reg389 <= slv_reg389;
slv_reg390 <= slv_reg390;
slv_reg391 <= slv_reg391;
slv_reg392 <= slv_reg392;
slv_reg393 <= slv_reg393;
slv_reg394 <= slv_reg394;
slv_reg395 <= slv_reg395;
slv_reg396 <= slv_reg396;
slv_reg397 <= slv_reg397;
slv_reg398 <= slv_reg398;
slv_reg399 <= slv_reg399;
slv_reg400 <= slv_reg400;
slv_reg401 <= slv_reg401;
slv_reg402 <= slv_reg402;
slv_reg403 <= slv_reg403;
slv_reg404 <= slv_reg404;
slv_reg405 <= slv_reg405;
slv_reg406 <= slv_reg406;
slv_reg407 <= slv_reg407;
slv_reg408 <= slv_reg408;
slv_reg409 <= slv_reg409;
slv_reg410 <= slv_reg410;
slv_reg411 <= slv_reg411;
slv_reg412 <= slv_reg412;
slv_reg413 <= slv_reg413;
slv_reg414 <= slv_reg414;
slv_reg415 <= slv_reg415;
slv_reg416 <= slv_reg416;
slv_reg417 <= slv_reg417;
slv_reg418 <= slv_reg418;
slv_reg419 <= slv_reg419;
slv_reg420 <= slv_reg420;
slv_reg421 <= slv_reg421;
slv_reg422 <= slv_reg422;
slv_reg423 <= slv_reg423;
slv_reg424 <= slv_reg424;
slv_reg425 <= slv_reg425;
slv_reg426 <= slv_reg426;
slv_reg427 <= slv_reg427;
slv_reg428 <= slv_reg428;
slv_reg429 <= slv_reg429;
slv_reg430 <= slv_reg430;
slv_reg431 <= slv_reg431;
slv_reg432 <= slv_reg432;
slv_reg433 <= slv_reg433;
slv_reg434 <= slv_reg434;
slv_reg435 <= slv_reg435;
slv_reg436 <= slv_reg436;
slv_reg437 <= slv_reg437;
slv_reg438 <= slv_reg438;
slv_reg439 <= slv_reg439;
slv_reg440 <= slv_reg440;
slv_reg441 <= slv_reg441;
slv_reg442 <= slv_reg442;
slv_reg443 <= slv_reg443;
slv_reg444 <= slv_reg444;
slv_reg445 <= slv_reg445;
slv_reg446 <= slv_reg446;
slv_reg447 <= slv_reg447;
slv_reg448 <= slv_reg448;
slv_reg449 <= slv_reg449;
slv_reg450 <= slv_reg450;
slv_reg451 <= slv_reg451;
slv_reg452 <= slv_reg452;
slv_reg453 <= slv_reg453;
slv_reg454 <= slv_reg454;
slv_reg455 <= slv_reg455;
slv_reg456 <= slv_reg456;
slv_reg457 <= slv_reg457;
slv_reg458 <= slv_reg458;
slv_reg459 <= slv_reg459;
slv_reg460 <= slv_reg460;
slv_reg461 <= slv_reg461;
slv_reg462 <= slv_reg462;
slv_reg463 <= slv_reg463;
slv_reg464 <= slv_reg464;
slv_reg465 <= slv_reg465;
slv_reg466 <= slv_reg466;
slv_reg467 <= slv_reg467;
slv_reg468 <= slv_reg468;
slv_reg469 <= slv_reg469;
slv_reg470 <= slv_reg470;
slv_reg471 <= slv_reg471;
slv_reg472 <= slv_reg472;
slv_reg473 <= slv_reg473;
slv_reg474 <= slv_reg474;
slv_reg475 <= slv_reg475;
slv_reg476 <= slv_reg476;
slv_reg477 <= slv_reg477;
slv_reg478 <= slv_reg478;
slv_reg479 <= slv_reg479;
slv_reg480 <= slv_reg480;
slv_reg481 <= slv_reg481;
slv_reg482 <= slv_reg482;
slv_reg483 <= slv_reg483;
slv_reg484 <= slv_reg484;
slv_reg485 <= slv_reg485;
slv_reg486 <= slv_reg486;
slv_reg487 <= slv_reg487;
slv_reg488 <= slv_reg488;
slv_reg489 <= slv_reg489;
slv_reg490 <= slv_reg490;
slv_reg491 <= slv_reg491;
slv_reg492 <= slv_reg492;
slv_reg493 <= slv_reg493;
slv_reg494 <= slv_reg494;
slv_reg495 <= slv_reg495;
slv_reg496 <= slv_reg496;
slv_reg497 <= slv_reg497;
slv_reg498 <= slv_reg498;
slv_reg499 <= slv_reg499;
slv_reg500 <= slv_reg500;
slv_reg501 <= slv_reg501;
slv_reg502 <= slv_reg502;
slv_reg503 <= slv_reg503;
slv_reg504 <= slv_reg504;
slv_reg505 <= slv_reg505;
slv_reg506 <= slv_reg506;
slv_reg507 <= slv_reg507;
slv_reg508 <= slv_reg508;
slv_reg509 <= slv_reg509;
slv_reg510 <= slv_reg510;
slv_reg511 <= slv_reg511;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, slv_reg40, slv_reg41, slv_reg42, slv_reg43, slv_reg44, slv_reg45, slv_reg46, slv_reg47, slv_reg48, slv_reg49, slv_reg50, slv_reg51, slv_reg52, slv_reg53, slv_reg54, slv_reg55, slv_reg56, slv_reg57, slv_reg58, slv_reg59, slv_reg60, slv_reg61, slv_reg62, slv_reg63, slv_reg64, slv_reg65, slv_reg66, slv_reg67, slv_reg68, slv_reg69, slv_reg70, slv_reg71, slv_reg72, slv_reg73, slv_reg74, slv_reg75, slv_reg76, slv_reg77, slv_reg78, slv_reg79, slv_reg80, slv_reg81, slv_reg82, slv_reg83, slv_reg84, slv_reg85, slv_reg86, slv_reg87, slv_reg88, slv_reg89, slv_reg90, slv_reg91, slv_reg92, slv_reg93, slv_reg94, slv_reg95, slv_reg96, slv_reg97, slv_reg98, slv_reg99, slv_reg100, slv_reg101, slv_reg102, slv_reg103, slv_reg104, slv_reg105, slv_reg106, slv_reg107, slv_reg108, slv_reg109, slv_reg110, slv_reg111, slv_reg112, slv_reg113, slv_reg114, slv_reg115, slv_reg116, slv_reg117, slv_reg118, slv_reg119, slv_reg120, slv_reg121, slv_reg122, slv_reg123, slv_reg124, slv_reg125, slv_reg126, slv_reg127, slv_reg128, slv_reg129, slv_reg130, slv_reg131, slv_reg132, slv_reg133, slv_reg134, slv_reg135, slv_reg136, slv_reg137, slv_reg138, slv_reg139, slv_reg140, slv_reg141, slv_reg142, slv_reg143, slv_reg144, slv_reg145, slv_reg146, slv_reg147, slv_reg148, slv_reg149, slv_reg150, slv_reg151, slv_reg152, slv_reg153, slv_reg154, slv_reg155, slv_reg156, slv_reg157, slv_reg158, slv_reg159, slv_reg160, slv_reg161, slv_reg162, slv_reg163, slv_reg164, slv_reg165, slv_reg166, slv_reg167, slv_reg168, slv_reg169, slv_reg170, slv_reg171, slv_reg172, slv_reg173, slv_reg174, slv_reg175, slv_reg176, slv_reg177, slv_reg178, slv_reg179, slv_reg180, slv_reg181, slv_reg182, slv_reg183, slv_reg184, slv_reg185, slv_reg186, slv_reg187, slv_reg188, slv_reg189, slv_reg190, slv_reg191, slv_reg192, slv_reg193, slv_reg194, slv_reg195, slv_reg196, slv_reg197, slv_reg198, slv_reg199, slv_reg200, slv_reg201, slv_reg202, slv_reg203, slv_reg204, slv_reg205, slv_reg206, slv_reg207, slv_reg208, slv_reg209, slv_reg210, slv_reg211, slv_reg212, slv_reg213, slv_reg214, slv_reg215, slv_reg216, slv_reg217, slv_reg218, slv_reg219, slv_reg220, slv_reg221, slv_reg222, slv_reg223, slv_reg224, slv_reg225, slv_reg226, slv_reg227, slv_reg228, slv_reg229, slv_reg230, slv_reg231, slv_reg232, slv_reg233, slv_reg234, slv_reg235, slv_reg236, slv_reg237, slv_reg238, slv_reg239, slv_reg240, slv_reg241, slv_reg242, slv_reg243, slv_reg244, slv_reg245, slv_reg246, slv_reg247, slv_reg248, slv_reg249, slv_reg250, slv_reg251, slv_reg252, slv_reg253, slv_reg254, slv_reg255, slv_reg256, slv_reg257, slv_reg258, slv_reg259, slv_reg260, slv_reg261, slv_reg262, slv_reg263, slv_reg264, slv_reg265, slv_reg266, slv_reg267, slv_reg268, slv_reg269, slv_reg270, slv_reg271, slv_reg272, slv_reg273, slv_reg274, slv_reg275, slv_reg276, slv_reg277, slv_reg278, slv_reg279, slv_reg280, slv_reg281, slv_reg282, slv_reg283, slv_reg284, slv_reg285, slv_reg286, slv_reg287, slv_reg288, slv_reg289, slv_reg290, slv_reg291, slv_reg292, slv_reg293, slv_reg294, slv_reg295, slv_reg296, slv_reg297, slv_reg298, slv_reg299, slv_reg300, slv_reg301, slv_reg302, slv_reg303, slv_reg304, slv_reg305, slv_reg306, slv_reg307, slv_reg308, slv_reg309, slv_reg310, slv_reg311, slv_reg312, slv_reg313, slv_reg314, slv_reg315, slv_reg316, slv_reg317, slv_reg318, slv_reg319, slv_reg320, slv_reg321, slv_reg322, slv_reg323, slv_reg324, slv_reg325, slv_reg326, slv_reg327, slv_reg328, slv_reg329, slv_reg330, slv_reg331, slv_reg332, slv_reg333, slv_reg334, slv_reg335, slv_reg336, slv_reg337, slv_reg338, slv_reg339, slv_reg340, slv_reg341, slv_reg342, slv_reg343, slv_reg344, slv_reg345, slv_reg346, slv_reg347, slv_reg348, slv_reg349, slv_reg350, slv_reg351, slv_reg352, slv_reg353, slv_reg354, slv_reg355, slv_reg356, slv_reg357, slv_reg358, slv_reg359, slv_reg360, slv_reg361, slv_reg362, slv_reg363, slv_reg364, slv_reg365, slv_reg366, slv_reg367, slv_reg368, slv_reg369, slv_reg370, slv_reg371, slv_reg372, slv_reg373, slv_reg374, slv_reg375, slv_reg376, slv_reg377, slv_reg378, slv_reg379, slv_reg380, slv_reg381, slv_reg382, slv_reg383, slv_reg384, slv_reg385, slv_reg386, slv_reg387, slv_reg388, slv_reg389, slv_reg390, slv_reg391, slv_reg392, slv_reg393, slv_reg394, slv_reg395, slv_reg396, slv_reg397, slv_reg398, slv_reg399, slv_reg400, slv_reg401, slv_reg402, slv_reg403, slv_reg404, slv_reg405, slv_reg406, slv_reg407, slv_reg408, slv_reg409, slv_reg410, slv_reg411, slv_reg412, slv_reg413, slv_reg414, slv_reg415, slv_reg416, slv_reg417, slv_reg418, slv_reg419, slv_reg420, slv_reg421, slv_reg422, slv_reg423, slv_reg424, slv_reg425, slv_reg426, slv_reg427, slv_reg428, slv_reg429, slv_reg430, slv_reg431, slv_reg432, slv_reg433, slv_reg434, slv_reg435, slv_reg436, slv_reg437, slv_reg438, slv_reg439, slv_reg440, slv_reg441, slv_reg442, slv_reg443, slv_reg444, slv_reg445, slv_reg446, slv_reg447, slv_reg448, slv_reg449, slv_reg450, slv_reg451, slv_reg452, slv_reg453, slv_reg454, slv_reg455, slv_reg456, slv_reg457, slv_reg458, slv_reg459, slv_reg460, slv_reg461, slv_reg462, slv_reg463, slv_reg464, slv_reg465, slv_reg466, slv_reg467, slv_reg468, slv_reg469, slv_reg470, slv_reg471, slv_reg472, slv_reg473, slv_reg474, slv_reg475, slv_reg476, slv_reg477, slv_reg478, slv_reg479, slv_reg480, slv_reg481, slv_reg482, slv_reg483, slv_reg484, slv_reg485, slv_reg486, slv_reg487, slv_reg488, slv_reg489, slv_reg490, slv_reg491, slv_reg492, slv_reg493, slv_reg494, slv_reg495, slv_reg496, slv_reg497, slv_reg498, slv_reg499, slv_reg500, slv_reg501, slv_reg502, slv_reg503, slv_reg504, slv_reg505, slv_reg506, slv_reg507, slv_reg508, slv_reg509, slv_reg510, slv_reg511, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when b"000000101" =>
reg_data_out <= slv_reg5;
when b"000000110" =>
reg_data_out <= slv_reg6;
when b"000000111" =>
reg_data_out <= slv_reg7;
when b"000001000" =>
reg_data_out <= slv_reg8;
when b"000001001" =>
reg_data_out <= slv_reg9;
when b"000001010" =>
reg_data_out <= slv_reg10;
when b"000001011" =>
reg_data_out <= slv_reg11;
when b"000001100" =>
reg_data_out <= slv_reg12;
when b"000001101" =>
reg_data_out <= slv_reg13;
when b"000001110" =>
reg_data_out <= slv_reg14;
when b"000001111" =>
reg_data_out <= slv_reg15;
when b"000010000" =>
reg_data_out <= slv_reg16;
when b"000010001" =>
reg_data_out <= slv_reg17;
when b"000010010" =>
reg_data_out <= slv_reg18;
when b"000010011" =>
reg_data_out <= slv_reg19;
when b"000010100" =>
reg_data_out <= slv_reg20;
when b"000010101" =>
reg_data_out <= slv_reg21;
when b"000010110" =>
reg_data_out <= slv_reg22;
when b"000010111" =>
reg_data_out <= slv_reg23;
when b"000011000" =>
reg_data_out <= slv_reg24;
when b"000011001" =>
reg_data_out <= slv_reg25;
when b"000011010" =>
reg_data_out <= slv_reg26;
when b"000011011" =>
reg_data_out <= slv_reg27;
when b"000011100" =>
reg_data_out <= slv_reg28;
when b"000011101" =>
reg_data_out <= slv_reg29;
when b"000011110" =>
reg_data_out <= slv_reg30;
when b"000011111" =>
reg_data_out <= slv_reg31;
when b"000100000" =>
reg_data_out <= slv_reg32;
when b"000100001" =>
reg_data_out <= slv_reg33;
when b"000100010" =>
reg_data_out <= slv_reg34;
when b"000100011" =>
reg_data_out <= slv_reg35;
when b"000100100" =>
reg_data_out <= slv_reg36;
when b"000100101" =>
reg_data_out <= slv_reg37;
when b"000100110" =>
reg_data_out <= slv_reg38;
when b"000100111" =>
reg_data_out <= slv_reg39;
when b"000101000" =>
reg_data_out <= slv_reg40;
when b"000101001" =>
reg_data_out <= slv_reg41;
when b"000101010" =>
reg_data_out <= slv_reg42;
when b"000101011" =>
reg_data_out <= slv_reg43;
when b"000101100" =>
reg_data_out <= slv_reg44;
when b"000101101" =>
reg_data_out <= slv_reg45;
when b"000101110" =>
reg_data_out <= slv_reg46;
when b"000101111" =>
reg_data_out <= slv_reg47;
when b"000110000" =>
reg_data_out <= slv_reg48;
when b"000110001" =>
reg_data_out <= slv_reg49;
when b"000110010" =>
reg_data_out <= slv_reg50;
when b"000110011" =>
reg_data_out <= slv_reg51;
when b"000110100" =>
reg_data_out <= slv_reg52;
when b"000110101" =>
reg_data_out <= slv_reg53;
when b"000110110" =>
reg_data_out <= slv_reg54;
when b"000110111" =>
reg_data_out <= slv_reg55;
when b"000111000" =>
reg_data_out <= slv_reg56;
when b"000111001" =>
reg_data_out <= slv_reg57;
when b"000111010" =>
reg_data_out <= slv_reg58;
when b"000111011" =>
reg_data_out <= slv_reg59;
when b"000111100" =>
reg_data_out <= slv_reg60;
when b"000111101" =>
reg_data_out <= slv_reg61;
when b"000111110" =>
reg_data_out <= slv_reg62;
when b"000111111" =>
reg_data_out <= slv_reg63;
when b"001000000" =>
reg_data_out <= slv_reg64;
when b"001000001" =>
reg_data_out <= slv_reg65;
when b"001000010" =>
reg_data_out <= slv_reg66;
when b"001000011" =>
reg_data_out <= slv_reg67;
when b"001000100" =>
reg_data_out <= slv_reg68;
when b"001000101" =>
reg_data_out <= slv_reg69;
when b"001000110" =>
reg_data_out <= slv_reg70;
when b"001000111" =>
reg_data_out <= slv_reg71;
when b"001001000" =>
reg_data_out <= slv_reg72;
when b"001001001" =>
reg_data_out <= slv_reg73;
when b"001001010" =>
reg_data_out <= slv_reg74;
when b"001001011" =>
reg_data_out <= slv_reg75;
when b"001001100" =>
reg_data_out <= slv_reg76;
when b"001001101" =>
reg_data_out <= slv_reg77;
when b"001001110" =>
reg_data_out <= slv_reg78;
when b"001001111" =>
reg_data_out <= slv_reg79;
when b"001010000" =>
reg_data_out <= slv_reg80;
when b"001010001" =>
reg_data_out <= slv_reg81;
when b"001010010" =>
reg_data_out <= slv_reg82;
when b"001010011" =>
reg_data_out <= slv_reg83;
when b"001010100" =>
reg_data_out <= slv_reg84;
when b"001010101" =>
reg_data_out <= slv_reg85;
when b"001010110" =>
reg_data_out <= slv_reg86;
when b"001010111" =>
reg_data_out <= slv_reg87;
when b"001011000" =>
reg_data_out <= slv_reg88;
when b"001011001" =>
reg_data_out <= slv_reg89;
when b"001011010" =>
reg_data_out <= slv_reg90;
when b"001011011" =>
reg_data_out <= slv_reg91;
when b"001011100" =>
reg_data_out <= slv_reg92;
when b"001011101" =>
reg_data_out <= slv_reg93;
when b"001011110" =>
reg_data_out <= slv_reg94;
when b"001011111" =>
reg_data_out <= slv_reg95;
when b"001100000" =>
reg_data_out <= slv_reg96;
when b"001100001" =>
reg_data_out <= slv_reg97;
when b"001100010" =>
reg_data_out <= slv_reg98;
when b"001100011" =>
reg_data_out <= slv_reg99;
when b"001100100" =>
reg_data_out <= slv_reg100;
when b"001100101" =>
reg_data_out <= slv_reg101;
when b"001100110" =>
reg_data_out <= slv_reg102;
when b"001100111" =>
reg_data_out <= slv_reg103;
when b"001101000" =>
reg_data_out <= slv_reg104;
when b"001101001" =>
reg_data_out <= slv_reg105;
when b"001101010" =>
reg_data_out <= slv_reg106;
when b"001101011" =>
reg_data_out <= slv_reg107;
when b"001101100" =>
reg_data_out <= slv_reg108;
when b"001101101" =>
reg_data_out <= slv_reg109;
when b"001101110" =>
reg_data_out <= slv_reg110;
when b"001101111" =>
reg_data_out <= slv_reg111;
when b"001110000" =>
reg_data_out <= slv_reg112;
when b"001110001" =>
reg_data_out <= slv_reg113;
when b"001110010" =>
reg_data_out <= slv_reg114;
when b"001110011" =>
reg_data_out <= slv_reg115;
when b"001110100" =>
reg_data_out <= slv_reg116;
when b"001110101" =>
reg_data_out <= slv_reg117;
when b"001110110" =>
reg_data_out <= slv_reg118;
when b"001110111" =>
reg_data_out <= slv_reg119;
when b"001111000" =>
reg_data_out <= slv_reg120;
when b"001111001" =>
reg_data_out <= slv_reg121;
when b"001111010" =>
reg_data_out <= slv_reg122;
when b"001111011" =>
reg_data_out <= slv_reg123;
when b"001111100" =>
reg_data_out <= slv_reg124;
when b"001111101" =>
reg_data_out <= slv_reg125;
when b"001111110" =>
reg_data_out <= slv_reg126;
when b"001111111" =>
reg_data_out <= slv_reg127;
when b"010000000" =>
reg_data_out <= slv_reg128;
when b"010000001" =>
reg_data_out <= slv_reg129;
when b"010000010" =>
reg_data_out <= slv_reg130;
when b"010000011" =>
reg_data_out <= slv_reg131;
when b"010000100" =>
reg_data_out <= slv_reg132;
when b"010000101" =>
reg_data_out <= slv_reg133;
when b"010000110" =>
reg_data_out <= slv_reg134;
when b"010000111" =>
reg_data_out <= slv_reg135;
when b"010001000" =>
reg_data_out <= slv_reg136;
when b"010001001" =>
reg_data_out <= slv_reg137;
when b"010001010" =>
reg_data_out <= slv_reg138;
when b"010001011" =>
reg_data_out <= slv_reg139;
when b"010001100" =>
reg_data_out <= slv_reg140;
when b"010001101" =>
reg_data_out <= slv_reg141;
when b"010001110" =>
reg_data_out <= slv_reg142;
when b"010001111" =>
reg_data_out <= slv_reg143;
when b"010010000" =>
reg_data_out <= slv_reg144;
when b"010010001" =>
reg_data_out <= slv_reg145;
when b"010010010" =>
reg_data_out <= slv_reg146;
when b"010010011" =>
reg_data_out <= slv_reg147;
when b"010010100" =>
reg_data_out <= slv_reg148;
when b"010010101" =>
reg_data_out <= slv_reg149;
when b"010010110" =>
reg_data_out <= slv_reg150;
when b"010010111" =>
reg_data_out <= slv_reg151;
when b"010011000" =>
reg_data_out <= slv_reg152;
when b"010011001" =>
reg_data_out <= slv_reg153;
when b"010011010" =>
reg_data_out <= slv_reg154;
when b"010011011" =>
reg_data_out <= slv_reg155;
when b"010011100" =>
reg_data_out <= slv_reg156;
when b"010011101" =>
reg_data_out <= slv_reg157;
when b"010011110" =>
reg_data_out <= slv_reg158;
when b"010011111" =>
reg_data_out <= slv_reg159;
when b"010100000" =>
reg_data_out <= slv_reg160;
when b"010100001" =>
reg_data_out <= slv_reg161;
when b"010100010" =>
reg_data_out <= slv_reg162;
when b"010100011" =>
reg_data_out <= slv_reg163;
when b"010100100" =>
reg_data_out <= slv_reg164;
when b"010100101" =>
reg_data_out <= slv_reg165;
when b"010100110" =>
reg_data_out <= slv_reg166;
when b"010100111" =>
reg_data_out <= slv_reg167;
when b"010101000" =>
reg_data_out <= slv_reg168;
when b"010101001" =>
reg_data_out <= slv_reg169;
when b"010101010" =>
reg_data_out <= slv_reg170;
when b"010101011" =>
reg_data_out <= slv_reg171;
when b"010101100" =>
reg_data_out <= slv_reg172;
when b"010101101" =>
reg_data_out <= slv_reg173;
when b"010101110" =>
reg_data_out <= slv_reg174;
when b"010101111" =>
reg_data_out <= slv_reg175;
when b"010110000" =>
reg_data_out <= slv_reg176;
when b"010110001" =>
reg_data_out <= slv_reg177;
when b"010110010" =>
reg_data_out <= slv_reg178;
when b"010110011" =>
reg_data_out <= slv_reg179;
when b"010110100" =>
reg_data_out <= slv_reg180;
when b"010110101" =>
reg_data_out <= slv_reg181;
when b"010110110" =>
reg_data_out <= slv_reg182;
when b"010110111" =>
reg_data_out <= slv_reg183;
when b"010111000" =>
reg_data_out <= slv_reg184;
when b"010111001" =>
reg_data_out <= slv_reg185;
when b"010111010" =>
reg_data_out <= slv_reg186;
when b"010111011" =>
reg_data_out <= slv_reg187;
when b"010111100" =>
reg_data_out <= slv_reg188;
when b"010111101" =>
reg_data_out <= slv_reg189;
when b"010111110" =>
reg_data_out <= slv_reg190;
when b"010111111" =>
reg_data_out <= slv_reg191;
when b"011000000" =>
reg_data_out <= slv_reg192;
when b"011000001" =>
reg_data_out <= slv_reg193;
when b"011000010" =>
reg_data_out <= slv_reg194;
when b"011000011" =>
reg_data_out <= slv_reg195;
when b"011000100" =>
reg_data_out <= slv_reg196;
when b"011000101" =>
reg_data_out <= slv_reg197;
when b"011000110" =>
reg_data_out <= slv_reg198;
when b"011000111" =>
reg_data_out <= slv_reg199;
when b"011001000" =>
reg_data_out <= slv_reg200;
when b"011001001" =>
reg_data_out <= slv_reg201;
when b"011001010" =>
reg_data_out <= slv_reg202;
when b"011001011" =>
reg_data_out <= slv_reg203;
when b"011001100" =>
reg_data_out <= slv_reg204;
when b"011001101" =>
reg_data_out <= slv_reg205;
when b"011001110" =>
reg_data_out <= slv_reg206;
when b"011001111" =>
reg_data_out <= slv_reg207;
when b"011010000" =>
reg_data_out <= slv_reg208;
when b"011010001" =>
reg_data_out <= slv_reg209;
when b"011010010" =>
reg_data_out <= slv_reg210;
when b"011010011" =>
reg_data_out <= slv_reg211;
when b"011010100" =>
reg_data_out <= slv_reg212;
when b"011010101" =>
reg_data_out <= slv_reg213;
when b"011010110" =>
reg_data_out <= slv_reg214;
when b"011010111" =>
reg_data_out <= slv_reg215;
when b"011011000" =>
reg_data_out <= slv_reg216;
when b"011011001" =>
reg_data_out <= slv_reg217;
when b"011011010" =>
reg_data_out <= slv_reg218;
when b"011011011" =>
reg_data_out <= slv_reg219;
when b"011011100" =>
reg_data_out <= slv_reg220;
when b"011011101" =>
reg_data_out <= slv_reg221;
when b"011011110" =>
reg_data_out <= slv_reg222;
when b"011011111" =>
reg_data_out <= slv_reg223;
when b"011100000" =>
reg_data_out <= slv_reg224;
when b"011100001" =>
reg_data_out <= slv_reg225;
when b"011100010" =>
reg_data_out <= slv_reg226;
when b"011100011" =>
reg_data_out <= slv_reg227;
when b"011100100" =>
reg_data_out <= slv_reg228;
when b"011100101" =>
reg_data_out <= slv_reg229;
when b"011100110" =>
reg_data_out <= slv_reg230;
when b"011100111" =>
reg_data_out <= slv_reg231;
when b"011101000" =>
reg_data_out <= slv_reg232;
when b"011101001" =>
reg_data_out <= slv_reg233;
when b"011101010" =>
reg_data_out <= slv_reg234;
when b"011101011" =>
reg_data_out <= slv_reg235;
when b"011101100" =>
reg_data_out <= slv_reg236;
when b"011101101" =>
reg_data_out <= slv_reg237;
when b"011101110" =>
reg_data_out <= slv_reg238;
when b"011101111" =>
reg_data_out <= slv_reg239;
when b"011110000" =>
reg_data_out <= slv_reg240;
when b"011110001" =>
reg_data_out <= slv_reg241;
when b"011110010" =>
reg_data_out <= slv_reg242;
when b"011110011" =>
reg_data_out <= slv_reg243;
when b"011110100" =>
reg_data_out <= slv_reg244;
when b"011110101" =>
reg_data_out <= slv_reg245;
when b"011110110" =>
reg_data_out <= slv_reg246;
when b"011110111" =>
reg_data_out <= slv_reg247;
when b"011111000" =>
reg_data_out <= slv_reg248;
when b"011111001" =>
reg_data_out <= slv_reg249;
when b"011111010" =>
reg_data_out <= slv_reg250;
when b"011111011" =>
reg_data_out <= slv_reg251;
when b"011111100" =>
reg_data_out <= slv_reg252;
when b"011111101" =>
reg_data_out <= slv_reg253;
when b"011111110" =>
reg_data_out <= slv_reg254;
when b"011111111" =>
reg_data_out <= slv_reg255;
when b"100000000" =>
reg_data_out <= slv_reg256;
when b"100000001" =>
reg_data_out <= slv_reg257;
when b"100000010" =>
reg_data_out <= slv_reg258;
when b"100000011" =>
reg_data_out <= slv_reg259;
when b"100000100" =>
reg_data_out <= slv_reg260;
when b"100000101" =>
reg_data_out <= slv_reg261;
when b"100000110" =>
reg_data_out <= slv_reg262;
when b"100000111" =>
reg_data_out <= slv_reg263;
when b"100001000" =>
reg_data_out <= slv_reg264;
when b"100001001" =>
reg_data_out <= slv_reg265;
when b"100001010" =>
reg_data_out <= slv_reg266;
when b"100001011" =>
reg_data_out <= slv_reg267;
when b"100001100" =>
reg_data_out <= slv_reg268;
when b"100001101" =>
reg_data_out <= slv_reg269;
when b"100001110" =>
reg_data_out <= slv_reg270;
when b"100001111" =>
reg_data_out <= slv_reg271;
when b"100010000" =>
reg_data_out <= slv_reg272;
when b"100010001" =>
reg_data_out <= slv_reg273;
when b"100010010" =>
reg_data_out <= slv_reg274;
when b"100010011" =>
reg_data_out <= slv_reg275;
when b"100010100" =>
reg_data_out <= slv_reg276;
when b"100010101" =>
reg_data_out <= slv_reg277;
when b"100010110" =>
reg_data_out <= slv_reg278;
when b"100010111" =>
reg_data_out <= slv_reg279;
when b"100011000" =>
reg_data_out <= slv_reg280;
when b"100011001" =>
reg_data_out <= slv_reg281;
when b"100011010" =>
reg_data_out <= slv_reg282;
when b"100011011" =>
reg_data_out <= slv_reg283;
when b"100011100" =>
reg_data_out <= slv_reg284;
when b"100011101" =>
reg_data_out <= slv_reg285;
when b"100011110" =>
reg_data_out <= slv_reg286;
when b"100011111" =>
reg_data_out <= slv_reg287;
when b"100100000" =>
reg_data_out <= slv_reg288;
when b"100100001" =>
reg_data_out <= slv_reg289;
when b"100100010" =>
reg_data_out <= slv_reg290;
when b"100100011" =>
reg_data_out <= slv_reg291;
when b"100100100" =>
reg_data_out <= slv_reg292;
when b"100100101" =>
reg_data_out <= slv_reg293;
when b"100100110" =>
reg_data_out <= slv_reg294;
when b"100100111" =>
reg_data_out <= slv_reg295;
when b"100101000" =>
reg_data_out <= slv_reg296;
when b"100101001" =>
reg_data_out <= slv_reg297;
when b"100101010" =>
reg_data_out <= slv_reg298;
when b"100101011" =>
reg_data_out <= slv_reg299;
when b"100101100" =>
reg_data_out <= slv_reg300;
when b"100101101" =>
reg_data_out <= slv_reg301;
when b"100101110" =>
reg_data_out <= slv_reg302;
when b"100101111" =>
reg_data_out <= slv_reg303;
when b"100110000" =>
reg_data_out <= slv_reg304;
when b"100110001" =>
reg_data_out <= slv_reg305;
when b"100110010" =>
reg_data_out <= slv_reg306;
when b"100110011" =>
reg_data_out <= slv_reg307;
when b"100110100" =>
reg_data_out <= slv_reg308;
when b"100110101" =>
reg_data_out <= slv_reg309;
when b"100110110" =>
reg_data_out <= slv_reg310;
when b"100110111" =>
reg_data_out <= slv_reg311;
when b"100111000" =>
reg_data_out <= slv_reg312;
when b"100111001" =>
reg_data_out <= slv_reg313;
when b"100111010" =>
reg_data_out <= slv_reg314;
when b"100111011" =>
reg_data_out <= slv_reg315;
when b"100111100" =>
reg_data_out <= slv_reg316;
when b"100111101" =>
reg_data_out <= slv_reg317;
when b"100111110" =>
reg_data_out <= slv_reg318;
when b"100111111" =>
reg_data_out <= slv_reg319;
when b"101000000" =>
reg_data_out <= slv_reg320;
when b"101000001" =>
reg_data_out <= slv_reg321;
when b"101000010" =>
reg_data_out <= slv_reg322;
when b"101000011" =>
reg_data_out <= slv_reg323;
when b"101000100" =>
reg_data_out <= slv_reg324;
when b"101000101" =>
reg_data_out <= slv_reg325;
when b"101000110" =>
reg_data_out <= slv_reg326;
when b"101000111" =>
reg_data_out <= slv_reg327;
when b"101001000" =>
reg_data_out <= slv_reg328;
when b"101001001" =>
reg_data_out <= slv_reg329;
when b"101001010" =>
reg_data_out <= slv_reg330;
when b"101001011" =>
reg_data_out <= slv_reg331;
when b"101001100" =>
reg_data_out <= slv_reg332;
when b"101001101" =>
reg_data_out <= slv_reg333;
when b"101001110" =>
reg_data_out <= slv_reg334;
when b"101001111" =>
reg_data_out <= slv_reg335;
when b"101010000" =>
reg_data_out <= slv_reg336;
when b"101010001" =>
reg_data_out <= slv_reg337;
when b"101010010" =>
reg_data_out <= slv_reg338;
when b"101010011" =>
reg_data_out <= slv_reg339;
when b"101010100" =>
reg_data_out <= slv_reg340;
when b"101010101" =>
reg_data_out <= slv_reg341;
when b"101010110" =>
reg_data_out <= slv_reg342;
when b"101010111" =>
reg_data_out <= slv_reg343;
when b"101011000" =>
reg_data_out <= slv_reg344;
when b"101011001" =>
reg_data_out <= slv_reg345;
when b"101011010" =>
reg_data_out <= slv_reg346;
when b"101011011" =>
reg_data_out <= slv_reg347;
when b"101011100" =>
reg_data_out <= slv_reg348;
when b"101011101" =>
reg_data_out <= slv_reg349;
when b"101011110" =>
reg_data_out <= slv_reg350;
when b"101011111" =>
reg_data_out <= slv_reg351;
when b"101100000" =>
reg_data_out <= slv_reg352;
when b"101100001" =>
reg_data_out <= slv_reg353;
when b"101100010" =>
reg_data_out <= slv_reg354;
when b"101100011" =>
reg_data_out <= slv_reg355;
when b"101100100" =>
reg_data_out <= slv_reg356;
when b"101100101" =>
reg_data_out <= slv_reg357;
when b"101100110" =>
reg_data_out <= slv_reg358;
when b"101100111" =>
reg_data_out <= slv_reg359;
when b"101101000" =>
reg_data_out <= slv_reg360;
when b"101101001" =>
reg_data_out <= slv_reg361;
when b"101101010" =>
reg_data_out <= slv_reg362;
when b"101101011" =>
reg_data_out <= slv_reg363;
when b"101101100" =>
reg_data_out <= slv_reg364;
when b"101101101" =>
reg_data_out <= slv_reg365;
when b"101101110" =>
reg_data_out <= slv_reg366;
when b"101101111" =>
reg_data_out <= slv_reg367;
when b"101110000" =>
reg_data_out <= slv_reg368;
when b"101110001" =>
reg_data_out <= slv_reg369;
when b"101110010" =>
reg_data_out <= slv_reg370;
when b"101110011" =>
reg_data_out <= slv_reg371;
when b"101110100" =>
reg_data_out <= slv_reg372;
when b"101110101" =>
reg_data_out <= slv_reg373;
when b"101110110" =>
reg_data_out <= slv_reg374;
when b"101110111" =>
reg_data_out <= slv_reg375;
when b"101111000" =>
reg_data_out <= slv_reg376;
when b"101111001" =>
reg_data_out <= slv_reg377;
when b"101111010" =>
reg_data_out <= slv_reg378;
when b"101111011" =>
reg_data_out <= slv_reg379;
when b"101111100" =>
reg_data_out <= slv_reg380;
when b"101111101" =>
reg_data_out <= slv_reg381;
when b"101111110" =>
reg_data_out <= slv_reg382;
when b"101111111" =>
reg_data_out <= slv_reg383;
when b"110000000" =>
reg_data_out <= slv_reg384;
when b"110000001" =>
reg_data_out <= slv_reg385;
when b"110000010" =>
reg_data_out <= slv_reg386;
when b"110000011" =>
reg_data_out <= slv_reg387;
when b"110000100" =>
reg_data_out <= slv_reg388;
when b"110000101" =>
reg_data_out <= slv_reg389;
when b"110000110" =>
reg_data_out <= slv_reg390;
when b"110000111" =>
reg_data_out <= slv_reg391;
when b"110001000" =>
reg_data_out <= slv_reg392;
when b"110001001" =>
reg_data_out <= slv_reg393;
when b"110001010" =>
reg_data_out <= slv_reg394;
when b"110001011" =>
reg_data_out <= slv_reg395;
when b"110001100" =>
reg_data_out <= slv_reg396;
when b"110001101" =>
reg_data_out <= slv_reg397;
when b"110001110" =>
reg_data_out <= slv_reg398;
when b"110001111" =>
reg_data_out <= slv_reg399;
when b"110010000" =>
reg_data_out <= slv_reg400;
when b"110010001" =>
reg_data_out <= slv_reg401;
when b"110010010" =>
reg_data_out <= slv_reg402;
when b"110010011" =>
reg_data_out <= slv_reg403;
when b"110010100" =>
reg_data_out <= slv_reg404;
when b"110010101" =>
reg_data_out <= slv_reg405;
when b"110010110" =>
reg_data_out <= slv_reg406;
when b"110010111" =>
reg_data_out <= slv_reg407;
when b"110011000" =>
reg_data_out <= slv_reg408;
when b"110011001" =>
reg_data_out <= slv_reg409;
when b"110011010" =>
reg_data_out <= slv_reg410;
when b"110011011" =>
reg_data_out <= slv_reg411;
when b"110011100" =>
reg_data_out <= slv_reg412;
when b"110011101" =>
reg_data_out <= slv_reg413;
when b"110011110" =>
reg_data_out <= slv_reg414;
when b"110011111" =>
reg_data_out <= slv_reg415;
when b"110100000" =>
reg_data_out <= slv_reg416;
when b"110100001" =>
reg_data_out <= slv_reg417;
when b"110100010" =>
reg_data_out <= slv_reg418;
when b"110100011" =>
reg_data_out <= slv_reg419;
when b"110100100" =>
reg_data_out <= slv_reg420;
when b"110100101" =>
reg_data_out <= slv_reg421;
when b"110100110" =>
reg_data_out <= slv_reg422;
when b"110100111" =>
reg_data_out <= slv_reg423;
when b"110101000" =>
reg_data_out <= slv_reg424;
when b"110101001" =>
reg_data_out <= slv_reg425;
when b"110101010" =>
reg_data_out <= slv_reg426;
when b"110101011" =>
reg_data_out <= slv_reg427;
when b"110101100" =>
reg_data_out <= slv_reg428;
when b"110101101" =>
reg_data_out <= slv_reg429;
when b"110101110" =>
reg_data_out <= slv_reg430;
when b"110101111" =>
reg_data_out <= slv_reg431;
when b"110110000" =>
reg_data_out <= slv_reg432;
when b"110110001" =>
reg_data_out <= slv_reg433;
when b"110110010" =>
reg_data_out <= slv_reg434;
when b"110110011" =>
reg_data_out <= slv_reg435;
when b"110110100" =>
reg_data_out <= slv_reg436;
when b"110110101" =>
reg_data_out <= slv_reg437;
when b"110110110" =>
reg_data_out <= slv_reg438;
when b"110110111" =>
reg_data_out <= slv_reg439;
when b"110111000" =>
reg_data_out <= slv_reg440;
when b"110111001" =>
reg_data_out <= slv_reg441;
when b"110111010" =>
reg_data_out <= slv_reg442;
when b"110111011" =>
reg_data_out <= slv_reg443;
when b"110111100" =>
reg_data_out <= slv_reg444;
when b"110111101" =>
reg_data_out <= slv_reg445;
when b"110111110" =>
reg_data_out <= slv_reg446;
when b"110111111" =>
reg_data_out <= slv_reg447;
when b"111000000" =>
reg_data_out <= slv_reg448;
when b"111000001" =>
reg_data_out <= slv_reg449;
when b"111000010" =>
reg_data_out <= slv_reg450;
when b"111000011" =>
reg_data_out <= slv_reg451;
when b"111000100" =>
reg_data_out <= slv_reg452;
when b"111000101" =>
reg_data_out <= slv_reg453;
when b"111000110" =>
reg_data_out <= slv_reg454;
when b"111000111" =>
reg_data_out <= slv_reg455;
when b"111001000" =>
reg_data_out <= slv_reg456;
when b"111001001" =>
reg_data_out <= slv_reg457;
when b"111001010" =>
reg_data_out <= slv_reg458;
when b"111001011" =>
reg_data_out <= slv_reg459;
when b"111001100" =>
reg_data_out <= slv_reg460;
when b"111001101" =>
reg_data_out <= slv_reg461;
when b"111001110" =>
reg_data_out <= slv_reg462;
when b"111001111" =>
reg_data_out <= slv_reg463;
when b"111010000" =>
reg_data_out <= slv_reg464;
when b"111010001" =>
reg_data_out <= slv_reg465;
when b"111010010" =>
reg_data_out <= slv_reg466;
when b"111010011" =>
reg_data_out <= slv_reg467;
when b"111010100" =>
reg_data_out <= slv_reg468;
when b"111010101" =>
reg_data_out <= slv_reg469;
when b"111010110" =>
reg_data_out <= slv_reg470;
when b"111010111" =>
reg_data_out <= slv_reg471;
when b"111011000" =>
reg_data_out <= slv_reg472;
when b"111011001" =>
reg_data_out <= slv_reg473;
when b"111011010" =>
reg_data_out <= slv_reg474;
when b"111011011" =>
reg_data_out <= slv_reg475;
when b"111011100" =>
reg_data_out <= slv_reg476;
when b"111011101" =>
reg_data_out <= slv_reg477;
when b"111011110" =>
reg_data_out <= slv_reg478;
when b"111011111" =>
reg_data_out <= slv_reg479;
when b"111100000" =>
reg_data_out <= slv_reg480;
when b"111100001" =>
reg_data_out <= slv_reg481;
when b"111100010" =>
reg_data_out <= slv_reg482;
when b"111100011" =>
reg_data_out <= slv_reg483;
when b"111100100" =>
reg_data_out <= slv_reg484;
when b"111100101" =>
reg_data_out <= slv_reg485;
when b"111100110" =>
reg_data_out <= slv_reg486;
when b"111100111" =>
reg_data_out <= slv_reg487;
when b"111101000" =>
reg_data_out <= slv_reg488;
when b"111101001" =>
reg_data_out <= slv_reg489;
when b"111101010" =>
reg_data_out <= slv_reg490;
when b"111101011" =>
reg_data_out <= slv_reg491;
when b"111101100" =>
reg_data_out <= slv_reg492;
when b"111101101" =>
reg_data_out <= slv_reg493;
when b"111101110" =>
reg_data_out <= slv_reg494;
when b"111101111" =>
reg_data_out <= slv_reg495;
when b"111110000" =>
reg_data_out <= slv_reg496;
when b"111110001" =>
reg_data_out <= slv_reg497;
when b"111110010" =>
reg_data_out <= slv_reg498;
when b"111110011" =>
reg_data_out <= slv_reg499;
when b"111110100" =>
reg_data_out <= slv_reg500;
when b"111110101" =>
reg_data_out <= slv_reg501;
when b"111110110" =>
reg_data_out <= slv_reg502;
when b"111110111" =>
reg_data_out <= slv_reg503;
when b"111111000" =>
reg_data_out <= slv_reg504;
when b"111111001" =>
reg_data_out <= slv_reg505;
when b"111111010" =>
reg_data_out <= slv_reg506;
when b"111111011" =>
reg_data_out <= slv_reg507;
when b"111111100" =>
reg_data_out <= slv_reg508;
when b"111111101" =>
reg_data_out <= slv_reg509;
when b"111111110" =>
reg_data_out <= slv_reg510;
when b"111111111" =>
reg_data_out <= slv_reg511;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End Pass-through architecture |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end add_203;
architecture augh of add_203 is
signal carry_inA : std_logic_vector(40 downto 0);
signal carry_inB : std_logic_vector(40 downto 0);
signal carry_res : std_logic_vector(40 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
output <= carry_res(39 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end add_203;
architecture augh of add_203 is
signal carry_inA : std_logic_vector(40 downto 0);
signal carry_inB : std_logic_vector(40 downto 0);
signal carry_res : std_logic_vector(40 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
output <= carry_res(39 downto 1);
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_09 is
end entity fg_a_09;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_09 is
signal clk25M, resetl : std_ulogic;
signal data, odat : std_ulogic_vector(7 downto 0);
begin
-- code from book
wrong_way : process ( clk25M, resetl, data )
begin
if resetl = '0' then
odat <= B"0000_0000";
elsif rising_edge(clk25M) then
odat <= data;
elsif data = B"0000_0000" then
odat <= B"0000_0001";
end if;
end process wrong_way;
-- end code from book
data <= odat(6 downto 0) & '0';
clk_gen : process is
begin
clk25M <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
resetl <= '1', '0' after 20 ns, '1' after 60 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_09 is
end entity fg_a_09;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_09 is
signal clk25M, resetl : std_ulogic;
signal data, odat : std_ulogic_vector(7 downto 0);
begin
-- code from book
wrong_way : process ( clk25M, resetl, data )
begin
if resetl = '0' then
odat <= B"0000_0000";
elsif rising_edge(clk25M) then
odat <= data;
elsif data = B"0000_0000" then
odat <= B"0000_0001";
end if;
end process wrong_way;
-- end code from book
data <= odat(6 downto 0) & '0';
clk_gen : process is
begin
clk25M <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
resetl <= '1', '0' after 20 ns, '1' after 60 ns;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_09 is
end entity fg_a_09;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_09 is
signal clk25M, resetl : std_ulogic;
signal data, odat : std_ulogic_vector(7 downto 0);
begin
-- code from book
wrong_way : process ( clk25M, resetl, data )
begin
if resetl = '0' then
odat <= B"0000_0000";
elsif rising_edge(clk25M) then
odat <= data;
elsif data = B"0000_0000" then
odat <= B"0000_0001";
end if;
end process wrong_way;
-- end code from book
data <= odat(6 downto 0) & '0';
clk_gen : process is
begin
clk25M <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
resetl <= '1', '0' after 20 ns, '1' after 60 ns;
end architecture test;
|
entity foo is
end;
architecture bar of foo is
type bit is range 0 to 1;
signal a : bit;
begin
stim : process
begin
a <= 0;
a <= 1 after 10 ns;
--a <= 0 after 0; -- this should be a type error
end process;
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for PADS_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template
--
-- Generator: mix_0.pl /mix/0.1, [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
--
--
-- Start of Generated Architecture PADS_struct
--
architecture PADS_struct of PADS is
--
-- Components
--
-- Generated Components
component padcell
port (
-- generated
-- NO OUT PORTs : ;
EI : in std_ulogic;
EO : out std_ulogic
-- end of generated port
);
end component;
-- ---------
component padcell_4_e
port (
-- generated
EI : in std_ulogic;
EO : out std_ulogic
-- end of generated port
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signals
--
signal __LOGIC0__ : __E_TYPE_MISMATCH(3 downto 0);
signal pad_conn_1_2 : std_ulogic;
signal pad_conn_2_3 : std_ulogic;
signal pad_conn_3_4 : std_ulogic;
signal pad_conn_4_5 : std_ulogic;
signal pad_conn_5_6 : std_ulogic;
signal pad_conn_6_7 : std_ulogic;
signal pad_conn_7_8 : std_ulogic;
signal pad_conn_8_9 : std_ulogic;
signal pad_conn_9_10 : std_ulogic;
--
-- End of Generated Signals
--
-- %CONSTANTS%
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
__LOGIC0__ <= '0';
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for Pad_1
Pad_1: padcell PORT MAP(
EI => __LOGIC0__,
EO => pad_conn_1_2
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_10
Pad_10: padcell PORT MAP(
EI => pad_conn_9_10
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_2
Pad_2: padcell PORT MAP(
EI => pad_conn_1_2,
EO => pad_conn_2_3
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_3
Pad_3: padcell PORT MAP(
EI => pad_conn_2_3,
EO => pad_conn_3_4
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_4
Pad_4: padcell_4_e PORT MAP(
EI => pad_conn_3_4,
EO => pad_conn_4_5
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_5
Pad_5: padcell PORT MAP(
EI => pad_conn_4_5,
EO => pad_conn_5_6
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_6
Pad_6: padcell PORT MAP(
EI => pad_conn_5_6,
EO => pad_conn_6_7
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_7
Pad_7: padcell PORT MAP(
EI => pad_conn_6_7,
EO => pad_conn_7_8
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_8
Pad_8: padcell PORT MAP(
EI => pad_conn_7_8,
EO => pad_conn_8_9
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_9
Pad_9: padcell PORT MAP(
EI => pad_conn_8_9,
EO => pad_conn_9_10
);
-- End of Generated Instance Port Map
end PADS_struct;
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux2x16 is
port(
i0 : in std_logic_vector(15 downto 0);
i1 : in std_logic_vector(15 downto 0);
sel : in std_logic;
o : out std_logic_vector(15 downto 0)
);
end mux2x16;
architecture synth of mux2x16 is
begin
o <= i0 when sel = '0' else i1;
end synth;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:20:30 11/19/2013
-- Design Name:
-- Module Name: My_32bit2x1Mux_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_32bit2x1Mux_948282 is
Port ( B_inv : in STD_LOGIC;
B : in STD_LOGIC_VECTOR (31 downto 0);
B_comp : in STD_LOGIC_VECTOR (31 downto 0);
B_out : out STD_LOGIC_VECTOR (31 downto 0));
end My_32bit2x1Mux_948282;
architecture Behavioral of My_32bit2x1Mux_948282 is
component My_32bitOr_948282 is
Port ( inA_8282 : in STD_LOGIC_VECTOR (31 downto 0);
inB_8282 : in STD_LOGIC_VECTOR (31 downto 0);
outR_8282 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component My_32bitAnd_948282 is
Port ( A_8282 : in STD_LOGIC_VECTOR (31 downto 0);
B_8282 : in STD_LOGIC_VECTOR (31 downto 0);
R_8282 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myNOT_948282 is
Port ( i1 : in STD_LOGIC;
o1 : out STD_LOGIC);
end component;
component Extend_1to16bits is
Port ( In_1bit : in STD_LOGIC;
Out_16bit : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal sig11, sig22, sig2, sig5: std_logic_vector(31 downto 0);
signal sig3, sig3b, sig1b, sig1: std_logic_vector(15 downto 0);
signal sig4, sig6, sig7: std_logic;
begin
u0: Extend_1to16bits port map (In_1bit=>B_inv, Out_16bit=>sig1);
u2: sig11(15 downto 0)<=sig1;
u3: sig11(31 downto 16)<=sig1;
u4: My_32bitAnd_948282 port map (A_8282=>B_comp, B_8282=>sig11, R_8282=>sig2);--sig2 in or
u5: myNot_948282 port map (i1=>B_inv, o1=>sig4);
u6: Extend_1to16bits port map (In_1bit=>sig4, Out_16bit=>sig3b);
u7: sig22(15 downto 0)<=sig3b;
u8: sig22(31 downto 16)<=sig3b;
u9: My_32bitAnd_948282 port map (A_8282=>B, B_8282=>sig22, R_8282=>sig5);--sig5 in or
u10: My_32bitOr_948282 port map (inA_8282=>sig2, inB_8282=>sig5, outR_8282=>B_out);
end Behavioral;
|
entity bug2 is
end entity bug2;
architecture x of bug2 is
type bit_position is (msb);
signal test : integer;
begin
test <= msb;
end architecture x;
|
entity bug2 is
end entity bug2;
architecture x of bug2 is
type bit_position is (msb);
signal test : integer;
begin
test <= msb;
end architecture x;
|
-- $Id: sys_conf_sim.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-28 295 1.0 Initial version (cloned from _s3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_clkfx_divide : positive := 25;
-- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
-------------------------------------------------------------------------------
-- xip_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi in XIP mode.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
--library unisim;
-- use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_XIP_SPICR_REG_WIDTH -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_XIPCR_data -- Data written from the PLB bus
-- Bus2IP_XIPCR_WrCE -- Write CE for control register
-- Bus2IP_XIPCR_RdCE -- Read CE for control register
-- IP2Bus_XIPCR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register,10 for control reg - 8 for cmd + 2 CPOL/CPHA
C_XIP_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_XIPCR_WrCE : in std_logic;
Bus2IP_XIPCR_RdCE : in std_logic;
Bus2IP_XIPCR_data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
ip2Bus_RdAck_core : in std_logic;
ip2Bus_WrAck_core : in std_logic;
XIPCR_1_CPOL : out std_logic;
XIPCR_0_CPHA : out std_logic;
--------------------------
IP2Bus_XIPCR_Data : out std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
--------------------------
TO_XIPSR_CPHA_CPOL_ERR : out std_logic
);
end xip_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of xip_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPCR_data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
-----
begin
-----
---------------------------------------
XIPCR_CPHA_CPOL_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH))
<= "00";
elsif(ip2Bus_WrAck_core = '1') and (Bus2IP_XIPCR_WrCE = '1')then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (0))
<= Bus2IP_XIPCR_data
((C_XIP_SPICR_REG_WIDTH-1) downto (0));
end if;
end if;
end process XIPCR_CPHA_CPOL_STORE_P;
------------------------------------
XIPCR_1_CPOL <= XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1);
XIPCR_0_CPHA <= XIPCR_data_int(0);
XIPCR_REG_RD_GENERATE: for i in C_XIP_SPICR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPCR_Data(i) <= XIPCR_data_int(i) and Bus2IP_XIPCR_RdCE;
end generate XIPCR_REG_RD_GENERATE;
-----------------------------------
TO_XIPSR_CPHA_CPOL_ERR <= (XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1)) xor
(XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH));
end imp;
--------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- xip_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi in XIP mode.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
--library unisim;
-- use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_XIP_SPICR_REG_WIDTH -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_XIPCR_data -- Data written from the PLB bus
-- Bus2IP_XIPCR_WrCE -- Write CE for control register
-- Bus2IP_XIPCR_RdCE -- Read CE for control register
-- IP2Bus_XIPCR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register,10 for control reg - 8 for cmd + 2 CPOL/CPHA
C_XIP_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_XIPCR_WrCE : in std_logic;
Bus2IP_XIPCR_RdCE : in std_logic;
Bus2IP_XIPCR_data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
ip2Bus_RdAck_core : in std_logic;
ip2Bus_WrAck_core : in std_logic;
XIPCR_1_CPOL : out std_logic;
XIPCR_0_CPHA : out std_logic;
--------------------------
IP2Bus_XIPCR_Data : out std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
--------------------------
TO_XIPSR_CPHA_CPOL_ERR : out std_logic
);
end xip_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of xip_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPCR_data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
-----
begin
-----
---------------------------------------
XIPCR_CPHA_CPOL_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH))
<= "00";
elsif(ip2Bus_WrAck_core = '1') and (Bus2IP_XIPCR_WrCE = '1')then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (0))
<= Bus2IP_XIPCR_data
((C_XIP_SPICR_REG_WIDTH-1) downto (0));
end if;
end if;
end process XIPCR_CPHA_CPOL_STORE_P;
------------------------------------
XIPCR_1_CPOL <= XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1);
XIPCR_0_CPHA <= XIPCR_data_int(0);
XIPCR_REG_RD_GENERATE: for i in C_XIP_SPICR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPCR_Data(i) <= XIPCR_data_int(i) and Bus2IP_XIPCR_RdCE;
end generate XIPCR_REG_RD_GENERATE;
-----------------------------------
TO_XIPSR_CPHA_CPOL_ERR <= (XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1)) xor
(XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH));
end imp;
--------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_dram_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth;
BURST_SIZE : positive := 4;
THRESHOLD : positive := 4;
FIFO_SIZE : positive := 8_000_000;
SYNC_LOGIC_INTERFACE : boolean := false;
IS_READ : boolean := true ;
sdram_address_width : positive := 24;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0')
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
write_fifo, read_fifo : in std_logic ;
fifo_input: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
fifo_output : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
fifo_empty, fifo_full : out std_logic ;
fifo_reset : out std_logic ;
fifo_threshold : out std_logic;
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end wishbone_dram_fifo;
architecture RTL of wishbone_dram_fifo is
component dram_fifo is
generic(CACHE_SIZE : positive := 2048;
FIFO_SIZE : positive := 8_000_000;
sdram_address_width : positive := 24;
SYNC_READ : boolean := true;
SYNC_WRITE : boolean := true;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- FIFO interface
reset_fifo : in std_logic ;
write_fifo, read_fifo : in std_logic ;
nb_available : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end component;
constant address_space_nbit : integer := MAX((nbit(BURST_SIZE)+1), 3);
signal read_from_bus, write_from_bus, reset_fifo: std_logic ;
signal data_from_bus, data_to_bus : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_available_fifo : std_logic_vector(31 downto 0 );
signal write_ack, read_ack, read_ack_old, write_ack_old, write_ack_re, read_ack_fe : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal control_space_data_spacen : std_logic ;
begin
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
write_ack_old <= write_ack ;
end if;
end process write_bloc;
write_ack_re <= (not write_ack_old) and write_ack ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0';
control_latched <= (others => '0');
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
read_ack_old <= read_ack ;
end if;
end process read_bloc;
read_ack_fe <= (not read_ack) and read_ack_old;
wbs_ack <= read_ack or write_ack;
gen_read_fifo : if IS_READ generate
fifo_read_from_bus : dram_fifo
generic map(CACHE_SIZE => 2048,
FIFO_SIZE => FIFO_SIZE,
sdram_address_width => 24,
SYNC_READ => false,
SYNC_WRITE => true,
CACHE_ADDRESS =>CACHE_ADDRESS)
port map(
clk => gls_clk,
reset => gls_reset,
-- FIFO interface
reset_fifo => reset_fifo,
write_fifo => write_fifo,
read_fifo => read_from_bus,
nb_available => nb_available_fifo,
data_out => data_to_bus, -- to bus
data_in => fifo_input, -- from logic
refresh_active => refresh_active,
flush_active => flush_active,
-- Interface to issue reads or write data
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
end generate ;
gen_write_fifo : if NOT IS_READ generate
fifo_write_from_bus : dram_fifo
generic map(CACHE_SIZE => 2048,
FIFO_SIZE => FIFO_SIZE,
sdram_address_width => 24,
SYNC_READ => true,
SYNC_WRITE => false,
CACHE_ADDRESS =>CACHE_ADDRESS)
port map(
clk => gls_clk,
reset => gls_reset,
-- FIFO interface
reset_fifo => reset_fifo,
write_fifo => write_from_bus,
read_fifo => read_fifo,
nb_available => nb_available_fifo,
data_out => fifo_output, -- to logic
data_in => data_from_bus, -- from bus
refresh_active => refresh_active,
flush_active => flush_active,
-- Interface to issue reads or write data
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
data_to_bus <= (others => '0');
end generate ;
control_space_data_spacen <= wbs_address((address_space_nbit-1)) ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_available_fifo(15 downto 0)) when wbs_address(1 downto 0)= "01" else
( nb_available_fifo(31 downto 16)) when wbs_address(1 downto 0)= "10" else
(others => '0');
wbs_readdata <= control_latched when control_space_data_spacen = '1' else
data_to_bus ;
--read_from_bus <= read_ack_fe when control_space_data_spacen = '0' else
-- '0' ;
read_from_bus <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
--write_from_bus <= write_ack_re when control_space_data_spacen = '0' else
-- '0' ;
write_from_bus <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' else
'0' ;
reset_fifo <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "01"else
'1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "10"else
'0' ;
fifo_reset <= reset_fifo ;
data_from_bus <= wbs_writedata ;
fifo_threshold <= '1' when nb_available_fifo > THRESHOLD else
'0' ;
fifo_full <= '1' when nb_available_fifo >= FIFO_SIZE else
'0' ;
end RTL;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_dram_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth;
BURST_SIZE : positive := 4;
THRESHOLD : positive := 4;
FIFO_SIZE : positive := 8_000_000;
SYNC_LOGIC_INTERFACE : boolean := false;
IS_READ : boolean := true ;
sdram_address_width : positive := 24;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0')
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
write_fifo, read_fifo : in std_logic ;
fifo_input: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
fifo_output : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
fifo_empty, fifo_full : out std_logic ;
fifo_reset : out std_logic ;
fifo_threshold : out std_logic;
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end wishbone_dram_fifo;
architecture RTL of wishbone_dram_fifo is
component dram_fifo is
generic(CACHE_SIZE : positive := 2048;
FIFO_SIZE : positive := 8_000_000;
sdram_address_width : positive := 24;
SYNC_READ : boolean := true;
SYNC_WRITE : boolean := true;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- FIFO interface
reset_fifo : in std_logic ;
write_fifo, read_fifo : in std_logic ;
nb_available : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end component;
constant address_space_nbit : integer := MAX((nbit(BURST_SIZE)+1), 3);
signal read_from_bus, write_from_bus, reset_fifo: std_logic ;
signal data_from_bus, data_to_bus : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_available_fifo : std_logic_vector(31 downto 0 );
signal write_ack, read_ack, read_ack_old, write_ack_old, write_ack_re, read_ack_fe : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal control_space_data_spacen : std_logic ;
begin
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
write_ack_old <= write_ack ;
end if;
end process write_bloc;
write_ack_re <= (not write_ack_old) and write_ack ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0';
control_latched <= (others => '0');
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
read_ack_old <= read_ack ;
end if;
end process read_bloc;
read_ack_fe <= (not read_ack) and read_ack_old;
wbs_ack <= read_ack or write_ack;
gen_read_fifo : if IS_READ generate
fifo_read_from_bus : dram_fifo
generic map(CACHE_SIZE => 2048,
FIFO_SIZE => FIFO_SIZE,
sdram_address_width => 24,
SYNC_READ => false,
SYNC_WRITE => true,
CACHE_ADDRESS =>CACHE_ADDRESS)
port map(
clk => gls_clk,
reset => gls_reset,
-- FIFO interface
reset_fifo => reset_fifo,
write_fifo => write_fifo,
read_fifo => read_from_bus,
nb_available => nb_available_fifo,
data_out => data_to_bus, -- to bus
data_in => fifo_input, -- from logic
refresh_active => refresh_active,
flush_active => flush_active,
-- Interface to issue reads or write data
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
end generate ;
gen_write_fifo : if NOT IS_READ generate
fifo_write_from_bus : dram_fifo
generic map(CACHE_SIZE => 2048,
FIFO_SIZE => FIFO_SIZE,
sdram_address_width => 24,
SYNC_READ => true,
SYNC_WRITE => false,
CACHE_ADDRESS =>CACHE_ADDRESS)
port map(
clk => gls_clk,
reset => gls_reset,
-- FIFO interface
reset_fifo => reset_fifo,
write_fifo => write_from_bus,
read_fifo => read_fifo,
nb_available => nb_available_fifo,
data_out => fifo_output, -- to logic
data_in => data_from_bus, -- from bus
refresh_active => refresh_active,
flush_active => flush_active,
-- Interface to issue reads or write data
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
data_to_bus <= (others => '0');
end generate ;
control_space_data_spacen <= wbs_address((address_space_nbit-1)) ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_available_fifo(15 downto 0)) when wbs_address(1 downto 0)= "01" else
( nb_available_fifo(31 downto 16)) when wbs_address(1 downto 0)= "10" else
(others => '0');
wbs_readdata <= control_latched when control_space_data_spacen = '1' else
data_to_bus ;
--read_from_bus <= read_ack_fe when control_space_data_spacen = '0' else
-- '0' ;
read_from_bus <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
--write_from_bus <= write_ack_re when control_space_data_spacen = '0' else
-- '0' ;
write_from_bus <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' else
'0' ;
reset_fifo <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "01"else
'1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "10"else
'0' ;
fifo_reset <= reset_fifo ;
data_from_bus <= wbs_writedata ;
fifo_threshold <= '1' when nb_available_fifo > THRESHOLD else
'0' ;
fifo_full <= '1' when nb_available_fifo >= FIFO_SIZE else
'0' ;
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc528.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00528ent IS
END c03s03b00x00p03n04i00528ent;
ARCHITECTURE c03s03b00x00p03n04i00528arch OF c03s03b00x00p03n04i00528ent IS
BEGIN
TESTING : PROCESS
type char_ptr is access character;
variable v_char_ptr1: char_ptr := new character'('a');
variable v_char_ptr2: char_ptr;
variable v_char_ptr3: char_ptr := v_char_ptr1;
variable v_char_ptr4: char_ptr := new character'('|');
variable OKtest : integer := 0;
BEGIN
assert v_char_ptr1.all = 'a';
if (v_char_ptr1.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr2 = null;
if (v_char_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_char_ptr3.all = 'a';
if (v_char_ptr3.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr4.all = '|';
if (v_char_ptr4.all = '|') then
OKtest := Oktest + 1;
end if;
v_char_ptr2 := new character'('K');
assert v_char_ptr2.all = 'K';
if (v_char_ptr2.all = 'K') then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr3.all) = "aa";
if ((v_char_ptr1.all & v_char_ptr3.all) = "aa") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr2.all) = "aK";
if ((v_char_ptr1.all & v_char_ptr2.all) = "aK") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr4.all) = "a|";
if ((v_char_ptr1.all & v_char_ptr4.all) = "a|") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all /= v_char_ptr4.all) = true;
if ((v_char_ptr1.all /= v_char_ptr4.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_char_ptr1);
deallocate(v_char_ptr2);
deallocate(v_char_ptr4);
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p03n04i00528"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p03n04i00528 - Character type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00528arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc528.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00528ent IS
END c03s03b00x00p03n04i00528ent;
ARCHITECTURE c03s03b00x00p03n04i00528arch OF c03s03b00x00p03n04i00528ent IS
BEGIN
TESTING : PROCESS
type char_ptr is access character;
variable v_char_ptr1: char_ptr := new character'('a');
variable v_char_ptr2: char_ptr;
variable v_char_ptr3: char_ptr := v_char_ptr1;
variable v_char_ptr4: char_ptr := new character'('|');
variable OKtest : integer := 0;
BEGIN
assert v_char_ptr1.all = 'a';
if (v_char_ptr1.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr2 = null;
if (v_char_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_char_ptr3.all = 'a';
if (v_char_ptr3.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr4.all = '|';
if (v_char_ptr4.all = '|') then
OKtest := Oktest + 1;
end if;
v_char_ptr2 := new character'('K');
assert v_char_ptr2.all = 'K';
if (v_char_ptr2.all = 'K') then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr3.all) = "aa";
if ((v_char_ptr1.all & v_char_ptr3.all) = "aa") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr2.all) = "aK";
if ((v_char_ptr1.all & v_char_ptr2.all) = "aK") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr4.all) = "a|";
if ((v_char_ptr1.all & v_char_ptr4.all) = "a|") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all /= v_char_ptr4.all) = true;
if ((v_char_ptr1.all /= v_char_ptr4.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_char_ptr1);
deallocate(v_char_ptr2);
deallocate(v_char_ptr4);
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p03n04i00528"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p03n04i00528 - Character type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00528arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc528.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00528ent IS
END c03s03b00x00p03n04i00528ent;
ARCHITECTURE c03s03b00x00p03n04i00528arch OF c03s03b00x00p03n04i00528ent IS
BEGIN
TESTING : PROCESS
type char_ptr is access character;
variable v_char_ptr1: char_ptr := new character'('a');
variable v_char_ptr2: char_ptr;
variable v_char_ptr3: char_ptr := v_char_ptr1;
variable v_char_ptr4: char_ptr := new character'('|');
variable OKtest : integer := 0;
BEGIN
assert v_char_ptr1.all = 'a';
if (v_char_ptr1.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr2 = null;
if (v_char_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_char_ptr3.all = 'a';
if (v_char_ptr3.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr4.all = '|';
if (v_char_ptr4.all = '|') then
OKtest := Oktest + 1;
end if;
v_char_ptr2 := new character'('K');
assert v_char_ptr2.all = 'K';
if (v_char_ptr2.all = 'K') then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr3.all) = "aa";
if ((v_char_ptr1.all & v_char_ptr3.all) = "aa") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr2.all) = "aK";
if ((v_char_ptr1.all & v_char_ptr2.all) = "aK") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr4.all) = "a|";
if ((v_char_ptr1.all & v_char_ptr4.all) = "a|") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all /= v_char_ptr4.all) = true;
if ((v_char_ptr1.all /= v_char_ptr4.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_char_ptr1);
deallocate(v_char_ptr2);
deallocate(v_char_ptr4);
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p03n04i00528"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p03n04i00528 - Character type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00528arch;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (
name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"
), (
name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"); -- Comment
begin
end architecture rtl;
|
-------------------------------------------------------------------------------
--
-- Title : fp23_fix2float
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : Signed fix 16 bit to float fp23 converter
--
-------------------------------------------------------------------------------
--
-- Version 1.0 25.05.2013
-- Description:
-- Bus width for:
-- din = 15
-- dout = 23
-- exp = 6
-- sign = 1
-- mant = 15 + 1
-- Math expression:
-- A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)
-- NB:
-- 1's complement
-- Converting from fixed to float takes only 9 clock cycles
--
-- MODES: Mode0 : normal fix2float (1's complement data)
-- Mode1 : +1 fix2float for negative data (uncomment and
-- change this code a little: add a component
-- sp_addsub_m1 and some signals): 2's complement data.
--
--
-- Version 1.1 15.01.2015
-- Description:
-- Based on fp27_fix2float_m3 (FP27 FORMAT)
-- New version of FP (Reduced fraction width)
--
-- Version 1.2 18.03.2015
-- Description:
-- Changed CE signal
-- This version has ena. See OR5+OR5 stages
--
-- Version 1.3 24.03.2015
-- Description:
-- Deleted ENABLE signal
-- This version is fully pipelined !!!
--
-- Version 1.4 04.10.2015
-- Description:
-- DSP48E1 has been removed. Barrel shift is used now.
-- Delay 9 clocks
--
-- Version 1.5 04.01.2016
-- Description:
-- New barrel shifter with minimum resources.
-- New FP format: FP24 -> FP23.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fp_m1_pkg.fp23_data;
use work.reduce_pack.nor_reduce;
entity fp23_fix2float is
port(
din : in std_logic_vector(15 downto 0); --! Fixed input data
ena : in std_logic; --! Data enable
dout : out fp23_data; --! Float output data
vld : out std_logic; --! Data out valid
clk : in std_logic; --! Clock
reset : in std_logic --! Negative Reset
);
end fp23_fix2float;
architecture fp23_fix2float of fp23_fix2float is
constant FP32_EXP : std_logic_vector(5 downto 0):="011111";
signal true_form : std_logic_vector(15 downto 0):=(others => '0');
signal norm : std_logic_vector(15 downto 0);
signal frac : std_logic_vector(15 downto 0);
signal set_zero : std_logic;
signal sum_man : std_logic_vector(15 downto 0);
signal msb_num : std_logic_vector(4 downto 0);
signal msb_numn : std_logic_vector(5 downto 0);
signal msb_numt : std_logic_vector(4 downto 0);
signal msb_numz : std_logic_vector(5 downto 0);
signal expc : std_logic_vector(5 downto 0); -- (E - 127) by (IEEE754)
signal sign : std_logic_vector(2 downto 0);
signal valid : std_logic_vector(4 downto 0);
--signal dinz : std_logic_vector(15 downto 0);
signal dinz : std_logic_vector(15 downto 0);
signal dinh : std_logic;
signal dinx : std_logic;
begin
-- x2S_COMPL: if (IS_CMPL = TRUE) generate
pr_sgn: process(clk) is
begin
if rising_edge(clk) then
dinz <= din - din(15);
dinh <= din(15);
end if;
end process;
---- make abs(data) by using XOR ----
pr_abs: process(clk) is
begin
if rising_edge(clk) then
true_form(15) <= dinz(15) or dinh;
for ii in 0 to 14 loop
true_form(ii) <= dinz(ii) xor (dinz(15) or dinh);
end loop;
end if;
end process;
sum_man <= true_form(14 downto 0) & '0' when rising_edge(clk);
---- find MSB (highest '1' position) ----
pr_lead: process(clk) is
begin
if rising_edge(clk) then
if (true_form(14-00)='1') then msb_num <= "00001";--"00010";--"00001";
elsif (true_form(14-01)='1') then msb_num <= "00010";--"00011";--"00010";
elsif (true_form(14-02)='1') then msb_num <= "00011";--"00100";--"00011";
elsif (true_form(14-03)='1') then msb_num <= "00100";--"00101";--"00100";
elsif (true_form(14-04)='1') then msb_num <= "00101";--"00110";--"00101";
elsif (true_form(14-05)='1') then msb_num <= "00110";--"00111";--"00110";
elsif (true_form(14-06)='1') then msb_num <= "00111";--"01000";--"00111";
elsif (true_form(14-07)='1') then msb_num <= "01000";--"01001";--"01000";
elsif (true_form(14-08)='1') then msb_num <= "01001";--"01010";--"01001";
elsif (true_form(14-09)='1') then msb_num <= "01010";--"01011";--"01010";
elsif (true_form(14-10)='1') then msb_num <= "01011";--"01100";--"01011";
elsif (true_form(14-11)='1') then msb_num <= "01100";--"01101";--"01100";
elsif (true_form(14-12)='1') then msb_num <= "01101";--"01110";--"01101";
elsif (true_form(14-13)='1') then msb_num <= "01110";--"01111";--"01110";
elsif (true_form(14-14)='1') then msb_num <= "01111";--"10000";--"01111";
else msb_num <= "00000";
end if;
end if;
end process;
dinx <= dinz(15) xor dinh when rising_edge(clk);
msb_numz(5) <= dinx when rising_edge(clk);
msb_numz(4 downto 0) <= msb_num;
msb_numt <= msb_num when rising_edge(clk);
---- barrel shifter by 0-15 ----
norm <= STD_LOGIC_VECTOR(SHL(UNSIGNED(sum_man), UNSIGNED(msb_num))) when rising_edge(clk);
frac <= norm when rising_edge(clk);
---- Check zero value for fraction and exponent ----
set_zero <= nor_reduce(msb_numz) when rising_edge(clk);
---- find exponent (inv msb - x"2E") ----
pr_sub: process(clk) is
begin
if rising_edge(clk) then
if (set_zero = '1') then
expc <= (others=>'0');
else
expc <= FP32_EXP - msb_numt;
end if;
end if;
end process;
---- sign delay ----
sign <= sign(sign'left-1 downto 0) & true_form(15) when rising_edge(clk);
---- output data ----
pr_out: process(clk) is
begin
if rising_edge(clk) then
if (reset = '1') then
dout <= ("000000", '0', x"0000");
elsif (valid(valid'left) = '1') then
dout <= (expc, sign(sign'left), frac);
end if;
end if;
end process;
valid <= valid(valid'left-1 downto 0) & ena when rising_edge(clk);
vld <= valid(valid'left) when rising_edge(clk);
end fp23_fix2float; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible.
entity sinewave is
port (clk :in std_logic;
dataout : out real
);
end sinewave;
architecture Behavioral of sinewave is
signal i : integer range 0 to 30:=0;
type memory_type is array (0 to 29) of real range -1.0 to 1.0;
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=(0.0,0.21,0.40,0.58,0.75,0.87,0.96,1.0,1.0,0.96,0.87,0.75,0.58,0.40,0.21,0.0,
-0.21,-0.40,-0.58,-0.75,-0.87,-0.96,-1.0,-1.0,-0.96,-0.87,-0.75,-0.58,-0.40,-0.21);
begin
process(clk)
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then
dataout <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Logic pulse sequencer
-- Pulls data out from memory and assumes it comes in with the following flow:
-- 1)Logic step values and little endian duration
-- 2)Rest of duration
-- If duration comes in as x"FFFF", read_addr is reset to 0 (it is up to the user to design software to insert this)
-- If duration comes in as x"FFFE", the 'running' state is paused to await for a new trigger ( " )
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity logic_processor is
port
(
-- Clock input
clk_sys : in std_logic;
-- reset trigger for logic process
iRST : in std_logic;
-- Memory data bus
-- 16 bit data input for logic sequence data
data_in : in std_logic_vector(15 downto 0);
-- Memory address location for DAC data from memory
read_addr_out : out std_logic_vector(9 downto 0);
-- Input to begin running waveforms from computer trigger
run_cmd : in std_logic;
-- Pulse sequencing ports
-- Input logic ports
iLogic : in std_logic_vector(1 downto 0);
-- Output logic ports
oLogic : out std_logic_vector(3 downto 0);
-- Logic for triggering the next waveform in memory
oDAC0_trigger : out std_logic;
oDAC1_trigger : out std_logic;
-- Logic derived from ADC values, designed to go 'high' when voltage below some value
iADC0_logic : in std_logic;
iADC1_logic : in std_logic;
-- Logic to enable the ADC interlock
ADC_active : out std_logic;
-- LEDs to display logic states
oLED : out std_logic_vector(5 downto 0)
);
end entity;
architecture rtl of logic_processor is
-- Internal copy of the address for reading from memory
signal read_addr : std_logic_vector((read_addr_out'length - 1) downto 0) := (others => '0');
-- Internal version of output logic for singal processing
signal Logic : std_logic_vector(3 downto 0) := (others => '0');
signal DAC_trigger : std_logic_vector(1 downto 0) := (others => '0');
-- Amount of clock cycles to read in new sequence
constant READ_TIME : std_logic_vector(23 downto 0) := x"000002";
begin
-- latch read address
read_addr_out <= read_addr;
-- push through input trigger to DAC
oDAC0_trigger <= iLogic(0) when DAC_trigger(0) = '0' else '1';
oDAC1_trigger <= iLogic(0) when DAC_trigger(1) = '0' else '1';
-- ADC-measurement dependent logic
oLogic(0) <= Logic(0) when iADC0_logic = '0' else '1';
oLogic(1) <= Logic(1) when iADC1_logic = '0' else '1';
oLogic(2) <= Logic(2);
oLogic(3) <= Logic(3);
-- Display logic states
oLED(3 downto 0) <= Logic;
oLED(5 downto 4) <= DAC_trigger;
process (clk_sys, run_cmd, iLogic(1), iRST)
-- States for the DAC
type RUN_STATES is (RESET, IDLE, RUNNING);
variable run_state : RUN_STATES := RESET;
-- States when pulling data out of memory
type READ_MODES is (READ_1, READ_2, DONE, NONE);
variable read_mode : READ_MODES := READ_1;
-- Data communication for the logic sequence
variable data_comm : std_logic_vector(15 downto 0);
-- The following are internal values for outputting to the DAC waveform
-- Voltage values go 15 downto 4, we have 3 downto 0 to hold decimal points in lower bits
variable logic_step : std_logic_vector(7 downto 0);
variable duration : std_logic_vector(23 downto 0);
-- "Reading" versions for reading memory while the DAC still runs the previous waveform cycle
variable logic_step_read : std_logic_vector(7 downto 0);
variable duration_read : std_logic_vector(23 downto 0);
-- Whether or not we need to be counting
variable timing : std_logic;
begin
-- check reset flag
if iRST = '0' then
run_state := RESET;
else
-- Logic sequence operations
if rising_edge(clk_sys) then
case run_state is
when RESET => -- Return to boot conditions
Logic <= (others => '0');
DAC_trigger <= (others => '0');
read_addr <= (others => '0');
run_state := IDLE;
when IDLE => -- Awaiting a run command
-- Prepare to begin reading data at start of 'running'
read_mode := READ_1;
-- No counting down when beginning to read a waveform
timing := '0';
-- Check if the next value on the memory register signifies the end of memory,
-- should be in the position to which READ_1 would point in memory
if data_in = x"FFFF" then
read_addr <= (others => '0');
end if;
-- Check conditions to run the waveform
if (run_cmd = '1' OR iLogic(1) = '1') then
run_state := RUNNING;
end if;
when RUNNING => -- RUNNING is interpreting data at the current address
-- Latch external waveform data
data_comm := data_in;
case read_mode is
when READ_1 =>
-- Read in the time to run the waveform
logic_step_read := data_comm(7 downto 0);
duration_read(7 downto 0) := data_comm(15 downto 8);
read_addr <= read_addr + '1';
-- Check if the time value flags the need to leave RUNNING
if data_comm >= x"FFFE" then
-- Await next run trigger
run_state := IDLE;
else
-- Read in the starting voltage
read_mode := READ_2;
end if;
when READ_2 =>
-- Read the voltage
duration_read(23 downto 8) := data_comm;
read_addr <= read_addr + '1';
-- Handling the case that duration - read_time < 0 to make sure we have time to load the next logic in each step
if duration < READ_TIME then
duration := READ_TIME;
end if;
-- Read in the slope
read_mode := DONE;
when DONE =>
-- Latch the read data into values used for writing to DACs
logic_step := logic_step_read;
-- If the next data requires waiting for a new trigger, need to allow the waveform to finish and then break to IDLE
if data_comm >= x"FFFE" then
duration := duration_read - 1 + READ_TIME;
else
duration := duration_read - 1;
end if;
-- We are going to be timing operation time
timing := '1';
-- Prepared to run the waveform
read_mode := NONE;
when NONE =>
-- Case statement at NONE should end with the read address for the next waveform's time
read_mode := NONE;
end case;
-- Output the logic vector
Logic <= logic_step(3 downto 0);
DAC_trigger <= logic_step(5 downto 4);
ADC_active <= logic_step(6);
if timing = '1' then
if duration <= READ_TIME then
--Start getting ready for the next round of data
timing := '0';
-- Clear DAC triggers
DAC_trigger <= (others => '0');
-- Read next pulse
read_mode := READ_1;
else -- Still waiting, so loop
duration := duration - 1;
read_mode := NONE;
end if;
end if;
end case;
end if;
end if;
end process;
end rtl;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:36:37 09/03/2011
-- Design Name:
-- Module Name: C:/Users/Digitales/Desktop/digPractica3/test.vhd
-- Project Name: Display
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: practica3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT practica3
PORT(
LED1 : IN std_logic;
LED2 : IN std_logic;
LED3 : IN std_logic;
LED4 : IN std_logic;
LED5 : IN std_logic;
LED6 : IN std_logic;
LED7 : IN std_logic;
SEGA : OUT std_logic;
SEGB : OUT std_logic;
SEGC : OUT std_logic;
SEGD : OUT std_logic;
SEGE : OUT std_logic;
SEGF : OUT std_logic;
SEGG : OUT std_logic
);
END COMPONENT;
--Inputs
signal LED1 : std_logic := '0';
signal LED2 : std_logic := '0';
signal LED3 : std_logic := '0';
signal LED4 : std_logic := '0';
signal LED5 : std_logic := '0';
signal LED6 : std_logic := '0';
signal LED7 : std_logic := '0';
--Outputs
signal SEGA : std_logic;
signal SEGB : std_logic;
signal SEGC : std_logic;
signal SEGD : std_logic;
signal SEGE : std_logic;
signal SEGF : std_logic;
signal SEGG : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: practica3 PORT MAP (
LED1 => LED1,
LED2 => LED2,
LED3 => LED3,
LED4 => LED4,
LED5 => LED5,
LED6 => LED6,
LED7 => LED7,
SEGA => SEGA,
SEGB => SEGB,
SEGC => SEGC,
SEGD => SEGD,
SEGE => SEGE,
SEGF => SEGF,
SEGG => SEGG
);
PROCESS
BEGIN
WAIT FOR 10 NS; --1
LED1 <= '1';
LED2 <= '1';
LED3 <= '1';
LED4 <= '0';
LED5 <= '1';
LED6 <= '1';
LED7 <= '1';
WAIT FOR 10 NS; --2
LED1 <= '1';
LED2 <= '1';
LED3 <= '0';
LED4 <= '1';
LED5 <= '1';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --3
LED1 <= '1';
LED2 <= '1';
LED3 <= '0';
LED4 <= '0';
LED5 <= '1';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --4
LED1 <= '0';
LED2 <= '1';
LED3 <= '0';
LED4 <= '1';
LED5 <= '0';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --5
LED1 <= '0';
LED2 <= '1';
LED3 <= '0';
LED4 <= '0';
LED5 <= '0';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --6
LED1 <= '0';
LED2 <= '0';
LED3 <= '0';
LED4 <= '1';
LED5 <= '0';
LED6 <= '0';
LED7 <= '0';
END PROCESS;
END;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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ACHOZBV4VQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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`protect end_protected
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Parameters
--! @author Markus Fehrenz
--! @date 2011/07/01
--!
--! @details This is the configuration file of the Viterbi decoder.
--! Any changes for parameters should be done here.
--! Changing parameters somewhere else may result in a malicious
--! behavior.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_param is
-----------------------------------
-- Convolutional Code Parameters --
-----------------------------------
--
-- Set the number of parity values
-- This has to correspond to PARITY_POLYNOMIALS
--
constant NUMBER_PARITY_BITS : natural := 2;
type t_parity is array (NUMBER_PARITY_BITS - 1 downto 0) of natural;
--
-- Set parity polynoms in decimal notation
-- NUMBER_PARITY_BITS has to correspond to the number of elements
-- Examples: WiFi : [121,91] or [121,91,101]
-- CDMA : [491,369] or [367,435,369] or [501,441,331,315]
-- GSM : [27,19] or [27,21,31]
-- DAB : [91,121,101,91]
-- WiMAX: [91,121,117]
--
constant PARITY_POLYNOMIALS : t_parity := (121,91);
--
-- Set a recursive polynomial
-- Set to 0 if no recursion is used
-- Setting this arbitrary may result in a worse error correction ability
--
constant FEEDBACK_POLYNOMIAL : natural := 0;
-----------------------------
-- Architecture Parameters --
-----------------------------
--
-- Set bit width of LLR input
-- Recommended values: 3 or 4
--
constant BW_LLR_INPUT : natural := 4;
--
-- Set the maximum window length which shall be allowed at runtime.
-- Recommended: at least 6 * constraint length
--
constant MAX_WINDOW_LENGTH : natural := 96;
--
-- Set to 'true' if distributed RAM shall be used
-- Set to 'false' if block RAM shall be used
--
constant DISTRIBUTED_RAM : boolean := true;
end package pkg_param;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Parameters
--! @author Markus Fehrenz
--! @date 2011/07/01
--!
--! @details This is the configuration file of the Viterbi decoder.
--! Any changes for parameters should be done here.
--! Changing parameters somewhere else may result in a malicious
--! behavior.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_param is
-----------------------------------
-- Convolutional Code Parameters --
-----------------------------------
--
-- Set the number of parity values
-- This has to correspond to PARITY_POLYNOMIALS
--
constant NUMBER_PARITY_BITS : natural := 2;
type t_parity is array (NUMBER_PARITY_BITS - 1 downto 0) of natural;
--
-- Set parity polynoms in decimal notation
-- NUMBER_PARITY_BITS has to correspond to the number of elements
-- Examples: WiFi : [121,91] or [121,91,101]
-- CDMA : [491,369] or [367,435,369] or [501,441,331,315]
-- GSM : [27,19] or [27,21,31]
-- DAB : [91,121,101,91]
-- WiMAX: [91,121,117]
--
constant PARITY_POLYNOMIALS : t_parity := (121,91);
--
-- Set a recursive polynomial
-- Set to 0 if no recursion is used
-- Setting this arbitrary may result in a worse error correction ability
--
constant FEEDBACK_POLYNOMIAL : natural := 0;
-----------------------------
-- Architecture Parameters --
-----------------------------
--
-- Set bit width of LLR input
-- Recommended values: 3 or 4
--
constant BW_LLR_INPUT : natural := 4;
--
-- Set the maximum window length which shall be allowed at runtime.
-- Recommended: at least 6 * constraint length
--
constant MAX_WINDOW_LENGTH : natural := 96;
--
-- Set to 'true' if distributed RAM shall be used
-- Set to 'false' if block RAM shall be used
--
constant DISTRIBUTED_RAM : boolean := true;
end package pkg_param;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 1 20:55:20 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_108MHz/clk_108MHz_stub.vhdl
-- Design : clk_108MHz
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_108MHz is
Port (
clk_100MHz : in STD_LOGIC;
clk_108MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_108MHz;
architecture stub of clk_108MHz is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_100MHz,clk_108MHz,locked";
begin
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 1 20:55:20 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_108MHz/clk_108MHz_stub.vhdl
-- Design : clk_108MHz
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_108MHz is
Port (
clk_100MHz : in STD_LOGIC;
clk_108MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_108MHz;
architecture stub of clk_108MHz is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_100MHz,clk_108MHz,locked";
begin
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: LUTROM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY LUTROM_tb IS
END ENTITY;
ARCHITECTURE LUTROM_tb_ARCH OF LUTROM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
LUTROM_synth_inst:ENTITY work.LUTROM_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
architecture RTL of FIFO is
begin
process
begin
if (a = '1') then
b <= '0';
elsif (b = '0') then
c <= '1';
end if;
-- Violations below
if (a = '1') then
b <= '0';
elsif(b = '0') then
c <= '1';
end if;
if (a = '1') then
b <= '0';
elsif (b = '0') then
c <= '1';
end if;
if (a = '1') then
b <= '0';
elsif b = '0' then
c <= '1';
end if;
end process;
end architecture RTL;
|
--
-- Definition of a single port ROM for KCPSM3 program defined by picocode.psm
--
-- Generated by KCPSM3 Assembler 17Aug2015-12:53:39.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity picocode is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end picocode;
--
architecture low_level_definition of picocode is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "00C0056300C0056900C0055000C0052000C0052000C0052000EB051000D3C000";
attribute INIT_01 of ram_1024_x_18 : label is "00C0052000C0052000C0056500C0057A00C0056100C0056C00C0054200C0056F";
attribute INIT_02 of ram_1024_x_18 : label is "00C0056400C0056400C0056500C0056200C0056D00C0056500C0052000C00520";
attribute INIT_03 of ram_1024_x_18 : label is "00C0057200C0056F00C0052E00C0057400C0056E00C0056100C0056400C00565";
attribute INIT_04 of ram_1024_x_18 : label is "00C0054100C0055000C0055300C0052000C0052000EB052000C0052000C00567";
attribute INIT_05 of ram_1024_x_18 : label is "00C0054E00C0054100C0053300C0052D00C0054E00C0054100C0055400C00552";
attribute INIT_06 of ram_1024_x_18 : label is "00C0054100C0052D00C0053200C0053100C0052000C0052000C0052000C00520";
attribute INIT_07 of ram_1024_x_18 : label is "00C0053000C0053200C0052D00C0057400C0057300C0057500C0056700C00575";
attribute INIT_08 of ram_1024_x_18 : label is "008A0128A000548BC001000B408600A203FF00F500C0052000C0053500C00531";
attribute INIT_09 of ram_1024_x_18 : label is "C40100980432A0005499C30100930314A0005494C201008E0219A000548FC101";
attribute INIT_0A of ram_1024_x_18 : label is "00A6008AC400A4F8A000C400A4FE008AC400C401A00054A2C3010093A000549E";
attribute INIT_0B of ram_1024_x_18 : label is "A000C40004F0008E00AC04060406040604071450008A00ACC408A4F01450A000";
attribute INIT_0C of ram_1024_x_18 : label is "008E00A6008AC40004060406040704071450008A00A6008AC400C40CA4F01450";
attribute INIT_0D of ram_1024_x_18 : label is "008E00AC0420009800AC0430009800AC0430009800AC04300098A000C40004F0";
attribute INIT_0E of ram_1024_x_18 : label is "00B1C580A50F50F12510A0000093009300B1050100B1050C00B1050600B10528";
attribute INIT_0F of ram_1024_x_18 : label is "00000000000000000000000000008001A00000B10518A00000B1C5C0A50FA000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "40F8000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCF";
attribute INITP_01 of ram_1024_x_18 : label is "0003B2C2C36FCCCCF3CF3CE8FEAA3F80A3EA8F02F8A38B7B72DCB72DCB4F3CCC";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"00C0056300C0056900C0055000C0052000C0052000C0052000EB051000D3C000",
INIT_01 => X"00C0052000C0052000C0056500C0057A00C0056100C0056C00C0054200C0056F",
INIT_02 => X"00C0056400C0056400C0056500C0056200C0056D00C0056500C0052000C00520",
INIT_03 => X"00C0057200C0056F00C0052E00C0057400C0056E00C0056100C0056400C00565",
INIT_04 => X"00C0054100C0055000C0055300C0052000C0052000EB052000C0052000C00567",
INIT_05 => X"00C0054E00C0054100C0053300C0052D00C0054E00C0054100C0055400C00552",
INIT_06 => X"00C0054100C0052D00C0053200C0053100C0052000C0052000C0052000C00520",
INIT_07 => X"00C0053000C0053200C0052D00C0057400C0057300C0057500C0056700C00575",
INIT_08 => X"008A0128A000548BC001000B408600A203FF00F500C0052000C0053500C00531",
INIT_09 => X"C40100980432A0005499C30100930314A0005494C201008E0219A000548FC101",
INIT_0A => X"00A6008AC400A4F8A000C400A4FE008AC400C401A00054A2C3010093A000549E",
INIT_0B => X"A000C40004F0008E00AC04060406040604071450008A00ACC408A4F01450A000",
INIT_0C => X"008E00A6008AC40004060406040704071450008A00A6008AC400C40CA4F01450",
INIT_0D => X"008E00AC0420009800AC0430009800AC0430009800AC04300098A000C40004F0",
INIT_0E => X"00B1C580A50F50F12510A0000093009300B1050100B1050C00B1050600B10528",
INIT_0F => X"00000000000000000000000000008001A00000B10518A00000B1C5C0A50FA000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"40F8000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCF",
INITP_01 => X"0003B2C2C36FCCCCF3CF3CE8FEAA3F80A3EA8F02F8A38B7B72DCB72DCB4F3CCC",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE picocode.vhd
--
------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkand
-- File: clkand.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkand is
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand is
signal eni : std_ulogic;
begin
re : if ren = 1 generate
renproc : process(i)
begin
if falling_edge(i) then eni <= en; end if;
end process;
end generate;
ce : if ren = 0 generate eni <= en; end generate;
xil : if (tech = virtex2) or (tech = spartan3) or (tech = spartan3e)
or (tech = virtex4) or (tech = virtex5) generate
clkgate : clkand_unisim port map(I => i, en => eni, O => o);
end generate;
ut : if (tech = ut25) generate
clkgate : clkand_ut025crh port map(I => i, en => eni, O => o);
end generate;
gen : if has_clkand(tech) = 0 generate
o <= i and eni;
end generate;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkand
-- File: clkand.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkand is
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand is
signal eni : std_ulogic;
begin
re : if ren = 1 generate
renproc : process(i)
begin
if falling_edge(i) then eni <= en; end if;
end process;
end generate;
ce : if ren = 0 generate eni <= en; end generate;
xil : if (tech = virtex2) or (tech = spartan3) or (tech = spartan3e)
or (tech = virtex4) or (tech = virtex5) generate
clkgate : clkand_unisim port map(I => i, en => eni, O => o);
end generate;
ut : if (tech = ut25) generate
clkgate : clkand_ut025crh port map(I => i, en => eni, O => o);
end generate;
gen : if has_clkand(tech) = 0 generate
o <= i and eni;
end generate;
end architecture;
|
--------------------------------------------------------------------------------
-- Title : tx_put_data
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_put_data.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 07.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- data handling module for tx path, controlled by tx_ctrl.vhd;
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- * tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx_put_data is
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end entity tx_put_data;
-- ****************************************************************************
architecture tx_put_data_arch of tx_put_data is
-- internal signals: ----------------------------------------------------------
signal aligned_int : std_logic;
signal data_in_q : std_logic_vector(63 downto 0);
signal data_q : std_logic_vector(63 downto 0);
signal data_qq : std_logic_vector(63 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal lower_addr_int : std_logic_vector(6 downto 0);
signal first_DW_int : std_logic_vector(3 downto 0);
signal last_DW_int : std_logic_vector(3 downto 0);
signal wr_rd_int : std_logic; -- =0: wr, =1: rd
signal mem_io_int : std_logic; -- =0: mem, =1: I/O
signal io_write_int : std_logic;
-------------------------------------------------------------------------------
begin
io_write <= io_write_int;
data_path : process(rst, clk)
begin
if(rst = '1') then
-- ports:
tx_st_data0 <= (others => '0');
data_length <= (others => '0');
aligned <= '0';
wr_rd <= '0';
posted <= '0';
byte_count <= (others => '0');
orig_addr <= (others => '0');
-- signals:
aligned_int <= '0';
data_in_q <= (others => '0');
data_q <= (others => '0');
data_qq <= (others => '0');
req_id_int <= (others => '0');
tag_id_int <= (others => '0');
lower_addr_int <= (others => '0');
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
wr_rd_int <= '0';
mem_io_int <= '0';
io_write_int <= '0';
else
if(clk'event and clk = '1') then
-- capture data length from appropriate FIFO packet
if(get_header = '1' and c_wrrd = '0') then
data_length <= tx_c_head_out(9 downto 0);
elsif(get_header = '1' and c_wrrd = '1') then
data_length <= tx_wr_head_out(9 downto 0);
end if;
-- store alignment information for both completion and write/read transmissions
if(get_header = '1' and c_wrrd = '0') then
case tx_c_head_out(34) is
when '0' => -- check bit 2 of address for alignment
aligned_int <= '1' ;
aligned <= '1' ;
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
elsif(get_header = '1' and c_wrrd = '1') then
case tx_wr_head_out(34) is
when '0' =>
aligned_int <= '1';
aligned <= '1';
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
end if;
-- capture information if transmission is write or read
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(31) = '1') then
wr_rd <= '0';
wr_rd_int <= '0';
else
wr_rd <= '1';
wr_rd_int <= '1';
end if;
----------------------------------------------------------------------------------------
-- wr_rd is not reset if c_wrrd = 0 and if previous transfer is read it's stuck at '1'
-- which causes errors during transfer
-- thus added elsif
----------------------------------------------------------------------------------------
elsif get_header = '1' and c_wrrd = '0' then
wr_rd <= '0';
wr_rd_int <= '0';
end if;
-- define if transfer is posted or not
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(30) = '1') then -- posted
posted <= '1';
else -- non-posted
posted <= '0';
end if;
end if;
-- define wether transfer is of type memory or I/O
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(29) = '1') then
mem_io_int <= '0'; -- memory
else
mem_io_int <= '1'; -- I/O
end if;
end if;
-- store information on first/last byte enables
if(get_header = '1' and c_wrrd = '1') then
first_DW_int <= tx_wr_head_out(17 downto 14); -- first DW
last_DW_int <= tx_wr_head_out(13 downto 10); -- last DW
end if;
-- register header packet
if(get_header = '1' and c_wrrd = '0') then
data_in_q <= tx_c_head_out;
end if;
-- store requester ID
if(get_next_header = '1' and c_wrrd = '0') then
req_id_int <= tx_c_head_out(15 downto 0);
end if;
-- store tag ID
if(get_header = '1' and c_wrrd = '0') then
tag_id_int <= tx_c_head_out(25 downto 18);
end if;
-- store byte count
if(get_next_header = '1' and c_wrrd = '0') then
byte_count <= tx_c_head_out(27 downto 16);
end if;
-- store I/O write flag
if(get_next_header = '1' and c_wrrd = '0') then
io_write_int <= tx_c_head_out(28);
elsif c_wrrd = '1' then
io_write_int <= '0';
end if;
-- store original transfer address
if(get_header = '1' and c_wrrd = '0') then
orig_addr <= tx_c_head_out(63 downto 32);
elsif(get_header = '1' and c_wrrd = '1') then
orig_addr <= tx_wr_head_out(63 downto 32);
end if;
-- calculate lower address for completions
if(get_header = '1' and c_wrrd = '0') then
if(tx_c_head_out(17 downto 14) = "0000" or tx_c_head_out(14) = '1') then
lower_addr_int <= tx_c_head_out(38 downto 34) & "00"; -- calculate from first DW
elsif(tx_c_head_out(15 downto 14) = "10") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "01";
elsif(tx_c_head_out(16 downto 14) = "100") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "10";
elsif(tx_c_head_out(17 downto 14) = "1000") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "11";
-- coverage off
else
-- synthesis translate_off
report "wrong encoding of tx_c_head_out(17 downto 14)" severity error;
-- synthesis translate_on
-- coverage on
end if;
end if;
-- assebmle packets for transmission
-- c_wrrd controls whether completion or write/read transfer is needed
-- R := reserved according to PCIe base specification, thus set to '0' here
if(make_header = '1' and c_wrrd = '0') then
if(abort_compl = '1' or io_write_int = '1') then
data_qq(31 downto 24) <= "00001010"; -- fmt & type -> completion without data
else
data_qq(31 downto 24) <= "01001010"; -- fmt & type -> completion with data
end if;
data_qq(23) <= '0'; -- R
data_qq(22 downto 20) <= data_in_q(28 downto 26); -- TC
data_qq(19) <= '0'; -- R
data_qq(18) <= data_in_q(31); -- Attr(2)
data_qq(17 downto 14) <= '0' & '0' & '0' & '0'; -- R & TH & TD & EP
data_qq(13 downto 12) <= data_in_q(30 downto 29); -- Attr(1:0)
data_qq(11 downto 10) <= "00"; -- AT
data_qq(9 downto 0) <= data_in_q(9 downto 0); -- length
data_qq(63 downto 48) <= completer_id;
if(abort_compl = '1') then
data_qq(47 downto 45) <= "100"; -- completion status = completer abort
else
data_qq(47 downto 45) <= "000"; -- completion status = successful completion
end if;
data_qq(44) <= '0'; -- bcm
data_qq(43 downto 32) <= tx_c_head_out(27 downto 16); -- byte count
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 16) <= req_id_int; -- requester ID
data_q(15 downto 8) <= tag_id_int; -- tag ID
data_q(7 downto 0) <= '0' & lower_addr_int; -- R & lower address
elsif(make_header = '1' and c_wrrd = '1') then
if(mem_io_int = '0' and wr_rd_int = '0') then -- memory write
data_qq(31 downto 24) <= "01000000";
elsif(mem_io_int = '1' and wr_rd_int = '0') then -- I/O write
data_qq(31 downto 24) <= "01000010";
elsif(mem_io_int = '0' and wr_rd_int = '1') then -- memory read
data_qq(31 downto 24) <= "00000000";
else -- I/O read
data_qq(31 downto 24) <= "00000010";
end if;
-- R & TC(2:0) & R & Attr(2) & R & TH & TD & EP & Attr(1:0) & AT
data_qq(23 downto 10) <= '0' & "000" & '0' & '0' & '0' & '0' & '0' & '0' & "00" & "00";
data_qq(9 downto 0) <= send_len; -- length
data_qq(63 downto 48) <= req_id;
data_qq(47 downto 40) <= tag_nbr;
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 0) <= send_addr; -- address
-- do payload loop, that means: one request was transmitted from Wishbone but the length is too big
-- thus split up in order to obey PCIe max_payload_size or max_read_size, which means
-- to send several packets with the same header info except address and length
-- CAUTION:
-- if the last packet to be sent has length =1 then last_DW must be =0
-- and the original setting for last_DW must be inserted for first_DW
if(payload_loop = '0') then
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "01") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "10") then
if send_len = "0000000001" then
data_qq(39 downto 36) <= x"0";
data_qq(35 downto 32) <= last_DW_int;
else
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= x"F";
end if;
elsif(payload_loop = '1' and first_last_full = "11") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= x"F";
end if;
end if;
-- manage registration of data retrieved from FIFO's
if(data_enable = '1' and aligned_int = '0' and c_wrrd = '0') then
data_q(31 downto 0) <= tx_c_data_out(63 downto 32);
data_qq <= tx_c_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '0' and c_wrrd = '1') then
data_q(31 downto 0) <= tx_wr_data_out(63 downto 32);
data_qq <= tx_wr_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '0') then
data_q <= tx_c_data_out;
data_qq <= data_q;
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '1') then
data_q <= tx_wr_data_out;
data_qq <= data_q;
end if;
-- output registered data to Avalon ST data bus
if(data_enable = '1') then
tx_st_data0 <= data_qq;
end if;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture tx_put_data_arch;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(271 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(271 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
rc_in_s <= X"80801b1b36366c6cd8d8abab4d4d9a9a2f2f5e5ebcbc6363c6c6979735356a6ad4d4";
-- 000000000000000000";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_09_02_a is
-- code from book (in text)
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
-- end code from book
end package fg_09_02_a;
package body fg_09_02_a is
-- code from book
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
-- end code from book
end package body fg_09_02_a;
entity fg_09_02_b is
end entity fg_09_02_b;
architecture test of fg_09_02_b is
use work.fg_09_02_a.all;
begin
stimulus : process is
use std.textio.all;
variable L : line;
begin
write(L, X"0002" + X"0000");
writeline(output, L);
write(L, X"0002" + X"0005");
writeline(output, L);
write(L, X"0002" + X"FFFE");
writeline(output, L);
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_09_02_a is
-- code from book (in text)
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
-- end code from book
end package fg_09_02_a;
package body fg_09_02_a is
-- code from book
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
-- end code from book
end package body fg_09_02_a;
entity fg_09_02_b is
end entity fg_09_02_b;
architecture test of fg_09_02_b is
use work.fg_09_02_a.all;
begin
stimulus : process is
use std.textio.all;
variable L : line;
begin
write(L, X"0002" + X"0000");
writeline(output, L);
write(L, X"0002" + X"0005");
writeline(output, L);
write(L, X"0002" + X"FFFE");
writeline(output, L);
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_09_02_a is
-- code from book (in text)
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
-- end code from book
end package fg_09_02_a;
package body fg_09_02_a is
-- code from book
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
-- end code from book
end package body fg_09_02_a;
entity fg_09_02_b is
end entity fg_09_02_b;
architecture test of fg_09_02_b is
use work.fg_09_02_a.all;
begin
stimulus : process is
use std.textio.all;
variable L : line;
begin
write(L, X"0002" + X"0000");
writeline(output, L);
write(L, X"0002" + X"0005");
writeline(output, L);
write(L, X"0002" + X"FFFE");
writeline(output, L);
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1356.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01356ent IS
END c08s05b00x00p03n01i01356ent;
ARCHITECTURE c08s05b00x00p03n01i01356arch OF c08s05b00x00p03n01i01356ent IS
BEGIN
TESTING: PROCESS
type t1 is record
ele1 : integer;
ele2 : real;
end record;
variable f1: t1;
variable i : integer := 0;
variable r : real := 0.0;
BEGIN
f1.ele1 := 1;
f1.ele2 := 2.3;
i := f1.ele1;
r := f1.ele2;
assert NOT((i=1) and (r=2.3))
report "***PASSED TEST: c08s05b00x00p03n01i01356"
severity NOTE;
assert ((i=1) and (r=2.3))
report "***FAILED TEST: c08s05b00x00p03n01i01356 - Target and the expression on the right-hand side should have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01356arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1356.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01356ent IS
END c08s05b00x00p03n01i01356ent;
ARCHITECTURE c08s05b00x00p03n01i01356arch OF c08s05b00x00p03n01i01356ent IS
BEGIN
TESTING: PROCESS
type t1 is record
ele1 : integer;
ele2 : real;
end record;
variable f1: t1;
variable i : integer := 0;
variable r : real := 0.0;
BEGIN
f1.ele1 := 1;
f1.ele2 := 2.3;
i := f1.ele1;
r := f1.ele2;
assert NOT((i=1) and (r=2.3))
report "***PASSED TEST: c08s05b00x00p03n01i01356"
severity NOTE;
assert ((i=1) and (r=2.3))
report "***FAILED TEST: c08s05b00x00p03n01i01356 - Target and the expression on the right-hand side should have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01356arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1356.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01356ent IS
END c08s05b00x00p03n01i01356ent;
ARCHITECTURE c08s05b00x00p03n01i01356arch OF c08s05b00x00p03n01i01356ent IS
BEGIN
TESTING: PROCESS
type t1 is record
ele1 : integer;
ele2 : real;
end record;
variable f1: t1;
variable i : integer := 0;
variable r : real := 0.0;
BEGIN
f1.ele1 := 1;
f1.ele2 := 2.3;
i := f1.ele1;
r := f1.ele2;
assert NOT((i=1) and (r=2.3))
report "***PASSED TEST: c08s05b00x00p03n01i01356"
severity NOTE;
assert ((i=1) and (r=2.3))
report "***FAILED TEST: c08s05b00x00p03n01i01356 - Target and the expression on the right-hand side should have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01356arch;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
-- COMPONENT blk_mem_40K
-- PORT (
-- addra : IN std_logic_VECTOR (15 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
component blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_com1; -- UART
when "101" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when others => dbus_in_cpu <= dbus_esram; -- External SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 14)="000000" AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr,
web => (others => '0'),
doutb => vramdata
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:01:33 11/18/2013
-- Design Name:
-- Module Name: puntos_muestra - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end puntos_muestra;
architecture Behavioral of puntos_muestra is
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
--Tamaño de los coeficientes en la señal de salida del teclado
constant COEF : integer := 5;
constant NUM_COUNT : integer:= 4;
type matriz1 is array(0 to 32) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
type matriz2 is array(0 to 31) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
-- En función del caso utilizaremos uno de los siguientes muestreos de puntos (para más información consultar genera2.m)
constant puntos1 : matriz1 := (
"0000000000000000000000000",
"0000000000000001000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos2 : matriz2 := (
"0000000000000000000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos3 : matriz2 := (
"1111111111100000000000000",
"1111111111100010000000000",
"1111111111100100000000000",
"1111111111100110000000000",
"1111111111101000000000000",
"1111111111101010000000000",
"1111111111101100000000000",
"1111111111101110000000000",
"1111111111110000000000000",
"1111111111110010000000000",
"1111111111110100000000000",
"1111111111110110000000000",
"1111111111111000000000000",
"1111111111111010000000000",
"1111111111111100000000000",
"1111111111111110000000000",
"0000000000000010000000000",
"0000000000000100000000000",
"0000000000000110000000000",
"0000000000001000000000000",
"0000000000001010000000000",
"0000000000001100000000000",
"0000000000001110000000000",
"0000000000010000000000000",
"0000000000010010000000000",
"0000000000010100000000000",
"0000000000010110000000000",
"0000000000011000000000000",
"0000000000011010000000000",
"0000000000011100000000000",
"0000000000011110000000000",
"0000000000100000000000000");
signal punto: STD_LOGIC_VECTOR(DEC+ENT+NUM_COUNT-1 downto 0);
signal count: std_logic_vector(3 downto 0);
signal c3, c2,c1, cn1, cn2, cn3: std_logic_vector(COEF-1 downto 0);
signal puntoAux: std_logic_vector(20 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
begin
-- Obtenemos los coeficientes introducidos por el teclado, en valor absoluto
process(entradaTeclado)
begin
if entradaTeclado(34)='1' then c3 <= "00000" - entradaTeclado(34 downto 30);
else c3 <= entradaTeclado(34 downto 30);
end if;
if entradaTeclado(29)='1' then c2 <= "00000" - entradaTeclado(29 downto 25);
else c2 <= entradaTeclado(29 downto 25);
end if;
if entradaTeclado(24)='1' then c1 <= "00000" - entradaTeclado(24 downto 20);
else c1 <= entradaTeclado(24 downto 20);
end if;
if entradaTeclado(14)='1' then cn1<= "00000" - entradaTeclado(14 downto 10);
else cn1 <= entradaTeclado(14 downto 10);
end if;
if entradaTeclado(9)='1' then cn2 <= "00000" - entradaTeclado(9 downto 5);
else cn2 <= entradaTeclado(9 downto 5);
end if;
if entradaTeclado(4)='1' then cn3 <= "00000" - entradaTeclado(4 downto 0);
else cn3 <= entradaTeclado(4 downto 0);
end if;
end process;
-- En función de los coeficientes de la función, escogemos el count adecuado (reescalado del eje X)
-- (para más información consultar genera2.m)
pcount: process(c3, c2, c1, cn1, cn2, cn3, caso)
begin
if caso = "00" then
count <= "0000";
else
if c3>0 then
if cn3>0 then
count<="0010";
elsif cn2>0 then
if c3 > cn2(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
elsif cn1>0 then
count<="0001";
else
count<="0001";
end if;
elsif c2>0 then
if cn3>0 then
if cn3 > c2(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
elsif cn2>0 then
count<="0010";
elsif cn1>0 then
if c2 > cn1(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
else
count<="0010";
end if;
elsif c1>0 then
if cn3>0 then
count<="0011";
elsif cn2>0 then
if cn2 > c1(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
else
count<="0010";
end if;
else
if cn3>0 then
count<="0100";
elsif cn2>0 then
count<="0011";
elsif cn1>0 then
count<="0010";
else
count<="0000";
end if;
end if;
end if;
end process pcount;
sincrono: process (clk, reset, enable)
begin
if reset = '1' then
estado <= (others => '0');
elsif clk'event and clk = '1' then
if enable = '1' then
estado <= estado_sig;
elsif retro_muestra = '1'
then estado <= numPuntos-1;
end if;
end if;
end process sincrono;
maquina_estados: process(estado, caso, numPuntos)
begin
if estado = "0000000" then
fin <= '1';
else
fin <= '0';
end if;
if caso = "00" then
punto <= puntos1(conv_integer(unsigned(estado)));
elsif caso = "01" then
punto <= puntos2(conv_integer(unsigned(estado)));
else
punto <= puntos3(conv_integer(unsigned(estado)));
end if;
if estado = numPuntos-1 then
estado_sig <= (others => '0');
fin <= '1';
else
estado_sig <= estado + 1;
fin <= '0';
end if;
end process maquina_estados;
-- En función del count (nos indica la potencia de 2 por la cual tenemos que multiplicar los puntos de muestra),
--elegimos el subvector que nos interesa
puntoAux <= punto(DEC+ENT+NUM_COUNT-1-conv_integer(count) downto NUM_COUNT-conv_integer(count));
punto_o <= puntoAux;
-- Escala x: en el caso normal, 1 unidad equivale a 2^(count-3), por lo que count_o representará este exponente
-- En el caso de solo tomar números positivos (logaritmo), debido al reescalado de los puntos, ahora 1 unidad
-- representará la mitad que en el caso anterior
with caso select
count_o <= count-3 when "10", --eje central
count-4 when others;--eje en la izquierda (log)
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:01:33 11/18/2013
-- Design Name:
-- Module Name: puntos_muestra - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity puntos_muestra is
Port ( caso : in std_logic_vector(1 downto 0);
numPuntos : in std_logic_vector( 6 downto 0);
enable, retro_muestra : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fin : out STD_LOGIC;
entradaTeclado: in std_logic_vector(49 downto 0);
punto_o : out STD_LOGIC_VECTOR(20 downto 0);
count_o: out std_logic_vector(3 downto 0));-- Para mostrar en el display de 7 segmentos
end puntos_muestra;
architecture Behavioral of puntos_muestra is
-- En la representación en coma fija
-- DEC es el número de bits reservados a la parte decimal
-- ENT es el número de bits reservados a la parte entera
constant ENT : integer := 11;
constant DEC : integer := 10;
--Tamaño de los coeficientes en la señal de salida del teclado
constant COEF : integer := 5;
constant NUM_COUNT : integer:= 4;
type matriz1 is array(0 to 32) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
type matriz2 is array(0 to 31) of std_logic_vector(DEC+ENT+NUM_COUNT-1 downto 0);
-- En función del caso utilizaremos uno de los siguientes muestreos de puntos (para más información consultar genera2.m)
constant puntos1 : matriz1 := (
"0000000000000000000000000",
"0000000000000001000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos2 : matriz2 := (
"0000000000000000000000000",
"0000000000000010000000000",
"0000000000000011000000000",
"0000000000000100000000000",
"0000000000000101000000000",
"0000000000000110000000000",
"0000000000000111000000000",
"0000000000001000000000000",
"0000000000001001000000000",
"0000000000001010000000000",
"0000000000001011000000000",
"0000000000001100000000000",
"0000000000001101000000000",
"0000000000001110000000000",
"0000000000001111000000000",
"0000000000010000000000000",
"0000000000010001000000000",
"0000000000010010000000000",
"0000000000010011000000000",
"0000000000010100000000000",
"0000000000010101000000000",
"0000000000010110000000000",
"0000000000010111000000000",
"0000000000011000000000000",
"0000000000011001000000000",
"0000000000011010000000000",
"0000000000011011000000000",
"0000000000011100000000000",
"0000000000011101000000000",
"0000000000011110000000000",
"0000000000011111000000000",
"0000000000100000000000000");
constant puntos3 : matriz2 := (
"1111111111100000000000000",
"1111111111100010000000000",
"1111111111100100000000000",
"1111111111100110000000000",
"1111111111101000000000000",
"1111111111101010000000000",
"1111111111101100000000000",
"1111111111101110000000000",
"1111111111110000000000000",
"1111111111110010000000000",
"1111111111110100000000000",
"1111111111110110000000000",
"1111111111111000000000000",
"1111111111111010000000000",
"1111111111111100000000000",
"1111111111111110000000000",
"0000000000000010000000000",
"0000000000000100000000000",
"0000000000000110000000000",
"0000000000001000000000000",
"0000000000001010000000000",
"0000000000001100000000000",
"0000000000001110000000000",
"0000000000010000000000000",
"0000000000010010000000000",
"0000000000010100000000000",
"0000000000010110000000000",
"0000000000011000000000000",
"0000000000011010000000000",
"0000000000011100000000000",
"0000000000011110000000000",
"0000000000100000000000000");
signal punto: STD_LOGIC_VECTOR(DEC+ENT+NUM_COUNT-1 downto 0);
signal count: std_logic_vector(3 downto 0);
signal c3, c2,c1, cn1, cn2, cn3: std_logic_vector(COEF-1 downto 0);
signal puntoAux: std_logic_vector(20 downto 0);
signal estado, estado_sig: std_logic_vector(6 downto 0);
begin
-- Obtenemos los coeficientes introducidos por el teclado, en valor absoluto
process(entradaTeclado)
begin
if entradaTeclado(34)='1' then c3 <= "00000" - entradaTeclado(34 downto 30);
else c3 <= entradaTeclado(34 downto 30);
end if;
if entradaTeclado(29)='1' then c2 <= "00000" - entradaTeclado(29 downto 25);
else c2 <= entradaTeclado(29 downto 25);
end if;
if entradaTeclado(24)='1' then c1 <= "00000" - entradaTeclado(24 downto 20);
else c1 <= entradaTeclado(24 downto 20);
end if;
if entradaTeclado(14)='1' then cn1<= "00000" - entradaTeclado(14 downto 10);
else cn1 <= entradaTeclado(14 downto 10);
end if;
if entradaTeclado(9)='1' then cn2 <= "00000" - entradaTeclado(9 downto 5);
else cn2 <= entradaTeclado(9 downto 5);
end if;
if entradaTeclado(4)='1' then cn3 <= "00000" - entradaTeclado(4 downto 0);
else cn3 <= entradaTeclado(4 downto 0);
end if;
end process;
-- En función de los coeficientes de la función, escogemos el count adecuado (reescalado del eje X)
-- (para más información consultar genera2.m)
pcount: process(c3, c2, c1, cn1, cn2, cn3, caso)
begin
if caso = "00" then
count <= "0000";
else
if c3>0 then
if cn3>0 then
count<="0010";
elsif cn2>0 then
if c3 > cn2(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
elsif cn1>0 then
count<="0001";
else
count<="0001";
end if;
elsif c2>0 then
if cn3>0 then
if cn3 > c2(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
elsif cn2>0 then
count<="0010";
elsif cn1>0 then
if c2 > cn1(4 downto 1) then
count<="0001";
else
count<="0010";
end if;
else
count<="0010";
end if;
elsif c1>0 then
if cn3>0 then
count<="0011";
elsif cn2>0 then
if cn2 > c1(4 downto 1) then
count<="0011";
else
count<="0010";
end if;
else
count<="0010";
end if;
else
if cn3>0 then
count<="0100";
elsif cn2>0 then
count<="0011";
elsif cn1>0 then
count<="0010";
else
count<="0000";
end if;
end if;
end if;
end process pcount;
sincrono: process (clk, reset, enable)
begin
if reset = '1' then
estado <= (others => '0');
elsif clk'event and clk = '1' then
if enable = '1' then
estado <= estado_sig;
elsif retro_muestra = '1'
then estado <= numPuntos-1;
end if;
end if;
end process sincrono;
maquina_estados: process(estado, caso, numPuntos)
begin
if estado = "0000000" then
fin <= '1';
else
fin <= '0';
end if;
if caso = "00" then
punto <= puntos1(conv_integer(unsigned(estado)));
elsif caso = "01" then
punto <= puntos2(conv_integer(unsigned(estado)));
else
punto <= puntos3(conv_integer(unsigned(estado)));
end if;
if estado = numPuntos-1 then
estado_sig <= (others => '0');
fin <= '1';
else
estado_sig <= estado + 1;
fin <= '0';
end if;
end process maquina_estados;
-- En función del count (nos indica la potencia de 2 por la cual tenemos que multiplicar los puntos de muestra),
--elegimos el subvector que nos interesa
puntoAux <= punto(DEC+ENT+NUM_COUNT-1-conv_integer(count) downto NUM_COUNT-conv_integer(count));
punto_o <= puntoAux;
-- Escala x: en el caso normal, 1 unidad equivale a 2^(count-3), por lo que count_o representará este exponente
-- En el caso de solo tomar números positivos (logaritmo), debido al reescalado de los puntos, ahora 1 unidad
-- representará la mitad que en el caso anterior
with caso select
count_o <= count-3 when "10", --eje central
count-4 when others;--eje en la izquierda (log)
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
baz : out std_logic_vector(7 downto 0);
clock : in std_logic;
clock2 : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
baz <= "00101100";
case "100" is
when "000" =>
if rising_edge(clock) then
if rising_edge(clock2) then
A <= '0';
end if;
end if;
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control
--
-- Transfer Function:
--
-- pos_t_out = R*sin(theta)
--
-- Where pos_t = output translational position,
-- R = horn radius,
-- theta_in = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity ctl_horn_e is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta_in : electrical; -- input port
terminal pos_t_out : electrical); -- output port
end entity ctl_horn_e;
architecture bhv of ctl_horn_e is
quantity vin across theta_in to electrical_ref;
quantity vout across iout through pos_t_out to electrical_ref;
begin -- bhv
vout == R*sin(vin);
end bhv;
--
-------------------------------------------------------------------------------
-- Rudder Model
--
-- Transfer Function:
--
-- theta_out = arcsin(pos_t_in/R)
--
-- Where pos_t_in = input translational position,
-- R = horn radius,
-- theta_out = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity rudder_horn_e is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos_t_in : electrical; -- input port
terminal theta_out : electrical); -- output port
end entity rudder_horn_e;
architecture bhv of rudder_horn_e is
quantity vin across pos_t_in to electrical_ref;
quantity vout across iout through theta_out to electrical_ref;
begin -- bhv
vout == arcsin(vin/R);
end bhv;
--
-------------------------------------------------------------------------------
-- Integrator
--
-- Transfer Function:
--
-- k
-- H(s) = ---------
-- s
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity integ_1_e is
generic (
k: real := 1.0; -- Gain
init: real := 0.0); -- Initial value of output
port (terminal input: electrical;
terminal output: electrical);
end entity integ_1_e;
architecture simple of integ_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
begin
vin_temp == vin;
IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
vout == init;
ELSE
vout == k*vin_temp'INTEG;
END USE;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lpf_1_e is
generic (
fp : real; -- pole freq
gain : real := 1.0); -- filter gain
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_1_e;
architecture simple of lpf_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant wp : real := math_2_pi*fp;
constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (wp, 1.0);
quantity vin_temp : real;
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_S_Domain is
end TB_CS2_S_Domain;
architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
-- Component declarations
-- Signal declarations
terminal comp_in : electrical;
terminal ctl_horn_out : electrical;
terminal err_limit_in : electrical;
terminal error : electrical;
terminal gear_out : electrical;
terminal integ_out : electrical;
terminal load_trq : electrical;
terminal mtr_fb : electrical;
terminal mtr_gen_trq : electrical;
terminal mtr_in : electrical;
terminal mtr_out : electrical;
terminal pos_fb : electrical;
terminal rudder : electrical;
terminal rudder_in : electrical;
terminal src_in : electrical;
terminal XSIG010043 : electrical;
terminal XSIG010044 : electrical;
terminal XSIG010046 : electrical;
terminal XSIG010050 : electrical;
begin
-- Signal assignments
-- Component instances
v_source : entity work.v_sine(ideal)
generic map(
amplitude => 4.8,
freq => 1.0
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
sum_pos : entity work.sum2_e(simple)
port map(
in1 => src_in,
in2 => pos_fb,
output => error
);
loop_comp : entity work.lead_lag_e(simple)
generic map(
f1 => 5.0,
k => 4000.0,
f2 => 20000.0
)
port map(
input => comp_in,
output => err_limit_in
);
pos_fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => rudder_in,
output => pos_fb
);
mech_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 1.05,
limit_low => -1.05
)
port map(
input => integ_out,
output => rudder_in
);
gear_box_horn : entity work.ctl_horn_e(bhv)
port map(
theta_in => rudder_in,
pos_t_out => ctl_horn_out
);
rudder_horn : entity work.rudder_horn_e(bhv)
port map(
pos_t_in => ctl_horn_out,
theta_out => rudder
);
mtr_Kt : entity work.gain_e(simple)
generic map(
k => 3.43e-3
)
port map(
input => XSIG010044,
output => mtr_gen_trq
);
gear_box : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => mtr_out,
output => gear_out
);
mtr_Ke : entity work.gain_e(simple)
generic map(
k => -3.43e-3
)
port map(
input => mtr_out,
output => mtr_fb
);
sum_mtr_in : entity work.sum2_e(simple)
port map(
in1 => mtr_in,
in2 => mtr_fb,
output => XSIG010043
);
sum_load_trq : entity work.sum2_e(simple)
port map(
in1 => mtr_gen_trq,
in2 => load_trq,
output => XSIG010046
);
integrator : entity work.integ_1_e(simple)
generic map(
k => 1.0
)
port map(
input => gear_out,
output => integ_out
);
rudder_trq : entity work.gain_e(simple)
generic map(
k => -0.2
)
port map(
input => XSIG010050,
output => load_trq
);
trq_fb_gain : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => rudder_in,
output => XSIG010050
);
mtr_elec_pole : entity work.lpf_1_e(simple)
generic map(
gain => 0.4545,
fp => 172.48
)
port map(
input => XSIG010043,
output => XSIG010044
);
mtr_mech_pole : entity work.lpf_1_e(simple)
generic map(
gain => 177.67e3,
fp => 5.33
)
port map(
input => XSIG010046,
output => mtr_out
);
loop_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => comp_in
);
err_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => err_limit_in,
output => mtr_in
);
end TB_CS2_S_Domain;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control
--
-- Transfer Function:
--
-- pos_t_out = R*sin(theta)
--
-- Where pos_t = output translational position,
-- R = horn radius,
-- theta_in = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity ctl_horn_e is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta_in : electrical; -- input port
terminal pos_t_out : electrical); -- output port
end entity ctl_horn_e;
architecture bhv of ctl_horn_e is
quantity vin across theta_in to electrical_ref;
quantity vout across iout through pos_t_out to electrical_ref;
begin -- bhv
vout == R*sin(vin);
end bhv;
--
-------------------------------------------------------------------------------
-- Rudder Model
--
-- Transfer Function:
--
-- theta_out = arcsin(pos_t_in/R)
--
-- Where pos_t_in = input translational position,
-- R = horn radius,
-- theta_out = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity rudder_horn_e is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos_t_in : electrical; -- input port
terminal theta_out : electrical); -- output port
end entity rudder_horn_e;
architecture bhv of rudder_horn_e is
quantity vin across pos_t_in to electrical_ref;
quantity vout across iout through theta_out to electrical_ref;
begin -- bhv
vout == arcsin(vin/R);
end bhv;
--
-------------------------------------------------------------------------------
-- Integrator
--
-- Transfer Function:
--
-- k
-- H(s) = ---------
-- s
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity integ_1_e is
generic (
k: real := 1.0; -- Gain
init: real := 0.0); -- Initial value of output
port (terminal input: electrical;
terminal output: electrical);
end entity integ_1_e;
architecture simple of integ_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
begin
vin_temp == vin;
IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
vout == init;
ELSE
vout == k*vin_temp'INTEG;
END USE;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lpf_1_e is
generic (
fp : real; -- pole freq
gain : real := 1.0); -- filter gain
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_1_e;
architecture simple of lpf_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant wp : real := math_2_pi*fp;
constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (wp, 1.0);
quantity vin_temp : real;
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_S_Domain is
end TB_CS2_S_Domain;
architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
-- Component declarations
-- Signal declarations
terminal comp_in : electrical;
terminal ctl_horn_out : electrical;
terminal err_limit_in : electrical;
terminal error : electrical;
terminal gear_out : electrical;
terminal integ_out : electrical;
terminal load_trq : electrical;
terminal mtr_fb : electrical;
terminal mtr_gen_trq : electrical;
terminal mtr_in : electrical;
terminal mtr_out : electrical;
terminal pos_fb : electrical;
terminal rudder : electrical;
terminal rudder_in : electrical;
terminal src_in : electrical;
terminal XSIG010043 : electrical;
terminal XSIG010044 : electrical;
terminal XSIG010046 : electrical;
terminal XSIG010050 : electrical;
begin
-- Signal assignments
-- Component instances
v_source : entity work.v_sine(ideal)
generic map(
amplitude => 4.8,
freq => 1.0
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
sum_pos : entity work.sum2_e(simple)
port map(
in1 => src_in,
in2 => pos_fb,
output => error
);
loop_comp : entity work.lead_lag_e(simple)
generic map(
f1 => 5.0,
k => 4000.0,
f2 => 20000.0
)
port map(
input => comp_in,
output => err_limit_in
);
pos_fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => rudder_in,
output => pos_fb
);
mech_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 1.05,
limit_low => -1.05
)
port map(
input => integ_out,
output => rudder_in
);
gear_box_horn : entity work.ctl_horn_e(bhv)
port map(
theta_in => rudder_in,
pos_t_out => ctl_horn_out
);
rudder_horn : entity work.rudder_horn_e(bhv)
port map(
pos_t_in => ctl_horn_out,
theta_out => rudder
);
mtr_Kt : entity work.gain_e(simple)
generic map(
k => 3.43e-3
)
port map(
input => XSIG010044,
output => mtr_gen_trq
);
gear_box : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => mtr_out,
output => gear_out
);
mtr_Ke : entity work.gain_e(simple)
generic map(
k => -3.43e-3
)
port map(
input => mtr_out,
output => mtr_fb
);
sum_mtr_in : entity work.sum2_e(simple)
port map(
in1 => mtr_in,
in2 => mtr_fb,
output => XSIG010043
);
sum_load_trq : entity work.sum2_e(simple)
port map(
in1 => mtr_gen_trq,
in2 => load_trq,
output => XSIG010046
);
integrator : entity work.integ_1_e(simple)
generic map(
k => 1.0
)
port map(
input => gear_out,
output => integ_out
);
rudder_trq : entity work.gain_e(simple)
generic map(
k => -0.2
)
port map(
input => XSIG010050,
output => load_trq
);
trq_fb_gain : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => rudder_in,
output => XSIG010050
);
mtr_elec_pole : entity work.lpf_1_e(simple)
generic map(
gain => 0.4545,
fp => 172.48
)
port map(
input => XSIG010043,
output => XSIG010044
);
mtr_mech_pole : entity work.lpf_1_e(simple)
generic map(
gain => 177.67e3,
fp => 5.33
)
port map(
input => XSIG010046,
output => mtr_out
);
loop_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => comp_in
);
err_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => err_limit_in,
output => mtr_in
);
end TB_CS2_S_Domain;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control
--
-- Transfer Function:
--
-- pos_t_out = R*sin(theta)
--
-- Where pos_t = output translational position,
-- R = horn radius,
-- theta_in = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity ctl_horn_e is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta_in : electrical; -- input port
terminal pos_t_out : electrical); -- output port
end entity ctl_horn_e;
architecture bhv of ctl_horn_e is
quantity vin across theta_in to electrical_ref;
quantity vout across iout through pos_t_out to electrical_ref;
begin -- bhv
vout == R*sin(vin);
end bhv;
--
-------------------------------------------------------------------------------
-- Rudder Model
--
-- Transfer Function:
--
-- theta_out = arcsin(pos_t_in/R)
--
-- Where pos_t_in = input translational position,
-- R = horn radius,
-- theta_out = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity rudder_horn_e is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos_t_in : electrical; -- input port
terminal theta_out : electrical); -- output port
end entity rudder_horn_e;
architecture bhv of rudder_horn_e is
quantity vin across pos_t_in to electrical_ref;
quantity vout across iout through theta_out to electrical_ref;
begin -- bhv
vout == arcsin(vin/R);
end bhv;
--
-------------------------------------------------------------------------------
-- Integrator
--
-- Transfer Function:
--
-- k
-- H(s) = ---------
-- s
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity integ_1_e is
generic (
k: real := 1.0; -- Gain
init: real := 0.0); -- Initial value of output
port (terminal input: electrical;
terminal output: electrical);
end entity integ_1_e;
architecture simple of integ_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
begin
vin_temp == vin;
IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
vout == init;
ELSE
vout == k*vin_temp'INTEG;
END USE;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lpf_1_e is
generic (
fp : real; -- pole freq
gain : real := 1.0); -- filter gain
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_1_e;
architecture simple of lpf_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant wp : real := math_2_pi*fp;
constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (wp, 1.0);
quantity vin_temp : real;
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_S_Domain is
end TB_CS2_S_Domain;
architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
-- Component declarations
-- Signal declarations
terminal comp_in : electrical;
terminal ctl_horn_out : electrical;
terminal err_limit_in : electrical;
terminal error : electrical;
terminal gear_out : electrical;
terminal integ_out : electrical;
terminal load_trq : electrical;
terminal mtr_fb : electrical;
terminal mtr_gen_trq : electrical;
terminal mtr_in : electrical;
terminal mtr_out : electrical;
terminal pos_fb : electrical;
terminal rudder : electrical;
terminal rudder_in : electrical;
terminal src_in : electrical;
terminal XSIG010043 : electrical;
terminal XSIG010044 : electrical;
terminal XSIG010046 : electrical;
terminal XSIG010050 : electrical;
begin
-- Signal assignments
-- Component instances
v_source : entity work.v_sine(ideal)
generic map(
amplitude => 4.8,
freq => 1.0
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
sum_pos : entity work.sum2_e(simple)
port map(
in1 => src_in,
in2 => pos_fb,
output => error
);
loop_comp : entity work.lead_lag_e(simple)
generic map(
f1 => 5.0,
k => 4000.0,
f2 => 20000.0
)
port map(
input => comp_in,
output => err_limit_in
);
pos_fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => rudder_in,
output => pos_fb
);
mech_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 1.05,
limit_low => -1.05
)
port map(
input => integ_out,
output => rudder_in
);
gear_box_horn : entity work.ctl_horn_e(bhv)
port map(
theta_in => rudder_in,
pos_t_out => ctl_horn_out
);
rudder_horn : entity work.rudder_horn_e(bhv)
port map(
pos_t_in => ctl_horn_out,
theta_out => rudder
);
mtr_Kt : entity work.gain_e(simple)
generic map(
k => 3.43e-3
)
port map(
input => XSIG010044,
output => mtr_gen_trq
);
gear_box : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => mtr_out,
output => gear_out
);
mtr_Ke : entity work.gain_e(simple)
generic map(
k => -3.43e-3
)
port map(
input => mtr_out,
output => mtr_fb
);
sum_mtr_in : entity work.sum2_e(simple)
port map(
in1 => mtr_in,
in2 => mtr_fb,
output => XSIG010043
);
sum_load_trq : entity work.sum2_e(simple)
port map(
in1 => mtr_gen_trq,
in2 => load_trq,
output => XSIG010046
);
integrator : entity work.integ_1_e(simple)
generic map(
k => 1.0
)
port map(
input => gear_out,
output => integ_out
);
rudder_trq : entity work.gain_e(simple)
generic map(
k => -0.2
)
port map(
input => XSIG010050,
output => load_trq
);
trq_fb_gain : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => rudder_in,
output => XSIG010050
);
mtr_elec_pole : entity work.lpf_1_e(simple)
generic map(
gain => 0.4545,
fp => 172.48
)
port map(
input => XSIG010043,
output => XSIG010044
);
mtr_mech_pole : entity work.lpf_1_e(simple)
generic map(
gain => 177.67e3,
fp => 5.33
)
port map(
input => XSIG010046,
output => mtr_out
);
loop_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => comp_in
);
err_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => err_limit_in,
output => mtr_in
);
end TB_CS2_S_Domain;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2971.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02971ent IS
END c02s03b01x00p02n02i02971ent;
ARCHITECTURE c02s03b01x00p02n02i02971arch OF c02s03b01x00p02n02i02971ent IS
function "and" (a1 : real) return integer is --Failure here
begin
return 12;
end "and";
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s03b01x00p02n02i02971 - The subprogram specification of a binary operator must have two parameters."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02971arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2971.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02971ent IS
END c02s03b01x00p02n02i02971ent;
ARCHITECTURE c02s03b01x00p02n02i02971arch OF c02s03b01x00p02n02i02971ent IS
function "and" (a1 : real) return integer is --Failure here
begin
return 12;
end "and";
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s03b01x00p02n02i02971 - The subprogram specification of a binary operator must have two parameters."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02971arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2971.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02971ent IS
END c02s03b01x00p02n02i02971ent;
ARCHITECTURE c02s03b01x00p02n02i02971arch OF c02s03b01x00p02n02i02971ent IS
function "and" (a1 : real) return integer is --Failure here
begin
return 12;
end "and";
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s03b01x00p02n02i02971 - The subprogram specification of a binary operator must have two parameters."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02971arch;
|
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