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Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity Counter Is
Port (
clk_i: In std_logic;
clr_i: In std_logic;
enable_i: In std_logic;
counting_o: Out std_logic_vector (23 downto 0)
);
End Entity;
Architecture fCounter Of Counter Is
Signal tmp: std_logic_vector (23 downto 0);
Signal R0, R1, R2, R3, R4, R5: std_logic_vector (3 downto 0);
Begin
Process (clk_i, clr_i, enable_i, R5 , R4 , R3 , R2 , R1 , R0)
Begin
If clr_i = '1' Then
tmp <= "000000000000000000000000";
R0 <= "0000";
R1 <= "0000";
R2 <= "0000";
R3 <= "0000";
R4 <= "0000";
R5 <= "0000";
Elsif enable_i = '1' Then
If clk_i'Event And clk_i = '1' Then
If R0 = "1001" Then
R0 <= "0000";
R1 <= R1 + 1;
If R1 = "1001" Then
R1 <= "0000";
R2 <= R2 + 1;
If R2 = "1001" Then
R2 <= "0000";
R3 <= R3 + 1;
If R3 = "1001" Then
R3 <= "0000";
R4 <= R4 + 1;
If R4 = "1001" Then
R4 <= "0000";
R5 <= R5 + 1;
Else
R4 <= R4 + 1;
End If;
Else
R3 <= R3 + 1;
End If;
Else
R2 <= R2 + 1;
End If;
Else
R1 <= R1 + 1;
End If;
Else
R0 <= R0 + 1;
End If;
End If;
End If;
tmp <= R5 & R4 & R3 & R2 & R1 & R0;
End Process;
counting_o <= tmp;
End Architecture; |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point co-processor interface
-- The interface allows any number of parallel execution unit
-- As an example, two Meiko FPUs and two FMOVE units have been attached
------------------------------------------------------------------------------
-- FPU support unit - performs FMOVS, FNEGS, FABSS
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.iface.all;
entity fpaux is
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end;
architecture rtl of fpaux is
type reg_type is record
op : std_logic_vector (31 downto 0); -- operand
ins : std_logic_vector (1 downto 0); -- operand
end record;
signal r, rin : reg_type;
begin
comb: process(rst, eui, r)
variable rv : reg_type;
variable ready : std_logic;
variable sign : std_logic;
begin
rv := r;
if eui.start = '1' then rv.ins := eui.opcode(3 downto 2); end if;
if eui.load = '1' then rv.op := eui.op2(63 downto 32); end if;
case r.ins is
when "00" => sign := r.op(31); -- fmovs
when "01" => sign := not r.op(31); -- fnegs
when others => sign := '0'; -- fabss
end case;
euo.res(63 downto 29) <= sign & "000" & r.op(30 downto 0);
euo.res(28 downto 0) <= (others => '0');
euo.busy <= '0';
euo.exc <= (others => '0');
euo.cc <= (others => '0');
rin <= rv;
end process;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.ramlib.all;
use work.fpulib.all;
-- pragma translate_off
library MMS;
use MMS.stdioimp.all;
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp is
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp is
constant EUTYPES : integer := 1; -- number of execution unit types
--constant EUTYPES : integer := 1; -- number of execution unit types
constant EU1NUM : integer := 2; -- number of execution unit 1 types
constant EU2NUM : integer := 1; -- number of execution unit 2 types
constant EUMAX : integer := 2; -- maximum number of any execution unit
--constant EUTOT : integer := 2; -- total number of execution units
constant EUTOT : integer := 2; -- total number of execution units
subtype euindex is integer range 0 to EUMAX-1;
subtype eumindex is integer range 0 to EUTOT-1;
subtype eutindex is integer range 0 to EUTYPES-1;
-- array to define how many execution units of each type
type euconf_arr is array (0 to 2) of euindex; -- one more than necessay to avoid modeltech bug
constant euconf : euconf_arr := (EU1NUM-1, EU2NUM-1,0);
--constant euconf : euconf_arr := (EU1NUM,1);
type eu_fifo_arr is array (0 to EUTOT-1) of eutindex;
type eu_fifo_type is record
first : eumindex;
last : eumindex;
fifo : eu_fifo_arr;
end record;
type euq_type is record
first : euindex;
last : euindex;
end record;
type euq_arr is array (0 to EUTYPES-1) of euq_type;
type rfi_type is record
raddr1 : std_logic_vector (3 downto 0);
raddr2 : std_logic_vector (3 downto 0);
waddr : std_logic_vector (3 downto 0);
wdata : std_logic_vector (63 downto 0);
wren : std_logic_vector(1 downto 0);
end record;
type rfo_type is record
rdata1 : std_logic_vector (63 downto 0);
rdata2 : std_logic_vector (63 downto 0);
end record;
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
first : euindex;
end record;
type unit_status_type is (exception, free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wb : std_logic; -- result being written back
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
eufirst : euindex;
eulast : euindex;
sdep : std_logic; -- data dependency ex/me/wr
eut : integer range 0 to EUTYPES-1; -- type EU to start
eui : integer range 0 to EUMAX-1; -- index EU to start
start : std_logic; -- start EU
weut : integer range 0 to EUTYPES-1; -- write stage eut
weui : integer range 0 to EUMAX-1; -- write stage eui
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
state : execstate; -- using rs1
end record;
type unit_ctrl_arr is array (0 to EUMAX-1) of unit_ctrl;
type unit_ctrl_arr_arr is array (0 to EUTYPES-1) of unit_ctrl_arr;
type eui_arr is array (0 to EUMAX-1) of cp_unit_in_type;
type euo_arr is array (0 to EUMAX-1) of cp_unit_out_type;
type eui_arr_arr is array (0 to EUTYPES) of eui_arr;
type euo_arr_arr is array (0 to EUTYPES) of euo_arr;
signal vcc, gnd : std_logic;
signal rfi : rfi_type;
signal rfo : rfo_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : eui_arr_arr;
signal euo : euo_arr_arr;
signal eu, euin : unit_ctrl_arr_arr;
signal euq, euqin : euq_arr;
signal euf, eufin : eu_fifo_type;
component fpaux
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end component;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
function ddepcheck (rs1, rs2 : std_logic_vector;
rreg1, rreg2, rs1d, rs2d : std_logic; eu : unit_ctrl_arr_arr;
euo : euo_arr_arr) return std_logic is
variable ddep : std_logic;
variable r1, r2 : std_logic_vector(4 downto 0);
begin
ddep := '0'; r1 := rs1; r2 := rs2;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if (eu(i)(j).status = started) or (eu(i)(j).status = ready) then
if rreg1 = '1' then ddep := ddep or srccheck(r1, rs1d, eu(i)(j)); end if;
if rreg2 = '1' then ddep := ddep or srccheck(r2, rs2d, eu(i)(j)); end if;
end if;
end loop;
end loop;
return(ddep);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi, rfo, holdn, xholdn,
euo, euf, euq, rst)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl_arr_arr;
variable euqv : euq_arr;
variable euiv : eui_arr_arr;
variable eufv : eu_fifo_type;
variable euti : eumindex;
variable euqi : euindex;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx; ctrl.first := ex.first;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0';
rv.weut := r.eut; rv.weui := r.eui;
rxv.start := '0'; rv.eut := 0; rv.eui := 0; rv.sdep := '0';
euv := eu; euqv := euq; eufv := euf;
euti := euf.fifo(euf.last); euqi := euq(euti).last;
if (euf.last /= euf.first) or (eu(euti)(euqi).status = exception)
then qne := '1'; else qne := '0'; end if;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv(i)(j).start := '0'; euiv(i)(j).load := '0';
euiv(i)(j).flush := eu(i)(j).rst or euin(i)(j).rst;
euv(i)(j).wb := '0';
euv(i)(j).rst := not rst;
if (eu(i)(j).status = started) and (euo(i)(j).busy = '0') then
euv(i)(j).status := ready;
end if;
if (eu(i)(j).status > free) then
ccv := ccv or eu(i)(j).wrcc;
end if;
end loop;
end loop;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
for i in 0 to EUTYPES-1 loop -- dst interlock
for j in 0 to euconf(i) loop
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin(i)(j));
end loop;
end loop;
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin(i)(j));
end loop;
end loop;
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if eu(i)(j).status > free then ldlock := '1'; end if;
end loop;
end loop;
end if;
end if;
-- FIX ME - add check for not yet commited cpins in pipeline
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ctrl.cpins := none;
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi.raddr1 <= rs1(4 downto 1); rfi.raddr2 <= rs2(4 downto 1);
cpo.ldlock <= ldlock;
op1 := rfo.rdata1; op2 := rfo.rdata2;
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu(euti)(euqi).pc;
else stdata := eu(euti)(euqi).inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" & FPUVER &
rx.csr.tt & qne & '0' & rx.csr.cc & rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check for source operand dependency with scheduled instructions
if (ex.cpins = cpop) then
rv.sdep := ddepcheck(cpi.ex.inst(18 downto 14), cpi.ex.inst(4 downto 0),
ex.rreg1, ex.rreg2, ex.rs1d, ex.rs2d, eu, euo);
end if;
-- select execution unit type
if (cpi.ex.inst(12 downto 9) = "0000") and (EUTYPES > 1) then
rv.eut := EUTYPES-1; -- use exection unit 1
else
rv.eut := 0; -- use exection unit 0
end if;
-- check if an execution unit is available
if (ex.cpins = cpop) and (holdn = '1') and (cpi.flush = '0') then
rv.eui := euq(rv.eut).first;
ccv := ccv or ex.wrcc;
if (rv.sdep = '0') and (eu(rv.eut)(euq(rv.eut).first).status = free)
then
rxv.start := '1';
euiv(rv.eut)(rv.eui).start := '1';
euv(rv.eut)(rv.eui).status := started;
euv(rv.eut)(rv.eui).rd := cpi.ex.inst(29 downto 25);
euv(rv.eut)(rv.eui).rs1 := cpi.ex.inst(18 downto 14);
euv(rv.eut)(rv.eui).rs2 := cpi.ex.inst(4 downto 0);
euv(rv.eut)(rv.eui).wreg := ex.wreg;
euv(rv.eut)(rv.eui).rreg1 := ex.rreg1;
euv(rv.eut)(rv.eui).rreg2 := ex.rreg2;
euv(rv.eut)(rv.eui).rs1d := ex.rs1d;
euv(rv.eut)(rv.eui).rs2d := ex.rs2d;
euv(rv.eut)(rv.eui).rdd := ex.rdd;
euv(rv.eut)(rv.eui).wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
ctrl.first := euf.first;
eufv.fifo(euf.first) := rv.eut;
if euq(rv.eut).first = euconf(rv.eut) then euqv(rv.eut).first := 0;
else euqv(rv.eut).first := euqv(rv.eut).first + 1; end if;
if euf.first = (EUTOT-1) then eufv.first := 0;
else eufv.first := eufv.first + 1; end if;
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
ddep := ddepcheck(cpi.me.inst(18 downto 14), cpi.me.inst(4 downto 0),
me.rreg1, me.rreg2, me.rs1d, me.rs2d, eu, euo);
euiv(r.eut)(r.eui).load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
((r.sdep and ddep) = '0') and (euo(r.eut)(euq(r.eut).first).busy = '0')
then
euiv(r.eut)(r.eui).start := not rx.startx;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and (cpi.flush = '0') and
(not ((r.sdep = '1') and (ddep = '1'))) and
((eu(r.eut)(r.eui).status <= free) or
(euin(r.eut)(r.eui).wb = '1'))
then
euiv(r.eut)(r.eui).load := rx.starty;
euiv(r.eut)(r.eui).start := not (rx.starty or rx.startx);
if eu(r.eut)(r.eui).status /= exception then
euv(r.eut)(r.eui).status := started;
end if;
euv(r.eut)(r.eui).rs1 := cpi.me.inst(18 downto 14);
euv(r.eut)(r.eui).rs2 := cpi.me.inst(4 downto 0);
euv(r.eut)(r.eui).rd := cpi.me.inst(29 downto 25);
euv(r.eut)(r.eui).wreg := me.wreg;
euv(r.eut)(r.eui).rreg1 := me.rreg1;
euv(r.eut)(r.eui).rreg2 := me.rreg2;
euv(r.eut)(r.eui).rs1d := me.rs1d;
euv(r.eut)(r.eui).rs2d := me.rs2d;
euv(r.eut)(r.eui).rdd := me.rdd;
euv(r.eut)(r.eui).wrcc := me.wrcc;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
rxv.starty := euiv(r.eut)(r.eui).start;
rxv.startx := (rx.startx or euiv(r.eut)(r.eui).start) and not holdn;
ccv := ccv or me.wrcc;
if cpi.flush = '1' then rxv.holdn := '1'; end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi.wren(0) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(63 downto 32) := rfi.wdata(63 downto 32);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(63 downto 32) := rfi.wdata(63 downto 32);
end if;
end if;
if rfi.wren(1) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(31 downto 0) := rfi.wdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(31 downto 0) := rfi.wdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).op1 := op1; euiv(i)(j).op2 := op2;
end loop;
end loop;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if cpi.flush = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv(euti)(euqi).status := free;
euv(euti)(euqi).rst := '1';
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if (euf.last /= euf.first) then
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
end if;
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
euv(r.weut)(r.weui).inst := cpi.wr.inst;
euv(r.weut)(r.weui).pc := cpi.wr.pc;
when others => null;
end case;
end if;
-- flush EU if trap was taken
if ((holdn and cpi.flush) = '1') and (EUTOT > 1) then
case wr.cpins is
when cpop =>
if eu(r.weut)(r.weui).status /= exception then
euv(r.weut)(r.weui).rst := '1';
euv(r.weut)(r.weui).status := free;
end if;
eufv.first := wr.first;
euqv(r.eut).first := r.eut;
euqv(r.weut).first := r.weut;
when others => null;
end case;
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu(euti)(euqi).rd(4 downto 1);
if eu(euti)(euqi).rdd = '1' then rtdata := euo(euti)(euqi).res;
else
rtdata(63 downto 32) := euo(euti)(euqi).res(63) &
euo(euti)(euqi).res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (holdn & holdn);
if ((euo(euti)(euqi).exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo(euti)(euqi).exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu(euti)(euqi).status = ready) and
(rx.state = nominal)
then
waddr := rtaddr; wrdata := rtdata;
if cpexc = '0' then
if (eu(euti)(euqi).wreg) = '1' then
if (eu(euti)(euqi).rdd) = '1' then wren := "11";
else
wren(0) := not eu(euti)(euqi).rd(0);
wren(1) := eu(euti)(euqi).rd(0);
end if;
end if;
if eu(euti)(euqi).wrcc = '1' then
rxv.csr.cc := euo(euti)(euqi).cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo(euti)(euqi).exc(4 downto 0);
if euv(euti)(euqi).status = ready then
euv(euti)(euqi).status := free;
end if;
euv(euti)(euqi).wb := '1';
rxv.csr.cexc := euo(euti)(euqi).exc(4 downto 0);
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
else
euv(euti)(euqi).status := exception;
rxv.state := excpend;
if (euo(euti)(euqi).exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi.waddr <= waddr;
rfi.wren <= wren;
rfi.wdata <= wrdata;
-- reset
if rst = '0' then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop euv(i)(j).status := free; end loop;
euqv(i).first := 0; euqv(i).last := 0;
end loop;
eufv.first := 0; eufv.last := 0; rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0';
ctrl.first := 0;
end if;
euin <= euv;
eui <= euiv;
eufin <= eufv;
euqin <= euqv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk(0)) then
if holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
euq <= euqin; euf <= eufin;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if euin(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).wb = '1' then
pc := eu(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).pc;
else pc := cpi.wr.pc; end if;
if (rfi.wren(0) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '0') &
" = " & tost(rfi.wdata(63 downto 32)));
end if;
if (rfi.wren(1) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '1') &
" = " & tost(rfi.wdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- simple 3-port register file made up of 4 parallel dprams
dp00: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr1, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata1(63 downto 32));
dp01: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr1, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata1(31 downto 0));
dp10: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr2, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata2(63 downto 32));
dp11: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr2, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata2(31 downto 0));
gl0 : for i in 0 to euconf(0) generate
fpu0 : fpu port map (
ss_clock => clk(0),
FpInst => eui(0)(i).opcode,
FpOp => eui(0)(i).start,
FpLd => eui(0)(i).load,
Reset => eui(0)(i).flush,
fprf_dout1 => eui(0)(i).op1,
fprf_dout2 => eui(0)(i).op2,
RoundingMode => rx.csr.rd,
FpBusy => euo(0)(i).busy,
FracResult => euo(0)(i).res(51 downto 0),
ExpResult => euo(0)(i).res(62 downto 52),
SignResult => euo(0)(i).res(63),
SNnotDB => open,
Excep => euo(0)(i).exc,
ConditionCodes => euo(0)(i).cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end generate;
fpauxgen : if EUTYPES > 1 generate
gl1 : for i in 0 to euconf(1) generate
eu1 : fpaux port map (rst, clk(0), eui(1)(i), euo(1)(i));
end generate;
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point co-processor interface
-- The interface allows any number of parallel execution unit
-- As an example, two Meiko FPUs and two FMOVE units have been attached
------------------------------------------------------------------------------
-- FPU support unit - performs FMOVS, FNEGS, FABSS
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.iface.all;
entity fpaux is
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end;
architecture rtl of fpaux is
type reg_type is record
op : std_logic_vector (31 downto 0); -- operand
ins : std_logic_vector (1 downto 0); -- operand
end record;
signal r, rin : reg_type;
begin
comb: process(rst, eui, r)
variable rv : reg_type;
variable ready : std_logic;
variable sign : std_logic;
begin
rv := r;
if eui.start = '1' then rv.ins := eui.opcode(3 downto 2); end if;
if eui.load = '1' then rv.op := eui.op2(63 downto 32); end if;
case r.ins is
when "00" => sign := r.op(31); -- fmovs
when "01" => sign := not r.op(31); -- fnegs
when others => sign := '0'; -- fabss
end case;
euo.res(63 downto 29) <= sign & "000" & r.op(30 downto 0);
euo.res(28 downto 0) <= (others => '0');
euo.busy <= '0';
euo.exc <= (others => '0');
euo.cc <= (others => '0');
rin <= rv;
end process;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.ramlib.all;
use work.fpulib.all;
-- pragma translate_off
library MMS;
use MMS.stdioimp.all;
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp is
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp is
constant EUTYPES : integer := 1; -- number of execution unit types
--constant EUTYPES : integer := 1; -- number of execution unit types
constant EU1NUM : integer := 2; -- number of execution unit 1 types
constant EU2NUM : integer := 1; -- number of execution unit 2 types
constant EUMAX : integer := 2; -- maximum number of any execution unit
--constant EUTOT : integer := 2; -- total number of execution units
constant EUTOT : integer := 2; -- total number of execution units
subtype euindex is integer range 0 to EUMAX-1;
subtype eumindex is integer range 0 to EUTOT-1;
subtype eutindex is integer range 0 to EUTYPES-1;
-- array to define how many execution units of each type
type euconf_arr is array (0 to 2) of euindex; -- one more than necessay to avoid modeltech bug
constant euconf : euconf_arr := (EU1NUM-1, EU2NUM-1,0);
--constant euconf : euconf_arr := (EU1NUM,1);
type eu_fifo_arr is array (0 to EUTOT-1) of eutindex;
type eu_fifo_type is record
first : eumindex;
last : eumindex;
fifo : eu_fifo_arr;
end record;
type euq_type is record
first : euindex;
last : euindex;
end record;
type euq_arr is array (0 to EUTYPES-1) of euq_type;
type rfi_type is record
raddr1 : std_logic_vector (3 downto 0);
raddr2 : std_logic_vector (3 downto 0);
waddr : std_logic_vector (3 downto 0);
wdata : std_logic_vector (63 downto 0);
wren : std_logic_vector(1 downto 0);
end record;
type rfo_type is record
rdata1 : std_logic_vector (63 downto 0);
rdata2 : std_logic_vector (63 downto 0);
end record;
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
first : euindex;
end record;
type unit_status_type is (exception, free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wb : std_logic; -- result being written back
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
eufirst : euindex;
eulast : euindex;
sdep : std_logic; -- data dependency ex/me/wr
eut : integer range 0 to EUTYPES-1; -- type EU to start
eui : integer range 0 to EUMAX-1; -- index EU to start
start : std_logic; -- start EU
weut : integer range 0 to EUTYPES-1; -- write stage eut
weui : integer range 0 to EUMAX-1; -- write stage eui
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
state : execstate; -- using rs1
end record;
type unit_ctrl_arr is array (0 to EUMAX-1) of unit_ctrl;
type unit_ctrl_arr_arr is array (0 to EUTYPES-1) of unit_ctrl_arr;
type eui_arr is array (0 to EUMAX-1) of cp_unit_in_type;
type euo_arr is array (0 to EUMAX-1) of cp_unit_out_type;
type eui_arr_arr is array (0 to EUTYPES) of eui_arr;
type euo_arr_arr is array (0 to EUTYPES) of euo_arr;
signal vcc, gnd : std_logic;
signal rfi : rfi_type;
signal rfo : rfo_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : eui_arr_arr;
signal euo : euo_arr_arr;
signal eu, euin : unit_ctrl_arr_arr;
signal euq, euqin : euq_arr;
signal euf, eufin : eu_fifo_type;
component fpaux
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end component;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
function ddepcheck (rs1, rs2 : std_logic_vector;
rreg1, rreg2, rs1d, rs2d : std_logic; eu : unit_ctrl_arr_arr;
euo : euo_arr_arr) return std_logic is
variable ddep : std_logic;
variable r1, r2 : std_logic_vector(4 downto 0);
begin
ddep := '0'; r1 := rs1; r2 := rs2;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if (eu(i)(j).status = started) or (eu(i)(j).status = ready) then
if rreg1 = '1' then ddep := ddep or srccheck(r1, rs1d, eu(i)(j)); end if;
if rreg2 = '1' then ddep := ddep or srccheck(r2, rs2d, eu(i)(j)); end if;
end if;
end loop;
end loop;
return(ddep);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi, rfo, holdn, xholdn,
euo, euf, euq, rst)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl_arr_arr;
variable euqv : euq_arr;
variable euiv : eui_arr_arr;
variable eufv : eu_fifo_type;
variable euti : eumindex;
variable euqi : euindex;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx; ctrl.first := ex.first;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0';
rv.weut := r.eut; rv.weui := r.eui;
rxv.start := '0'; rv.eut := 0; rv.eui := 0; rv.sdep := '0';
euv := eu; euqv := euq; eufv := euf;
euti := euf.fifo(euf.last); euqi := euq(euti).last;
if (euf.last /= euf.first) or (eu(euti)(euqi).status = exception)
then qne := '1'; else qne := '0'; end if;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv(i)(j).start := '0'; euiv(i)(j).load := '0';
euiv(i)(j).flush := eu(i)(j).rst or euin(i)(j).rst;
euv(i)(j).wb := '0';
euv(i)(j).rst := not rst;
if (eu(i)(j).status = started) and (euo(i)(j).busy = '0') then
euv(i)(j).status := ready;
end if;
if (eu(i)(j).status > free) then
ccv := ccv or eu(i)(j).wrcc;
end if;
end loop;
end loop;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
for i in 0 to EUTYPES-1 loop -- dst interlock
for j in 0 to euconf(i) loop
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin(i)(j));
end loop;
end loop;
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin(i)(j));
end loop;
end loop;
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if eu(i)(j).status > free then ldlock := '1'; end if;
end loop;
end loop;
end if;
end if;
-- FIX ME - add check for not yet commited cpins in pipeline
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ctrl.cpins := none;
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi.raddr1 <= rs1(4 downto 1); rfi.raddr2 <= rs2(4 downto 1);
cpo.ldlock <= ldlock;
op1 := rfo.rdata1; op2 := rfo.rdata2;
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu(euti)(euqi).pc;
else stdata := eu(euti)(euqi).inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" & FPUVER &
rx.csr.tt & qne & '0' & rx.csr.cc & rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check for source operand dependency with scheduled instructions
if (ex.cpins = cpop) then
rv.sdep := ddepcheck(cpi.ex.inst(18 downto 14), cpi.ex.inst(4 downto 0),
ex.rreg1, ex.rreg2, ex.rs1d, ex.rs2d, eu, euo);
end if;
-- select execution unit type
if (cpi.ex.inst(12 downto 9) = "0000") and (EUTYPES > 1) then
rv.eut := EUTYPES-1; -- use exection unit 1
else
rv.eut := 0; -- use exection unit 0
end if;
-- check if an execution unit is available
if (ex.cpins = cpop) and (holdn = '1') and (cpi.flush = '0') then
rv.eui := euq(rv.eut).first;
ccv := ccv or ex.wrcc;
if (rv.sdep = '0') and (eu(rv.eut)(euq(rv.eut).first).status = free)
then
rxv.start := '1';
euiv(rv.eut)(rv.eui).start := '1';
euv(rv.eut)(rv.eui).status := started;
euv(rv.eut)(rv.eui).rd := cpi.ex.inst(29 downto 25);
euv(rv.eut)(rv.eui).rs1 := cpi.ex.inst(18 downto 14);
euv(rv.eut)(rv.eui).rs2 := cpi.ex.inst(4 downto 0);
euv(rv.eut)(rv.eui).wreg := ex.wreg;
euv(rv.eut)(rv.eui).rreg1 := ex.rreg1;
euv(rv.eut)(rv.eui).rreg2 := ex.rreg2;
euv(rv.eut)(rv.eui).rs1d := ex.rs1d;
euv(rv.eut)(rv.eui).rs2d := ex.rs2d;
euv(rv.eut)(rv.eui).rdd := ex.rdd;
euv(rv.eut)(rv.eui).wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
ctrl.first := euf.first;
eufv.fifo(euf.first) := rv.eut;
if euq(rv.eut).first = euconf(rv.eut) then euqv(rv.eut).first := 0;
else euqv(rv.eut).first := euqv(rv.eut).first + 1; end if;
if euf.first = (EUTOT-1) then eufv.first := 0;
else eufv.first := eufv.first + 1; end if;
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
ddep := ddepcheck(cpi.me.inst(18 downto 14), cpi.me.inst(4 downto 0),
me.rreg1, me.rreg2, me.rs1d, me.rs2d, eu, euo);
euiv(r.eut)(r.eui).load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
((r.sdep and ddep) = '0') and (euo(r.eut)(euq(r.eut).first).busy = '0')
then
euiv(r.eut)(r.eui).start := not rx.startx;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and (cpi.flush = '0') and
(not ((r.sdep = '1') and (ddep = '1'))) and
((eu(r.eut)(r.eui).status <= free) or
(euin(r.eut)(r.eui).wb = '1'))
then
euiv(r.eut)(r.eui).load := rx.starty;
euiv(r.eut)(r.eui).start := not (rx.starty or rx.startx);
if eu(r.eut)(r.eui).status /= exception then
euv(r.eut)(r.eui).status := started;
end if;
euv(r.eut)(r.eui).rs1 := cpi.me.inst(18 downto 14);
euv(r.eut)(r.eui).rs2 := cpi.me.inst(4 downto 0);
euv(r.eut)(r.eui).rd := cpi.me.inst(29 downto 25);
euv(r.eut)(r.eui).wreg := me.wreg;
euv(r.eut)(r.eui).rreg1 := me.rreg1;
euv(r.eut)(r.eui).rreg2 := me.rreg2;
euv(r.eut)(r.eui).rs1d := me.rs1d;
euv(r.eut)(r.eui).rs2d := me.rs2d;
euv(r.eut)(r.eui).rdd := me.rdd;
euv(r.eut)(r.eui).wrcc := me.wrcc;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
rxv.starty := euiv(r.eut)(r.eui).start;
rxv.startx := (rx.startx or euiv(r.eut)(r.eui).start) and not holdn;
ccv := ccv or me.wrcc;
if cpi.flush = '1' then rxv.holdn := '1'; end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi.wren(0) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(63 downto 32) := rfi.wdata(63 downto 32);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(63 downto 32) := rfi.wdata(63 downto 32);
end if;
end if;
if rfi.wren(1) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(31 downto 0) := rfi.wdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(31 downto 0) := rfi.wdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).op1 := op1; euiv(i)(j).op2 := op2;
end loop;
end loop;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if cpi.flush = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv(euti)(euqi).status := free;
euv(euti)(euqi).rst := '1';
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if (euf.last /= euf.first) then
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
end if;
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
euv(r.weut)(r.weui).inst := cpi.wr.inst;
euv(r.weut)(r.weui).pc := cpi.wr.pc;
when others => null;
end case;
end if;
-- flush EU if trap was taken
if ((holdn and cpi.flush) = '1') and (EUTOT > 1) then
case wr.cpins is
when cpop =>
if eu(r.weut)(r.weui).status /= exception then
euv(r.weut)(r.weui).rst := '1';
euv(r.weut)(r.weui).status := free;
end if;
eufv.first := wr.first;
euqv(r.eut).first := r.eut;
euqv(r.weut).first := r.weut;
when others => null;
end case;
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu(euti)(euqi).rd(4 downto 1);
if eu(euti)(euqi).rdd = '1' then rtdata := euo(euti)(euqi).res;
else
rtdata(63 downto 32) := euo(euti)(euqi).res(63) &
euo(euti)(euqi).res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (holdn & holdn);
if ((euo(euti)(euqi).exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo(euti)(euqi).exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu(euti)(euqi).status = ready) and
(rx.state = nominal)
then
waddr := rtaddr; wrdata := rtdata;
if cpexc = '0' then
if (eu(euti)(euqi).wreg) = '1' then
if (eu(euti)(euqi).rdd) = '1' then wren := "11";
else
wren(0) := not eu(euti)(euqi).rd(0);
wren(1) := eu(euti)(euqi).rd(0);
end if;
end if;
if eu(euti)(euqi).wrcc = '1' then
rxv.csr.cc := euo(euti)(euqi).cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo(euti)(euqi).exc(4 downto 0);
if euv(euti)(euqi).status = ready then
euv(euti)(euqi).status := free;
end if;
euv(euti)(euqi).wb := '1';
rxv.csr.cexc := euo(euti)(euqi).exc(4 downto 0);
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
else
euv(euti)(euqi).status := exception;
rxv.state := excpend;
if (euo(euti)(euqi).exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi.waddr <= waddr;
rfi.wren <= wren;
rfi.wdata <= wrdata;
-- reset
if rst = '0' then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop euv(i)(j).status := free; end loop;
euqv(i).first := 0; euqv(i).last := 0;
end loop;
eufv.first := 0; eufv.last := 0; rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0';
ctrl.first := 0;
end if;
euin <= euv;
eui <= euiv;
eufin <= eufv;
euqin <= euqv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk(0)) then
if holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
euq <= euqin; euf <= eufin;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if euin(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).wb = '1' then
pc := eu(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).pc;
else pc := cpi.wr.pc; end if;
if (rfi.wren(0) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '0') &
" = " & tost(rfi.wdata(63 downto 32)));
end if;
if (rfi.wren(1) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '1') &
" = " & tost(rfi.wdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- simple 3-port register file made up of 4 parallel dprams
dp00: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr1, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata1(63 downto 32));
dp01: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr1, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata1(31 downto 0));
dp10: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr2, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata2(63 downto 32));
dp11: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr2, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata2(31 downto 0));
gl0 : for i in 0 to euconf(0) generate
fpu0 : fpu port map (
ss_clock => clk(0),
FpInst => eui(0)(i).opcode,
FpOp => eui(0)(i).start,
FpLd => eui(0)(i).load,
Reset => eui(0)(i).flush,
fprf_dout1 => eui(0)(i).op1,
fprf_dout2 => eui(0)(i).op2,
RoundingMode => rx.csr.rd,
FpBusy => euo(0)(i).busy,
FracResult => euo(0)(i).res(51 downto 0),
ExpResult => euo(0)(i).res(62 downto 52),
SignResult => euo(0)(i).res(63),
SNnotDB => open,
Excep => euo(0)(i).exc,
ConditionCodes => euo(0)(i).cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end generate;
fpauxgen : if EUTYPES > 1 generate
gl1 : for i in 0 to euconf(1) generate
eu1 : fpaux port map (rst, clk(0), eui(1)(i), euo(1)(i));
end generate;
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point co-processor interface
-- The interface allows any number of parallel execution unit
-- As an example, two Meiko FPUs and two FMOVE units have been attached
------------------------------------------------------------------------------
-- FPU support unit - performs FMOVS, FNEGS, FABSS
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.iface.all;
entity fpaux is
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end;
architecture rtl of fpaux is
type reg_type is record
op : std_logic_vector (31 downto 0); -- operand
ins : std_logic_vector (1 downto 0); -- operand
end record;
signal r, rin : reg_type;
begin
comb: process(rst, eui, r)
variable rv : reg_type;
variable ready : std_logic;
variable sign : std_logic;
begin
rv := r;
if eui.start = '1' then rv.ins := eui.opcode(3 downto 2); end if;
if eui.load = '1' then rv.op := eui.op2(63 downto 32); end if;
case r.ins is
when "00" => sign := r.op(31); -- fmovs
when "01" => sign := not r.op(31); -- fnegs
when others => sign := '0'; -- fabss
end case;
euo.res(63 downto 29) <= sign & "000" & r.op(30 downto 0);
euo.res(28 downto 0) <= (others => '0');
euo.busy <= '0';
euo.exc <= (others => '0');
euo.cc <= (others => '0');
rin <= rv;
end process;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.ramlib.all;
use work.fpulib.all;
-- pragma translate_off
library MMS;
use MMS.stdioimp.all;
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp is
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp is
constant EUTYPES : integer := 1; -- number of execution unit types
--constant EUTYPES : integer := 1; -- number of execution unit types
constant EU1NUM : integer := 2; -- number of execution unit 1 types
constant EU2NUM : integer := 1; -- number of execution unit 2 types
constant EUMAX : integer := 2; -- maximum number of any execution unit
--constant EUTOT : integer := 2; -- total number of execution units
constant EUTOT : integer := 2; -- total number of execution units
subtype euindex is integer range 0 to EUMAX-1;
subtype eumindex is integer range 0 to EUTOT-1;
subtype eutindex is integer range 0 to EUTYPES-1;
-- array to define how many execution units of each type
type euconf_arr is array (0 to 2) of euindex; -- one more than necessay to avoid modeltech bug
constant euconf : euconf_arr := (EU1NUM-1, EU2NUM-1,0);
--constant euconf : euconf_arr := (EU1NUM,1);
type eu_fifo_arr is array (0 to EUTOT-1) of eutindex;
type eu_fifo_type is record
first : eumindex;
last : eumindex;
fifo : eu_fifo_arr;
end record;
type euq_type is record
first : euindex;
last : euindex;
end record;
type euq_arr is array (0 to EUTYPES-1) of euq_type;
type rfi_type is record
raddr1 : std_logic_vector (3 downto 0);
raddr2 : std_logic_vector (3 downto 0);
waddr : std_logic_vector (3 downto 0);
wdata : std_logic_vector (63 downto 0);
wren : std_logic_vector(1 downto 0);
end record;
type rfo_type is record
rdata1 : std_logic_vector (63 downto 0);
rdata2 : std_logic_vector (63 downto 0);
end record;
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
first : euindex;
end record;
type unit_status_type is (exception, free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wb : std_logic; -- result being written back
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
eufirst : euindex;
eulast : euindex;
sdep : std_logic; -- data dependency ex/me/wr
eut : integer range 0 to EUTYPES-1; -- type EU to start
eui : integer range 0 to EUMAX-1; -- index EU to start
start : std_logic; -- start EU
weut : integer range 0 to EUTYPES-1; -- write stage eut
weui : integer range 0 to EUMAX-1; -- write stage eui
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
state : execstate; -- using rs1
end record;
type unit_ctrl_arr is array (0 to EUMAX-1) of unit_ctrl;
type unit_ctrl_arr_arr is array (0 to EUTYPES-1) of unit_ctrl_arr;
type eui_arr is array (0 to EUMAX-1) of cp_unit_in_type;
type euo_arr is array (0 to EUMAX-1) of cp_unit_out_type;
type eui_arr_arr is array (0 to EUTYPES) of eui_arr;
type euo_arr_arr is array (0 to EUTYPES) of euo_arr;
signal vcc, gnd : std_logic;
signal rfi : rfi_type;
signal rfo : rfo_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : eui_arr_arr;
signal euo : euo_arr_arr;
signal eu, euin : unit_ctrl_arr_arr;
signal euq, euqin : euq_arr;
signal euf, eufin : eu_fifo_type;
component fpaux
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end component;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
function ddepcheck (rs1, rs2 : std_logic_vector;
rreg1, rreg2, rs1d, rs2d : std_logic; eu : unit_ctrl_arr_arr;
euo : euo_arr_arr) return std_logic is
variable ddep : std_logic;
variable r1, r2 : std_logic_vector(4 downto 0);
begin
ddep := '0'; r1 := rs1; r2 := rs2;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if (eu(i)(j).status = started) or (eu(i)(j).status = ready) then
if rreg1 = '1' then ddep := ddep or srccheck(r1, rs1d, eu(i)(j)); end if;
if rreg2 = '1' then ddep := ddep or srccheck(r2, rs2d, eu(i)(j)); end if;
end if;
end loop;
end loop;
return(ddep);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi, rfo, holdn, xholdn,
euo, euf, euq, rst)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl_arr_arr;
variable euqv : euq_arr;
variable euiv : eui_arr_arr;
variable eufv : eu_fifo_type;
variable euti : eumindex;
variable euqi : euindex;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx; ctrl.first := ex.first;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0';
rv.weut := r.eut; rv.weui := r.eui;
rxv.start := '0'; rv.eut := 0; rv.eui := 0; rv.sdep := '0';
euv := eu; euqv := euq; eufv := euf;
euti := euf.fifo(euf.last); euqi := euq(euti).last;
if (euf.last /= euf.first) or (eu(euti)(euqi).status = exception)
then qne := '1'; else qne := '0'; end if;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv(i)(j).start := '0'; euiv(i)(j).load := '0';
euiv(i)(j).flush := eu(i)(j).rst or euin(i)(j).rst;
euv(i)(j).wb := '0';
euv(i)(j).rst := not rst;
if (eu(i)(j).status = started) and (euo(i)(j).busy = '0') then
euv(i)(j).status := ready;
end if;
if (eu(i)(j).status > free) then
ccv := ccv or eu(i)(j).wrcc;
end if;
end loop;
end loop;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
for i in 0 to EUTYPES-1 loop -- dst interlock
for j in 0 to euconf(i) loop
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin(i)(j));
end loop;
end loop;
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin(i)(j));
end loop;
end loop;
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if eu(i)(j).status > free then ldlock := '1'; end if;
end loop;
end loop;
end if;
end if;
-- FIX ME - add check for not yet commited cpins in pipeline
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ctrl.cpins := none;
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi.raddr1 <= rs1(4 downto 1); rfi.raddr2 <= rs2(4 downto 1);
cpo.ldlock <= ldlock;
op1 := rfo.rdata1; op2 := rfo.rdata2;
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu(euti)(euqi).pc;
else stdata := eu(euti)(euqi).inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" & FPUVER &
rx.csr.tt & qne & '0' & rx.csr.cc & rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check for source operand dependency with scheduled instructions
if (ex.cpins = cpop) then
rv.sdep := ddepcheck(cpi.ex.inst(18 downto 14), cpi.ex.inst(4 downto 0),
ex.rreg1, ex.rreg2, ex.rs1d, ex.rs2d, eu, euo);
end if;
-- select execution unit type
if (cpi.ex.inst(12 downto 9) = "0000") and (EUTYPES > 1) then
rv.eut := EUTYPES-1; -- use exection unit 1
else
rv.eut := 0; -- use exection unit 0
end if;
-- check if an execution unit is available
if (ex.cpins = cpop) and (holdn = '1') and (cpi.flush = '0') then
rv.eui := euq(rv.eut).first;
ccv := ccv or ex.wrcc;
if (rv.sdep = '0') and (eu(rv.eut)(euq(rv.eut).first).status = free)
then
rxv.start := '1';
euiv(rv.eut)(rv.eui).start := '1';
euv(rv.eut)(rv.eui).status := started;
euv(rv.eut)(rv.eui).rd := cpi.ex.inst(29 downto 25);
euv(rv.eut)(rv.eui).rs1 := cpi.ex.inst(18 downto 14);
euv(rv.eut)(rv.eui).rs2 := cpi.ex.inst(4 downto 0);
euv(rv.eut)(rv.eui).wreg := ex.wreg;
euv(rv.eut)(rv.eui).rreg1 := ex.rreg1;
euv(rv.eut)(rv.eui).rreg2 := ex.rreg2;
euv(rv.eut)(rv.eui).rs1d := ex.rs1d;
euv(rv.eut)(rv.eui).rs2d := ex.rs2d;
euv(rv.eut)(rv.eui).rdd := ex.rdd;
euv(rv.eut)(rv.eui).wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
ctrl.first := euf.first;
eufv.fifo(euf.first) := rv.eut;
if euq(rv.eut).first = euconf(rv.eut) then euqv(rv.eut).first := 0;
else euqv(rv.eut).first := euqv(rv.eut).first + 1; end if;
if euf.first = (EUTOT-1) then eufv.first := 0;
else eufv.first := eufv.first + 1; end if;
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
ddep := ddepcheck(cpi.me.inst(18 downto 14), cpi.me.inst(4 downto 0),
me.rreg1, me.rreg2, me.rs1d, me.rs2d, eu, euo);
euiv(r.eut)(r.eui).load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
((r.sdep and ddep) = '0') and (euo(r.eut)(euq(r.eut).first).busy = '0')
then
euiv(r.eut)(r.eui).start := not rx.startx;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and (cpi.flush = '0') and
(not ((r.sdep = '1') and (ddep = '1'))) and
((eu(r.eut)(r.eui).status <= free) or
(euin(r.eut)(r.eui).wb = '1'))
then
euiv(r.eut)(r.eui).load := rx.starty;
euiv(r.eut)(r.eui).start := not (rx.starty or rx.startx);
if eu(r.eut)(r.eui).status /= exception then
euv(r.eut)(r.eui).status := started;
end if;
euv(r.eut)(r.eui).rs1 := cpi.me.inst(18 downto 14);
euv(r.eut)(r.eui).rs2 := cpi.me.inst(4 downto 0);
euv(r.eut)(r.eui).rd := cpi.me.inst(29 downto 25);
euv(r.eut)(r.eui).wreg := me.wreg;
euv(r.eut)(r.eui).rreg1 := me.rreg1;
euv(r.eut)(r.eui).rreg2 := me.rreg2;
euv(r.eut)(r.eui).rs1d := me.rs1d;
euv(r.eut)(r.eui).rs2d := me.rs2d;
euv(r.eut)(r.eui).rdd := me.rdd;
euv(r.eut)(r.eui).wrcc := me.wrcc;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
rxv.starty := euiv(r.eut)(r.eui).start;
rxv.startx := (rx.startx or euiv(r.eut)(r.eui).start) and not holdn;
ccv := ccv or me.wrcc;
if cpi.flush = '1' then rxv.holdn := '1'; end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi.wren(0) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(63 downto 32) := rfi.wdata(63 downto 32);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(63 downto 32) := rfi.wdata(63 downto 32);
end if;
end if;
if rfi.wren(1) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(31 downto 0) := rfi.wdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(31 downto 0) := rfi.wdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).op1 := op1; euiv(i)(j).op2 := op2;
end loop;
end loop;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if cpi.flush = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv(euti)(euqi).status := free;
euv(euti)(euqi).rst := '1';
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if (euf.last /= euf.first) then
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
end if;
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
euv(r.weut)(r.weui).inst := cpi.wr.inst;
euv(r.weut)(r.weui).pc := cpi.wr.pc;
when others => null;
end case;
end if;
-- flush EU if trap was taken
if ((holdn and cpi.flush) = '1') and (EUTOT > 1) then
case wr.cpins is
when cpop =>
if eu(r.weut)(r.weui).status /= exception then
euv(r.weut)(r.weui).rst := '1';
euv(r.weut)(r.weui).status := free;
end if;
eufv.first := wr.first;
euqv(r.eut).first := r.eut;
euqv(r.weut).first := r.weut;
when others => null;
end case;
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu(euti)(euqi).rd(4 downto 1);
if eu(euti)(euqi).rdd = '1' then rtdata := euo(euti)(euqi).res;
else
rtdata(63 downto 32) := euo(euti)(euqi).res(63) &
euo(euti)(euqi).res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (holdn & holdn);
if ((euo(euti)(euqi).exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo(euti)(euqi).exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu(euti)(euqi).status = ready) and
(rx.state = nominal)
then
waddr := rtaddr; wrdata := rtdata;
if cpexc = '0' then
if (eu(euti)(euqi).wreg) = '1' then
if (eu(euti)(euqi).rdd) = '1' then wren := "11";
else
wren(0) := not eu(euti)(euqi).rd(0);
wren(1) := eu(euti)(euqi).rd(0);
end if;
end if;
if eu(euti)(euqi).wrcc = '1' then
rxv.csr.cc := euo(euti)(euqi).cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo(euti)(euqi).exc(4 downto 0);
if euv(euti)(euqi).status = ready then
euv(euti)(euqi).status := free;
end if;
euv(euti)(euqi).wb := '1';
rxv.csr.cexc := euo(euti)(euqi).exc(4 downto 0);
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
else
euv(euti)(euqi).status := exception;
rxv.state := excpend;
if (euo(euti)(euqi).exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi.waddr <= waddr;
rfi.wren <= wren;
rfi.wdata <= wrdata;
-- reset
if rst = '0' then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop euv(i)(j).status := free; end loop;
euqv(i).first := 0; euqv(i).last := 0;
end loop;
eufv.first := 0; eufv.last := 0; rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0';
ctrl.first := 0;
end if;
euin <= euv;
eui <= euiv;
eufin <= eufv;
euqin <= euqv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk(0)) then
if holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
euq <= euqin; euf <= eufin;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if euin(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).wb = '1' then
pc := eu(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).pc;
else pc := cpi.wr.pc; end if;
if (rfi.wren(0) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '0') &
" = " & tost(rfi.wdata(63 downto 32)));
end if;
if (rfi.wren(1) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '1') &
" = " & tost(rfi.wdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- simple 3-port register file made up of 4 parallel dprams
dp00: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr1, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata1(63 downto 32));
dp01: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr1, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata1(31 downto 0));
dp10: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr2, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata2(63 downto 32));
dp11: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr2, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata2(31 downto 0));
gl0 : for i in 0 to euconf(0) generate
fpu0 : fpu port map (
ss_clock => clk(0),
FpInst => eui(0)(i).opcode,
FpOp => eui(0)(i).start,
FpLd => eui(0)(i).load,
Reset => eui(0)(i).flush,
fprf_dout1 => eui(0)(i).op1,
fprf_dout2 => eui(0)(i).op2,
RoundingMode => rx.csr.rd,
FpBusy => euo(0)(i).busy,
FracResult => euo(0)(i).res(51 downto 0),
ExpResult => euo(0)(i).res(62 downto 52),
SignResult => euo(0)(i).res(63),
SNnotDB => open,
Excep => euo(0)(i).exc,
ConditionCodes => euo(0)(i).cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end generate;
fpauxgen : if EUTYPES > 1 generate
gl1 : for i in 0 to euconf(1) generate
eu1 : fpaux port map (rst, clk(0), eui(1)(i), euo(1)(i));
end generate;
end generate;
end;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Binarization;
architecture rtl of Binarization is
component Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Binarization_GN;
begin
Binarization_GN_0: if true generate
inst_Binarization_GN_0: Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Binarization;
architecture rtl of Binarization is
component Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Binarization_GN;
begin
Binarization_GN_0: if true generate
inst_Binarization_GN_0: Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
|
-- Pixel_On_Text2 determines if the current pixel is on text and make it easiler to call from verilog
-- param:
-- display text
-- input:
-- VGA clock(the clk you used to update VGA)
-- top left corner of the text area -- positionX, positionY
-- current X and Y position
-- output:
-- a bit that represent whether is the pixel in text
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity Pixel_On_Text2 is
generic(
displayText: string := (others => NUL)
);
port (
clk: in std_logic;
-- top left corner of the text
positionX: in integer;
positionY: in integer;
-- current pixel postion
horzCoord: in integer;
vertCoord: in integer;
pixel: out std_logic := '0'
);
end Pixel_On_Text2;
architecture Behavioral of Pixel_On_Text2 is
signal fontAddress: integer;
-- A row of bit in a charactor, we check if our current (x,y) is 1 in char row
signal charBitInRow: std_logic_vector(FONT_WIDTH-1 downto 0) := (others => '0');
-- char in ASCII code
signal charCode:integer := 0;
-- the position(column) of a charactor in the given text
signal charPosition:integer := 0;
-- the bit position(column) in a charactor
signal bitPosition:integer := 0;
begin
-- (horzCoord - position.x): x positionin the top left of the whole text
charPosition <= (horzCoord - positionX)/FONT_WIDTH + 1;
bitPosition <= (horzCoord - positionX) mod FONT_WIDTH;
charCode <= character'pos(displayText(charPosition));
-- charCode*16: first row of the char
fontAddress <= charCode*16+(vertCoord - positionY);
FontRom: entity work.Font_Rom
port map(
clk => clk,
addr => fontAddress,
fontRow => charBitInRow
);
pixelOn: process(clk)
variable inXRange: boolean := false;
variable inYRange: boolean := false;
begin
if rising_edge(clk) then
-- reset
inXRange := false;
inYRange := false;
pixel <= '0';
-- If current pixel is in the horizontal range of text
if horzCoord >= positionX and horzCoord < positionX + (FONT_WIDTH * displayText'length) then
inXRange := true;
end if;
-- If current pixel is in the vertical range of text
if vertCoord >= positionY and vertCoord < positionY + FONT_HEIGHT then
inYRange := true;
end if;
-- need to check if the pixel is on for text
if inXRange and inYRange then
-- FONT_WIDTH-bitPosition: we are reverting the charactor
if charBitInRow(FONT_WIDTH-bitPosition) = '1' then
pixel <= '1';
end if;
end if;
end if;
end process;
end Behavioral; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(7 downto 0);
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk, sdfb : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal resetn : std_ulogic;
signal pbsw : std_logic_vector(4 downto 1);
signal ledo : std_logic_vector(8 downto 1);
signal memi : memory_in_type;
signal memo : memory_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal s_eth_din : std_logic_vector(31 downto 0);
constant ahbmmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+ CFG_GRETH;
constant BOARD_FREQ : integer := 50000; -- board frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ*CFG_CLKMUL)/CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
sdram_clk_pad : skew_outpad
generic map (tech => padtech, slew => 1, strength => 24, skew => -60)
port map (sdram_clk, sdclkl, rstn);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
resetn <= pbsw(4);
ledo(2) <= not cgo.clklock;
ledo(3) <= pbsw(3);
clk_pad : clkpad generic map (tech => padtech) port map (pll_clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => ahbmmax, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
ledo(8) <= dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1'; dsui.break <= pbsw(1); ledo(1) <= not dsuo.active;
end generate;
end generate;
nodcom : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= u2i.rxd; u2o.txd <= duo.txd; u2o.rtsn <= gnd(0);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- PROM/SDRAM Memory controller ------------------------------------
----------------------------------------------------------------------
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
memi.bwidth <= "00" when CFG_MCTRL_RAM16BIT = 0 else "01";
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0),
wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe, s_eth_din);
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (flash_a(20 downto 0), memo.address(21 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (flash_d(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
data15_pad : iopad generic map (tech => padtech)
port map (flash_d(15), memo.address(0), gnd(0), open);
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
data_pad : iopadv generic map (tech => padtech, width => 16)
port map (flash_d(15 downto 0), memo.data(31 downto 16),
memo.bdrive(0), memi.data(31 downto 16));
end generate;
sa_pad : outpadv generic map (width => 12, tech => padtech)
port map (sdram_a, memo.sa(11 downto 0));
sba1_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(1 downto 0), memo.sa(14 downto 13));
sba2_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(3 downto 2), memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sdram_d(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (sdram_wen, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (sdram_rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdram_casn, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (sdram_dqm, sdo.dqm(3 downto 0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, gnd(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(4));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(4) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts, u1o.rtsn);
ua2 : if (CFG_UART2_ENABLE /= 0) and (CFG_AHB_UART = 0) generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
ua2rx_pad : inpad generic map (tech => padtech) port map (uart2_rxd, u2i.rxd);
ua2tx_pad : outpad generic map (tech => padtech) port map (uart2_txd, u2o.txd);
ua2cts_pad : inpad generic map (tech => padtech) port map (uart2_cts, u2i.ctsn);
ua2rts_pad : outpad generic map (tech => padtech) port map (uart2_rts, u2o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if CFG_GRETH = 0 generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
ereset_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- I/O interface ---------------------------------------------------
-----------------------------------------------------------------------
pb_sw_pad : inpadv generic map (width => 4, tech => padtech)
port map (pb_sw, pbsw);
led_pad : outpadv generic map (width => 8, tech => padtech)
port map (led, ledo);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, gnd(0));
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, vcc(0));
end generate;
rpn_pad : outpad generic map (tech => padtech) port map (flash_rpn, rstn);
wpn_pad : outpad generic map (tech => padtech) port map (flash_wpn, vcc(0));
ready_pad : inpad generic map (tech => padtech) port map (flash_ready, open);
smsc_data_pads : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (smsc_data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), s_eth_din(31-i*8 downto 24-i*8));
end generate;
smsc_addr_pad : outpadv generic map (tech => padtech, width => 15)
port map (smsc_addr, memo.address(15 downto 1));
smsc_nbe_pad : outpadv generic map (tech => padtech, width => 4)
port map (smsc_nbe, s_eth_nbe);
smsc_reset_pad : outpad generic map (tech => padtech)
port map (smsc_resetn, rstn);
smsc_nrd_pad : outpad generic map (tech => padtech)
port map (smsc_nrd, s_eth_readn);
smsc_nwr_pad : outpad generic map (tech => padtech)
port map (smsc_nwr, s_eth_writen);
smsc_ncs_pad : outpad generic map (tech => padtech)
port map (smsc_ncs, memo.iosn);
smsc_aen_pad : outpad generic map (tech => padtech)
port map (smsc_aen, s_eth_aen);
smsc_lclk_pad : outpad generic map (tech => padtech)
port map (smsc_lclk, vcc(0));
smsc_wnr_pad : outpad generic map (tech => padtech)
port map (smsc_wnr, vcc(0));
smsc_rdyrtn_pad : outpad generic map (tech => padtech)
port map (smsc_rdyrtn, vcc(0));
smsc_cycle_pad : outpad generic map (tech => padtech)
port map (smsc_cycle, vcc(0));
smsc_nads_pad : outpad generic map (tech => padtech)
port map (smsc_nads, gnd(0));
-- lcd_data_pad : iopadv generic map (width => 8, tech => padtech)
-- port map (lcd_data, nuo.lcd_data, nuo.lcd_ben, nui.lcd_data);
-- lcd_rs_pad : outpad generic map (tech => padtech)
-- port map (lcd_rs, nuo.lcd_rs);
-- lcd_rw_pad : outpad generic map (tech => padtech)
-- port map (lcd_rw, nuo.lcd_rw );
-- lcd_en_pad : outpad generic map (tech => padtech)
-- port map (lcd_en, nuo.lcd_en);
-- lcd_backl_pad : outpad generic map (tech => padtech)
-- port map (lcd_backl, nuo.lcd_backl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Nuhorizon SP3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity usDMA_Transact is
port (
-- Around the Channel Buffer
usTlp_Req : OUT std_logic;
usTlp_RE : IN std_logic;
usTlp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : IN std_logic;
us_Last_sof : IN std_logic;
us_Last_eof : IN std_logic;
FIFO_Data_Count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
FIFO_Reading : IN std_logic;
-- Upstream reset from MWr channel
usDMA_Channel_Rst : IN std_logic;
-- Upstream Registers from MWr Channel
DMA_us_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : IN std_logic;
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
-- Calculation in advance, for better timing
usHA_is_64b : IN std_logic;
usBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : IN std_logic;
usLeng_Lo7b_True : IN std_logic;
-- from Cpl/D channel
usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Upstream Control Signals from MWr Channel
usDMA_Start : IN std_logic; -- out of 1st dex
usDMA_Stop : IN std_logic; -- out of 1st dex
-- Upstream Control Signals from CplD Channel
usDMA_Start2 : IN std_logic; -- out of consecutive dex
usDMA_Stop2 : IN std_logic; -- out of consecutive dex
-- Upstream DMA Acknowledge to the start command
DMA_Cmd_Ack : OUT std_logic;
-- To Interrupt module
DMA_Done : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
-- To Registers' Group
DMA_us_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- Common ports
trn_clk : IN std_logic
);
end entity usDMA_Transact;
architecture Behavioral of usDMA_Transact is
-- Upstream DMA channel
signal Local_Reset_i : std_logic;
signal DMA_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal cfg_MPS : std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
signal usDMA_MWr_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- DMA calculation
COMPONENT DMA_Calculate
PORT(
-- Downstream Registers from MWr Channel
DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : IN std_logic;
BDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : IN std_logic;
Leng_Lo7b_True : IN std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : OUT std_logic;
-- Only for downstream channel
DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : OUT std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
--
DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Engine control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : OUT std_logic;
ThereIs_Snout : OUT std_logic;
ThereIs_Body : OUT std_logic;
ThereIs_Tail : OUT std_logic;
ThereIs_Dex : OUT std_logic;
HA64bit : OUT std_logic;
Addr_Inc : OUT std_logic;
-- FSM indicators
State_Is_LoadParam : IN std_logic;
State_Is_Snout : IN std_logic;
State_Is_Body : IN std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : IN std_logic_vector(2 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
END COMPONENT;
signal usDMA_PA_Loaded : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_PA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_HA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_BDA_fsm : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usBDA_is_64b_fsm : std_logic;
signal usDMA_PA_snout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_BAR_Number : std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
signal usDMA_Snout_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal usDMA_Body_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal usDMA_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal usNo_More_Bodies : std_logic;
signal usThereIs_Snout : std_logic;
signal usThereIs_Body : std_logic;
signal usThereIs_Tail : std_logic;
signal usThereIs_Dex : std_logic;
signal usHA64bit : std_logic;
signal us_AInc : std_logic;
-- DMA state machine
COMPONENT DMA_FSM
PORT(
-- Fixed information for 1st header of TLP: MRd/MWr
TLP_Has_Payload : IN std_logic;
TLP_Hdr_is_4DW : IN std_logic;
DMA_Addr_Inc : IN std_logic;
DMA_BAR_Number : IN std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
-- FSM control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic;
DMA_Stop : IN std_logic;
DMA_Stop2 : IN std_logic;
No_More_Bodies : IN std_logic;
ThereIs_Snout : IN std_logic;
ThereIs_Body : IN std_logic;
ThereIs_Tail : IN std_logic;
ThereIs_Dex : IN std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : IN std_logic;
DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : IN std_logic;
Done_Condition_2 : IN std_logic;
Done_Condition_3 : IN std_logic;
Done_Condition_4 : IN std_logic;
Done_Condition_5 : IN std_logic;
-- Channel buffer write
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
ChBuf_aFull : IN std_logic;
ChBuf_WrEn : OUT std_logic;
ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : OUT std_logic;
State_Is_Snout : OUT std_logic;
State_Is_Body : OUT std_logic;
State_Is_Tail : OUT std_logic;
DMA_Cmd_Ack : OUT std_logic;
-- To Tx Port
ChBuf_ValidRd : IN std_logic;
BDA_nAligned : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
DMA_Done : OUT std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
END COMPONENT;
-- FSM state indicators
signal usState_Is_LoadParam : std_logic;
signal usState_Is_Snout : std_logic;
signal usState_Is_Body : std_logic;
signal usState_Is_Tail : std_logic;
signal usChBuf_ValidRd : std_logic;
signal usBDA_nAligned : std_logic;
signal usDMA_TimeOut_i : std_logic;
signal usDMA_Busy_i : std_logic;
signal usDMA_Done_i : std_logic;
-- Built-in single-port fifo as downstream DMA channel buffer
-- 128-bit wide, for 64-bit address
component k7_sfifo_15x128
port (
clk : IN std_logic;
rst : IN std_logic;
prog_full : OUT std_logic;
-- wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : OUT std_logic;
-- rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic
);
end component;
-- Signal with DMA_upstream channel abstract buffer
signal usTlp_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_RE_i : std_logic;
signal usTlp_RE_i_r1 : std_logic;
signal usTlp_we : std_logic;
signal usTlp_empty_i : std_logic;
signal usTlp_full : std_logic;
signal usTlp_prog_Full : std_logic;
signal usTlp_pempty : std_logic;
signal usTlp_Npempty_r1 : std_logic;
signal usTlp_Nempty_r1 : std_logic;
signal usTlp_empty_r1 : std_logic;
signal usTlp_empty_r2 : std_logic;
signal usTlp_empty_r3 : std_logic;
signal usTlp_empty_r4 : std_logic;
signal usTlp_prog_Full_r1 : std_logic;
-- Request for output arbitration
signal usTlp_Req_i : std_logic;
signal usTlp_nReq_r1 : std_logic;
signal FIFO_Reading_r1 : std_logic;
signal FIFO_Reading_r2 : std_logic;
signal FIFO_Reading_r3p : std_logic;
signal usTlp_MWr_Leng : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
-- Busy/Done state bits generation
type FSM_Request is (
REQST_Idle
, REQST_1Read
, REQST_Decision
, REQST_nFIFO_Req
, REQST_Quantity
, REQST_FIFO_Req
);
signal FSM_REQ_us : FSM_Request;
begin
-- DMA done signal
DMA_Done <= usDMA_Done_i;
DMA_TimeOut <= usDMA_TimeOut_i;
DMA_Busy <= usDMA_Busy_i;
-- connecting FIFO's signals
usTlp_Qout <= usTlp_Qout_i;
usTlp_Req <= usTlp_Req_i and not FIFO_Reading_r3p;
-- positive local reset
Local_Reset_i <= usDMA_Channel_Rst;
-- Max Payload Size bits
cfg_MPS <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
-- Kernel Engine
us_DMA_Calculation:
DMA_Calculate
PORT MAP(
DMA_PA => DMA_us_PA ,
DMA_HA => DMA_us_HA ,
DMA_BDA => DMA_us_BDA ,
DMA_Length => DMA_us_Length ,
DMA_Control => DMA_us_Control ,
HA_is_64b => usHA_is_64b ,
BDA_is_64b => usBDA_is_64b ,
Leng_Hi19b_True => usLeng_Hi19b_True ,
Leng_Lo7b_True => usLeng_Lo7b_True ,
DMA_PA_Loaded => usDMA_PA_Loaded ,
DMA_PA_Var => usDMA_PA_Var ,
DMA_HA_Var => usDMA_HA_Var ,
DMA_BDA_fsm => usDMA_BDA_fsm ,
BDA_is_64b_fsm => usBDA_is_64b_fsm ,
-- Only for downstream channel
DMA_PA_Snout => usDMA_PA_snout ,
DMA_BAR_Number => usDMA_BAR_Number ,
-- Lengths
DMA_Snout_Length => usDMA_Snout_Length ,
DMA_Body_Length => usDMA_Body_Length ,
DMA_Tail_Length => usDMA_Tail_Length ,
-- Control signals to FSM
No_More_Bodies => usNo_More_Bodies ,
ThereIs_Snout => usThereIs_Snout ,
ThereIs_Body => usThereIs_Body ,
ThereIs_Tail => usThereIs_Tail ,
ThereIs_Dex => usThereIs_Dex ,
HA64bit => usHA64bit ,
Addr_Inc => us_AInc ,
DMA_Start => usDMA_Start ,
DMA_Start2 => usDMA_Start2 ,
State_Is_LoadParam => usState_Is_LoadParam ,
State_Is_Snout => usState_Is_Snout ,
State_Is_Body => usState_Is_Body ,
-- State_Is_Tail => usState_Is_Tail ,
Param_Max_Cfg => cfg_MPS ,
dma_clk => trn_clk ,
dma_reset => Local_Reset_i
);
-- Kernel FSM
us_DMA_StateMachine:
DMA_FSM
PORT MAP(
TLP_Has_Payload => '1' ,
TLP_Hdr_is_4DW => usHA64bit ,
DMA_Addr_Inc => us_AInc ,
DMA_BAR_Number => usDMA_BAR_Number ,
DMA_Start => usDMA_Start ,
DMA_Start2 => usDMA_Start2 ,
DMA_Stop => usDMA_Stop ,
DMA_Stop2 => usDMA_Stop2 ,
-- Control signals to FSM
No_More_Bodies => usNo_More_Bodies ,
ThereIs_Snout => usThereIs_Snout ,
ThereIs_Body => usThereIs_Body ,
ThereIs_Tail => usThereIs_Tail ,
ThereIs_Dex => usThereIs_Dex ,
DMA_PA_Loaded => usDMA_PA_Loaded ,
DMA_PA_Var => usDMA_PA_Var ,
DMA_HA_Var => usDMA_HA_Var ,
DMA_BDA_fsm => usDMA_BDA_fsm ,
BDA_is_64b_fsm => usBDA_is_64b_fsm ,
DMA_Snout_Length => usDMA_Snout_Length ,
DMA_Body_Length => usDMA_Body_Length ,
DMA_Tail_Length => usDMA_Tail_Length ,
ChBuf_ValidRd => usChBuf_ValidRd ,
BDA_nAligned => usBDA_nAligned ,
DMA_TimeOut => usDMA_TimeOut_i ,
DMA_Busy => usDMA_Busy_i ,
DMA_Done => usDMA_Done_i ,
-- DMA_Done_Rise => open ,
Pkt_Tag => usDMA_MWr_Tag ,
Dex_Tag => usDMA_dex_Tag ,
Done_Condition_1 => '1' ,
Done_Condition_2 => usTlp_empty_r3 ,
Done_Condition_3 => usTlp_nReq_r1 ,
Done_Condition_4 => us_Last_sof ,
Done_Condition_5 => us_Last_eof ,
us_MWr_Param_Vec => us_MWr_Param_Vec ,
ChBuf_aFull => usTlp_Npempty_r1 , -- usTlp_prog_Full_r1 ,
ChBuf_WrEn => usTlp_we ,
ChBuf_WrDin => usTlp_din ,
State_Is_LoadParam => usState_Is_LoadParam ,
State_Is_Snout => usState_Is_Snout ,
State_Is_Body => usState_Is_Body ,
State_Is_Tail => usState_Is_Tail ,
DMA_Cmd_Ack => DMA_Cmd_Ack ,
dma_clk => trn_clk ,
dma_reset => Local_Reset_i
);
usChBuf_ValidRd <= usTlp_RE; -- usTlp_RE_i and not usTlp_empty_i;
-- -------------------------------------------------
--
DMA_us_Status <= DMA_Status_i;
--
-- Synchronous output: DMA_Status_i
--
US_DMA_Status_Concat:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DMA_Status_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
DMA_Status_i <= (
CINT_BIT_DMA_STAT_NALIGN => usBDA_nAligned,
CINT_BIT_DMA_STAT_TIMEOUT => usDMA_TimeOut_i,
CINT_BIT_DMA_STAT_BDANULL => usDMA_BDA_eq_Null,
CINT_BIT_DMA_STAT_BUSY => usDMA_Busy_i,
CINT_BIT_DMA_STAT_DONE => usDMA_Done_i,
Others => '0'
);
end if;
end process;
-- -----------------------------------
-- Synchronous Register: usDMA_MWr_Tag
FSM_usDMA_usDMA_MWr_Tag:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
usDMA_MWr_Tag <= C_TAG0_DMA_US_MWR;
elsif trn_clk'event and trn_clk = '1' then
if usState_Is_Snout='1'
or usState_Is_Body='1'
or usState_Is_Tail='1'
then
-- Only 4 lower bits increment, higher 4 stay
usDMA_MWr_Tag(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)
<= usDMA_MWr_Tag(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(1, C_TAG_WIDTH-C_TAG_DECODE_BITS);
else
usDMA_MWr_Tag <= usDMA_MWr_Tag;
end if;
end if;
end process;
-- -------------------------------------------------
-- us MWr/MRd TLP Buffer
-- -------------------------------------------------
US_TLP_Buffer:
k7_sfifo_15x128
port map (
clk => trn_clk,
rst => Local_Reset_i,
prog_full => usTlp_prog_Full ,
-- wr_clk => trn_clk,
wr_en => usTlp_we,
din => usTlp_din,
full => usTlp_full,
-- rd_clk => trn_clk,
rd_en => usTlp_RE_i,
dout => usTlp_Qout_wire,
prog_empty => usTlp_pempty,
empty => usTlp_empty_i
);
-- ---------------------------------------------
-- Synchronous delay
--
Synch_Delay_ren_Qout:
process (Local_Reset_i, trn_clk )
begin
if Local_Reset_i = '1' then
FIFO_Reading_r1 <= '0';
FIFO_Reading_r2 <= '0';
FIFO_Reading_r3p<= '0';
usTlp_RE_i_r1 <= '0';
usTlp_nReq_r1 <= '0';
usTlp_Qout_reg <= (OTHERS=>'0');
usTlp_MWr_Leng <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
FIFO_Reading_r1 <= FIFO_Reading;
FIFO_Reading_r2 <= FIFO_Reading_r1;
FIFO_Reading_r3p<= FIFO_Reading_r1 or FIFO_Reading_r2;
usTlp_RE_i_r1 <= usTlp_RE_i;
usTlp_nReq_r1 <= not usTlp_Req_i;
if usTlp_RE_i_r1='1' then
usTlp_Qout_reg <= usTlp_Qout_wire;
usTlp_MWr_Leng <= usTlp_Qout_wire(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
else
usTlp_Qout_reg <= usTlp_Qout_reg;
usTlp_MWr_Leng <= usTlp_MWr_Leng;
end if;
end if;
end process;
-- ---------------------------------------------
-- Request for arbitration
--
Synch_Req_Proc:
process (Local_Reset_i, trn_clk )
begin
if Local_Reset_i = '1' then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
elsif trn_clk'event and trn_clk = '1' then
case FSM_REQ_us is
when REQST_IDLE =>
if usTlp_empty_i = '0' then
usTlp_RE_i <= '1';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_1Read;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
end if;
when REQST_1Read =>
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Decision;
when REQST_Decision =>
if usTlp_Qout_wire(C_CHBUF_FMT_BIT_TOP) = '1' -- Has Payload
and usTlp_Qout_wire(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT)
=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_nFIFO_Req;
end if;
when REQST_nFIFO_Req =>
if usTlp_RE = '1' then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_nFIFO_Req;
end if;
when REQST_Quantity =>
if usTlp_RE = '1' then
usTlp_RE_i <= '1';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
elsif FIFO_Data_Count(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)=C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)
and FIFO_Data_Count(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) < usTlp_MWr_Leng(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_FIFO_Req;
end if;
when REQST_FIFO_Req =>
if FIFO_Data_Count(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)=C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)
and FIFO_Data_Count(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) < usTlp_MWr_Leng(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
elsif usTlp_RE = '1' then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_FIFO_Req;
end if;
when OTHERS =>
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
end case;
end if;
end process;
-- ---------------------------------------------
-- Sending usTlp_Qout
--
Synch_usTlp_Qout:
process (Local_Reset_i, trn_clk )
begin
if Local_Reset_i = '1' then
usTlp_Qout_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if usTlp_RE = '1' then
usTlp_Qout_i <= usTlp_Qout_reg;
else
usTlp_Qout_i <= usTlp_Qout_i;
end if;
end if;
end process;
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
usTlp_Npempty_r1 <= not usTlp_pempty;
usTlp_Nempty_r1 <= not usTlp_empty_i;
usTlp_empty_r1 <= usTlp_empty_i;
usTlp_empty_r2 <= usTlp_empty_r1;
usTlp_empty_r3 <= usTlp_empty_r2;
usTlp_empty_r4 <= usTlp_empty_r3;
usTlp_prog_Full_r1 <= usTlp_prog_Full;
-- usTlp_Req_i <= not usTlp_empty_i
-- and not usDMA_Stop
-- and not usDMA_Stop2
-- and not us_FC_stop
-- ;
end if;
end process;
end architecture Behavioral;
|
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 01:28:25 03/22/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: show_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity show_controller is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
up : in std_logic;
down : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
--get_data : in std_logic;
fifo_wr : out std_logic;
rf_addr : out std_logic_vector(addr_width - 1 downto 0);
show_dout : out std_logic_vector(7 downto 0);
data_count : out std_logic_vector(5 downto 0);
show_data : out std_logic
);
end show_controller;
architecture Behavioral of show_controller is
type t_state is (init, idle, take_data, send_data);
signal state, state_next : t_state;
signal reg_cnt, reg_cnt_next : integer range 0 to 31;
signal data_cnt, data_cnt_next : integer range 0 to 10;
signal delay, delay_next : integer range 0 to 200000000;
signal dout, dout_next : std_logic_vector(7 downto 0);
signal addr, addr_next : std_logic_vector(4 downto 0);
signal show, show_next : std_logic;
signal wr_en, wr_en_next : std_logic;
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= init;
reg_cnt <= 0;
delay <= 1;
data_cnt <= 0;
dout <= (others => '0');
addr <= (others => '0');
show <= '0';
wr_en <= '0';
else
state <= state_next;
reg_cnt <= reg_cnt_next;
delay <= delay_next;
data_cnt <= data_cnt_next;
dout <= dout_next;
addr <= addr_next;
show <= show_next;
wr_en <= wr_en_next;
end if;
end if;
end process;
routing : process (state, delay, reg_cnt, data_cnt, dout, rf_data, addr, show, up, down, wr_en)
begin
state_next <= state;
reg_cnt_next <= reg_cnt;
delay_next <= delay;
data_cnt_next <= data_cnt;
dout_next <= dout;
addr_next <= addr;
show_next <= show;
wr_en_next <= wr_en;
case state is
when init =>
if delay = 200000000 then
state_next <= take_data;
delay_next <= 0;
else
delay_next <= delay + 1;
end if;
when take_data =>
if delay = 150000 then
delay_next <= 0;
state_next <= send_data;
--show_next <= '1';
elsif delay = 0 then
addr_next <= std_logic_vector(to_unsigned(reg_cnt, addr_width));
delay_next <= delay + 1;
else
delay_next <= delay + 1;
end if;
when send_data =>
--show_next <= '0';
case data_cnt is
when 0 =>
dout_next <= "01010010";
wr_en_next <= '1';
data_cnt_next <= 1;
when 1 =>
dout_next <= "01000101";
wr_en_next <= '1';
data_cnt_next <= 2;
when 2 =>
dout_next <= "01000111";
wr_en_next <= '1';
data_cnt_next <= 3;
when 3 =>
case reg_cnt is
when 0|1|2|3|4|5|6|7|8|9 =>
dout_next <= "00110000";
when 10|11|12|13|14|15|16|17|18|19 =>
dout_next <= "00110001";
when 20|21|22|23|24|25|26|27|28|29 =>
dout_next <= "00110010";
when 30|31 =>
dout_next <= "00110011";
end case;
wr_en_next <= '1';
data_cnt_next <= 4;
when 4 =>
case reg_cnt is
when 0|10|20|30 =>
dout_next <= "00110000";
when 1|11|21|31 =>
dout_next <= "00110001";
when 2|12|22 =>
dout_next <= "00110010";
when 3|13|23 =>
dout_next <= "00110011";
when 4|14|24 =>
dout_next <= "00110100";
when 5|15|25 =>
dout_next <= "00110101";
when 6|16|26 =>
dout_next <= "00110110";
when 7|17|27 =>
dout_next <= "00110111";
when 8|18|28 =>
dout_next <= "00111000";
when 9|19|29 =>
dout_next <= "00111001";
end case;
wr_en_next <= '1';
data_cnt_next <= 5;
when 5 =>
dout_next <= "00111010";
wr_en_next <= '1';
data_cnt_next <= 6;
when 6 =>
--if get_data = '1' then
case rf_data(15 downto 12) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
wr_en_next <= '1';
data_cnt_next <= 7;
--end if;
when 7 =>
--if get_data = '1' then
case rf_data(11 downto 8) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
data_cnt_next <= 8;
wr_en_next <= '1';
--end if;
when 8 =>
--if get_data = '1' then
case rf_data(7 downto 4) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
wr_en_next <= '1';
data_cnt_next <= 9;
--end if;
when 9 =>
--if get_data = '1' then
case rf_data(3 downto 0) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
wr_en_next <= '1';
data_cnt_next <= 10;
when 10 =>
--wr_en_next <= '1';
data_cnt_next <= 0;
state_next <= idle;
show_next <= '1';
--end if;
end case;
when idle =>
show_next <= '0';
wr_en_next <= '0';
if up = '1' then
state_next <= take_data;
if reg_cnt = 31 then
reg_cnt_next <= 0;
else
reg_cnt_next <= reg_cnt + 1;
end if;
elsif down = '1' then
state_next <= take_data;
if reg_cnt = 0 then
reg_cnt_next <= 31;
else
reg_cnt_next <= reg_cnt - 1;
end if;
end if;
end case;
end process;
show_data <= show;
show_dout <= dout;
rf_addr <= addr;
data_count <= "001010";
fifo_wr <= wr_en;
end Behavioral;
|
architecture RTL of FIFO is
procedure proc1 is begin end procedure proc1;
PROCEDURE PROC1 IS BEGIN end PROCEDURE PROC1;
function func1 return integer is begin End function func1;
begin
end architecture RTL;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont255_V4.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity cont255_V4 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
set_zero: in std_logic;
start: in STD_LOGIC;
fin : out STD_LOGIC
);
end cont255_V4;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of cont255_V4 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal reg_cuenta: std_logic_vector(7 downto 0);
signal reg_cuenta_in: std_logic_vector(7 downto 0);
signal lim_cuenta: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT incrementadorCuenta8bits
PORT(
num_in : IN std_logic_vector(7 downto 0);
num_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
fin <= lim_cuenta;
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
incr_0: incrementadorCuenta8bits PORT MAP(
num_in => reg_cuenta,
num_out => reg_cuenta_in
--fin => disconnected
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_cuenta: process(rst, clk, start)
begin
if rst = '1' then
reg_cuenta <= (others => '0');
lim_cuenta <= '0';
elsif rising_edge(clk) then
if set_zero = '1' then
reg_cuenta <= (others => '0');
lim_cuenta <= '0';
elsif reg_cuenta = "10001010" then
lim_cuenta <= '1';
reg_cuenta <= reg_cuenta;
elsif start = '1' then --!!!
lim_cuenta <= '0';
reg_cuenta <= reg_cuenta_in; -- cuenta++
else
lim_cuenta <= lim_cuenta;
reg_cuenta <= reg_cuenta;
end if;
end if;
end process p_cuenta;
end rtl;
|
------------------------------------------------------------------------------
-- Testbench for fifoctrl.vhd
--
-- Project :
-- File : tb_fifoctrl.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/17
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_FifoCtrl is
end tb_FifoCtrl;
architecture arch of tb_FifoCtrl is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, ifwrite, ifread, engwrite, engread,
bothwrite, bothread);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- FIFO signals
signal RunningxSI : std_logic;
signal EngInPortxEI : std_logic;
signal EngOutPortxEI : std_logic;
signal DecFifoWExEI : std_logic;
signal DecFifoRExEI : std_logic;
signal FifoMuxSO : std_logic;
signal FifoWExEO : std_logic;
signal FifoRExEO : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : FifoCtrl
port map (
RunningxSI => RunningxSI,
EngInPortxEI => EngInPortxEI,
EngOutPortxEI => EngOutPortxEI,
DecFifoWExEI => DecFifoWExEI,
DecFifoRExEI => DecFifoRExEI,
FifoMuxSO => FifoMuxSO,
FifoWExEO => FifoWExEO,
FifoRExEO => FifoRExEO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal RunningxSI : out std_logic;
signal EngInPortxEI : out std_logic;
signal EngOutPortxEI : out std_logic;
signal DecFifoWExEI : out std_logic;
signal DecFifoRExEI : out std_logic) is
begin
RunningxSI <= '0';
EngInPortxEI <= '0';
EngOutPortxEI <= '0';
DecFifoWExEI <= '0';
DecFifoRExEI <= '0';
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= ifwrite; -- interface write
DecFifoWExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= ifread; -- interface read
DecFifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= engwrite; -- engine write
EngOutPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= engread; -- engine read
EngInPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= bothwrite; -- interface AND engine write
DecFifoWExEI <= '1'; -- (should be prevented...)
EngOutPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= bothread; -- interface AND engine read
DecFifoRExEI <= '1'; -- (should be prevented...)
EngInPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : wbmon64.vhd
-- Author : Michael Ernst
-- Email :
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 21/09/04
---------------------------------------------------------------
-- Simulator : Modelsim Altera 5.8g
-- Synthesis : --
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Version| Author | Mod. Date | Changes Made:
-- v0.1 | Ernst | 21/09/04 | first code
--
-- $Revision: 1.5 $
--
-- $Log: wbmon64.vhd,v $
-- Revision 1.5 2015/06/15 16:40:06 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from wishbone monitor
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.4 2010/03/01 09:28:36 SKrieger
-- R: Evaluation of master outputs / slave inputs should be done when stb and cyc are both different from '0'.
-- M: Changed accordingly
--
-- Revision 1.3 2009/09/30 07:14:35 mmiehling
-- added cti=011 support
--
-- Revision 1.2 2008/12/08 09:30:30 mmiehling
-- added unaligned read burst support
--
-- Revision 1.1 2008/10/08 17:25:49 mmiehling
-- Initial Revision
--
-- Revision 1.1 2008/09/16 09:33:52 mmiehling
-- Initial Revision
--
-- Revision 1.5 2008/07/04 11:25:09 mernst
-- - Added enable signal for simulation (use signal_force to deactivate output temporarily)
-- - Data lines are only checked while they have to be valid now
--
-- Revision 1.4 2007/11/20 11:55:46 FWombacher
-- Cosmetics: Removed obsoltete address decoding
--
-- Revision 1.3 2005/09/15 08:18:17 flenhardt
-- Fixed bug in error indication
--
-- Revision 1.2 2005/04/29 08:23:05 MMiehling
-- added reset values
--
-- Revision 1.1 2005/02/07 13:09:30 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
--
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY wbmon64 IS
GENERIC(
wbname : string := "wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(63 DOWNTO 0);
sldat_o : IN std_logic_vector(63 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(7 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(63 DOWNTO 0);
ende : string := "OK"
);
END wbmon64;
ARCHITECTURE wbmon64_arch OF wbmon64 IS
function to_string
(
constant val : in std_logic_vector
) return string is
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
begin
for i in reglen downto 1 loop
case slv(i) is
when 'U' => result_str(i) := 'U';
when 'X' => result_str(i) := 'X';
when '0' => result_str(i) := '0';
when '1' => result_str(i) := '1';
when 'Z' => result_str(i) := 'Z';
when 'W' => result_str(i) := 'W';
when 'L' => result_str(i) := 'L';
when 'H' => result_str(i) := 'H';
when '-' => result_str(i) := '-';
when others => -- an unknown std_logic value was passed
assert false
report "to_string -- unknown std_logic_vector value"
severity error;
end case;
end loop;
return result_str;
end;
FUNCTION to_hstring
(
CONSTANT val : in std_logic_vector(31 DOWNTO 0)
) RETURN string is
CONSTANT reglen : natural := 7;
VARIABLE result_str : string(1 to reglen + 1);
VARIABLE slv : std_logic_vector(31 DOWNTO 0) := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(8 - i) := '0';
WHEN "0001" => result_str(8 - i) := '1';
WHEN "0010" => result_str(8 - i) := '2';
WHEN "0011" => result_str(8 - i) := '3';
WHEN "0100" => result_str(8 - i) := '4';
WHEN "0101" => result_str(8 - i) := '5';
WHEN "0110" => result_str(8 - i) := '6';
WHEN "0111" => result_str(8 - i) := '7';
WHEN "1000" => result_str(8 - i) := '8';
WHEN "1001" => result_str(8 - i) := '9';
WHEN "1010" => result_str(8 - i) := 'a';
WHEN "1011" => result_str(8 - i) := 'b';
WHEN "1100" => result_str(8 - i) := 'c';
WHEN "1101" => result_str(8 - i) := 'd';
WHEN "1110" => result_str(8 - i) := 'e';
WHEN "1111" => result_str(8 - i) := 'f';
WHEN others => result_str(8 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION to_hstring64
(
CONSTANT val : in std_logic_vector(63 DOWNTO 0)
) RETURN string is
VARIABLE temp : string (1 TO 16);
BEGIN
temp := to_hstring(val(63 DOWNTO 32))&to_hstring(val(31 DOWNTO 0));
RETURN temp;
END;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(63 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" DATA: "));
IF sel(7) = '1' THEN
hwrite(wl,data(63 DOWNTO 56));
END IF;
IF sel(6) = '1' THEN
hwrite(wl,data(55 DOWNTO 48));
END IF;
IF sel(5) = '1' THEN
hwrite(wl,data(47 DOWNTO 40));
END IF;
IF sel(4) = '1' THEN
hwrite(wl,data(39 DOWNTO 32));
END IF;
IF sel(3) = '1' THEN
hwrite(wl,data(31 DOWNTO 24));
END IF;
IF sel(2) = '1' THEN
hwrite(wl,data(23 DOWNTO 16));
END IF;
IF sel(1) = '1' THEN
hwrite(wl,data(15 DOWNTO 8));
END IF;
IF sel(0) = '1' THEN
hwrite(wl,data(7 DOWNTO 0));
END IF;
write(wl,string'(" SEL: "));
hwrite(wl, sel);
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" DATA: "));
IF sel(7) = '1' THEN
hwrite(wl,data(63 DOWNTO 56));
END IF;
IF sel(6) = '1' THEN
hwrite(wl,data(55 DOWNTO 48));
END IF;
IF sel(5) = '1' THEN
hwrite(wl,data(47 DOWNTO 40));
END IF;
IF sel(4) = '1' THEN
hwrite(wl,data(39 DOWNTO 32));
END IF;
IF sel(3) = '1' THEN
hwrite(wl,data(31 DOWNTO 24));
END IF;
IF sel(2) = '1' THEN
hwrite(wl,data(23 DOWNTO 16));
END IF;
IF sel(1) = '1' THEN
hwrite(wl,data(15 DOWNTO 8));
END IF;
IF sel(0) = '1' THEN
hwrite(wl,data(7 DOWNTO 0));
END IF;
write(wl,string'(" SEL: "));
hwrite(wl, sel);
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(63 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (7 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(63 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 8;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "011") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' AND adr(4 DOWNTO 3) = "11" THEN
adr_s <= adr - 24;
ELSIF ack = '1' THEN
adr_s <= adr + 8;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" AND cti /= "011" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
IF (cti /= "010" AND cti /= "011" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,
"Master Data Out changed during burst cycle (0x"&to_hstring64(sldat_i)&" sb 0x"&to_hstring64(sldat_i_b)&")",
x"02",
enable ,
ERROR,
sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1' AND (cti = "011" OR cti_b = "011") AND adr_s(4 DOWNTO 3) = "11") THEN
-- Addrress Increment on acknowledge for unaligned burst
adr_s <= adr_s - 24;
new_b <= '1';
wb_state <= BURST;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 8;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(adr)&" sb 0x"&to_hstring(adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(adr)&" sb 0x"&to_hstring(adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring64(sldat_i)&" sb 0x"&to_hstring64(sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END wbmon64_arch; |
--------------------------------------------------------------------------------
--
-- Title : cl_select_text.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Text selector
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0); -- X line: 0:79
y_char : in std_logic_vector(4 downto 0); -- Y line: 0:29
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0) -- selected data
);
end cl_select_text;
architecture cl_select_text of cl_select_text is
signal x_int : integer range 0 to 79 :=0;
signal y_int : integer range 0 to 29 :=0;
signal addr : integer range 0 to 31 :=0;
begin
x_int <= to_integer(unsigned(x_char));
y_int <= to_integer(unsigned(y_char));
addr <= to_integer(unsigned(addr_rnd));
process(y_int, x_int, addr, win, lose, game, cntgames) is
begin
if y_int = 5 then
case x_int is
when 16 => ch_data <= x"54"; -- T
when 17 => ch_data <= x"68"; -- h
when 18 => ch_data <= x"65"; -- e
when 19 => ch_data <= x"00"; --
when 20 => ch_data <= x"4D"; -- M
when 21 => ch_data <= x"69"; -- i
when 22 => ch_data <= x"6E"; -- n
when 23 => ch_data <= x"65"; -- e
when 24 => ch_data <= x"73"; -- s
when 25 => ch_data <= x"77"; -- w
when 26 => ch_data <= x"65"; -- e
when 27 => ch_data <= x"65"; -- e
when 28 => ch_data <= x"70"; -- p
when 29 => ch_data <= x"65"; -- e
when 30 => ch_data <= x"72"; -- r
when 31 => ch_data <= x"00"; --
when 32 => ch_data <= x"67"; -- g
when 33 => ch_data <= x"61"; -- a
when 34 => ch_data <= x"6D"; -- m
when 35 => ch_data <= x"65"; -- e
when 36 => ch_data <= x"00"; --
when 37 => ch_data <= x"6F"; -- o
when 38 => ch_data <= x"6E"; -- n
when 39 => ch_data <= x"00"; --
when 40 => ch_data <= x"46"; -- F
when 41 => ch_data <= x"50"; -- P
when 42 => ch_data <= x"47"; -- G
when 43 => ch_data <= x"41"; -- A
when 44 => ch_data <= x"00"; --
when 45 => ch_data <= x"58"; -- X
when 46 => ch_data <= x"43"; -- C
when 47 => ch_data <= x"33"; -- 3
when 48 => ch_data <= x"35"; -- 5
when 49 => ch_data <= x"30"; -- 0
when 50 => ch_data <= x"30"; -- 0
when 51 => ch_data <= x"45"; -- E
when others => ch_data <= x"00";
end case;
elsif y_int = 6 then
case x_int is
when 32 => ch_data <= x"62"; -- b
when 33 => ch_data <= x"79"; -- y
when 34 => ch_data <= x"00"; --
when 35 => ch_data <= x"4B"; -- K
when 36 => ch_data <= x"61"; -- a
when 37 => ch_data <= x"70"; -- p
when 38 => ch_data <= x"69"; -- i
when 39 => ch_data <= x"74"; -- t
when 40 => ch_data <= x"61"; -- a
when 41 => ch_data <= x"6E"; -- n
when 42 => ch_data <= x"6F"; -- o
when 43 => ch_data <= x"76"; -- v
when 44 => ch_data <= x"00"; --
when 45 => ch_data <= x"41"; -- A
when 46 => ch_data <= x"6C"; -- l
when 47 => ch_data <= x"65"; -- e
when 48 => ch_data <= x"78"; -- x
when 49 => ch_data <= x"61"; -- a
when 50 => ch_data <= x"6E"; -- n
when 51 => ch_data <= x"64"; -- d
when 52 => ch_data <= x"65"; -- e
when 53 => ch_data <= x"72"; -- r
when 54 => ch_data <= x"00"; --
when 55 => ch_data <= x"2A"; -- $
when others => ch_data <= x"00";
end case;
elsif y_int = 7 then
case x_int is
when 16 => ch_data <= x"52"; -- R
when 17 => ch_data <= x"75"; -- u
when 18 => ch_data <= x"6C"; -- l
when 19 => ch_data <= x"65"; -- e
when 20 => ch_data <= x"73"; -- s
when 21 => ch_data <= x"3A"; -- :
when others => ch_data <= x"00";
end case;
elsif y_int = 8 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"53"; -- S
when 20 => ch_data <= x"50"; -- P
when 21 => ch_data <= x"41"; -- A
when 22 => ch_data <= x"43"; -- C
when 23 => ch_data <= x"45"; -- E
when 24 => ch_data <= x"00"; --
when 25 => ch_data <= x"2D"; -- -
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"73"; -- s
when 28 => ch_data <= x"74"; -- t
when 29 => ch_data <= x"61"; -- a
when 30 => ch_data <= x"72"; -- r
when 31 => ch_data <= x"74"; -- t
when 32 => ch_data <= x"00"; --
when 33 => ch_data <= x"6e"; -- n
when 34 => ch_data <= x"65"; -- e
when 35 => ch_data <= x"77"; -- w
when 36 => ch_data <= x"00"; --
when 37 => ch_data <= x"67"; -- g
when 38 => ch_data <= x"61"; -- a
when 39 => ch_data <= x"6D"; -- m
when 40 => ch_data <= x"65"; -- e
when 41 => ch_data <= x"2C"; -- ,
when others => ch_data <= x"00";
end case;
elsif y_int = 9 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"45"; -- E
when 20 => ch_data <= x"4E"; -- N
when 21 => ch_data <= x"54"; -- T
when 22 => ch_data <= x"45"; -- E
when 23 => ch_data <= x"52"; -- R
when 24 => ch_data <= x"00"; --
when 25 => ch_data <= x"2D"; -- -
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"63"; -- c
when 28 => ch_data <= x"68"; -- h
when 29 => ch_data <= x"65"; -- e
when 30 => ch_data <= x"63"; -- c
when 31 => ch_data <= x"6B"; -- k
when 32 => ch_data <= x"00"; --
when 33 => ch_data <= x"61"; -- a
when 34 => ch_data <= x"00"; --
when 35 => ch_data <= x"66"; -- f
when 36 => ch_data <= x"69"; -- i
when 37 => ch_data <= x"65"; -- e
when 38 => ch_data <= x"6C"; -- l
when 39 => ch_data <= x"64"; -- d
when 40 => ch_data <= x"2C"; -- ,
when others => ch_data <= x"00";
end case;
elsif y_int = 10 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"27"; -- "
when 20 => ch_data <= x"57"; -- W
when 21 => ch_data <= x"53"; -- S
when 22 => ch_data <= x"41"; -- A
when 23 => ch_data <= x"44"; -- D
when 24 => ch_data <= x"27"; -- "
-- when 25 => ch_data <= x"00"; --
when 25 => ch_data <= x"2D"; -- -
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"6B"; -- k
when 28 => ch_data <= x"65"; -- e
when 29 => ch_data <= x"79"; -- y
when 30 => ch_data <= x"73"; -- s
when 31 => ch_data <= x"00"; --
when 32 => ch_data <= x"66"; -- f
when 33 => ch_data <= x"6F"; -- o
when 34 => ch_data <= x"72"; -- r
when 35 => ch_data <= x"00"; --
when 36 => ch_data <= x"6D"; -- m
when 37 => ch_data <= x"6F"; -- o
when 38 => ch_data <= x"76"; -- v
when 39 => ch_data <= x"69"; -- i
when 40 => ch_data <= x"6E"; -- n
when 41 => ch_data <= x"67"; -- g
when 42 => ch_data <= x"2C"; -- ,
when others => ch_data <= x"00";
end case;
elsif y_int = 11 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"45"; -- E
when 20 => ch_data <= x"53"; -- S
when 21 => ch_data <= x"43"; -- C
when 22 => ch_data <= x"00"; --
when 23 => ch_data <= x"2D"; -- -
when 24 => ch_data <= x"00"; --
when 25 => ch_data <= x"65"; -- e
when 26 => ch_data <= x"78"; -- x
when 27 => ch_data <= x"69"; -- i
when 28 => ch_data <= x"74"; -- t
when 29 => ch_data <= x"2C"; -- .
when others => ch_data <= x"00";
end case;
elsif y_int = 12 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"38"; -- 8
when 20 => ch_data <= x"00"; --
when 21 => ch_data <= x"6D"; -- m
when 22 => ch_data <= x"69"; -- i
when 23 => ch_data <= x"6E"; -- n
when 24 => ch_data <= x"65"; -- e
when 25 => ch_data <= x"73"; -- s
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"6F"; -- o
when 28 => ch_data <= x"6E"; -- n
when 29 => ch_data <= x"6C"; -- l
when 30 => ch_data <= x"79"; -- y
when 31 => ch_data <= x"2E"; -- .
when others => ch_data <= x"00";
end case;
elsif y_int = 14 then
case x_int is
when 16 => ch_data <= x"47"; -- G
when 17 => ch_data <= x"41"; -- A
when 18 => ch_data <= x"4D"; -- M
when 19 => ch_data <= x"45"; -- E
when 20 => ch_data <= x"00"; --
when 21 =>
if cntgames = '1' then
if (addr < 10) then
ch_data <= x"30";
elsif ((10 <= addr) and (addr < 20)) then
ch_data <= x"31";
elsif ((20 <= addr) and (addr < 30)) then
ch_data <= x"32";
else
ch_data <= x"33";
end if;
else
ch_data <= x"05";
end if;
when 22 =>
if cntgames = '1' then
if ((addr = 0) or (addr = 10) or (addr = 20) or (addr = 30)) then
ch_data <= x"30";
elsif ((addr = 1) or (addr = 11) or (addr = 21) or (addr = 31)) then
ch_data <= x"31";
elsif ((addr = 2) or (addr = 12) or (addr = 22)) then
ch_data <= x"32";
elsif ((addr = 3) or (addr = 13) or (addr = 23)) then
ch_data <= x"33";
elsif ((addr = 4) or (addr = 14) or (addr = 24)) then
ch_data <= x"34";
elsif ((addr = 5) or (addr = 15) or (addr = 25)) then
ch_data <= x"35";
elsif ((addr = 6) or (addr = 16) or (addr = 26)) then
ch_data <= x"36";
elsif ((addr = 7) or (addr = 17) or (addr = 27)) then
ch_data <= x"37";
elsif ((addr = 8) or (addr = 18) or (addr = 28)) then
ch_data <= x"38";
elsif ((addr = 9) or (addr = 19) or (addr = 29)) then
ch_data <= x"39";
else
null;
end if;
else
ch_data <= x"05";
end if;
when others => ch_data <= x"00";
end case;
elsif y_int = 16 then
if lose = '1' then
case x_int is
when 26 => ch_data <= x"0F"; -- :(
when 27 => ch_data <= x"00"; --
when 28 => ch_data <= x"47"; -- G
when 29 => ch_data <= x"41"; -- A
when 30 => ch_data <= x"4D"; -- M
when 31 => ch_data <= x"45"; -- E
when 32 => ch_data <= x"00"; --
when 33 => ch_data <= x"4F"; -- O
when 34 => ch_data <= x"56"; -- V
when 35 => ch_data <= x"45"; -- E
when 36 => ch_data <= x"52"; -- R
when 37 => ch_data <= x"00"; --
when 38 => ch_data <= x"0F"; -- :(
when others => ch_data <= x"00";
end case;
elsif win = '1' then
case x_int is
when 26 => ch_data <= x"01"; -- :)
when 27 => ch_data <= x"00"; --
when 28 => ch_data <= x"59"; -- Y
when 29 => ch_data <= x"4F"; -- O
when 30 => ch_data <= x"55"; -- U
when 31 => ch_data <= x"00"; --
when 32 => ch_data <= x"57"; -- W
when 33 => ch_data <= x"49"; -- I
when 34 => ch_data <= x"4E"; -- N
when 35 => ch_data <= x"21"; -- !
when 36 => ch_data <= x"21"; -- !
when 37 => ch_data <= x"00"; --
when 38 => ch_data <= x"01"; -- :)
when others => ch_data <= x"00";
end case;
else
ch_data <= x"00";
end if;
elsif y_int = 19 then
if game = '1' then
case x_int is
when 26 => ch_data <= x"4E"; -- N
when 27 => ch_data <= x"65"; -- e
when 28 => ch_data <= x"77"; -- w
when 29 => ch_data <= x"00"; --
when 30 => ch_data <= x"67"; -- g
when 31 => ch_data <= x"61"; -- a
when 32 => ch_data <= x"6D"; -- m
when 33 => ch_data <= x"65"; -- e
when 34 => ch_data <= x"00"; --
when 35 => ch_data <= x"7b"; -- {
when 36 => ch_data <= x"59"; -- Y
when 37 => ch_data <= x"2F"; -- /
when 38 => ch_data <= x"4e"; -- N
when 39 => ch_data <= x"7d"; -- }
when 40 => ch_data <= x"3F"; -- ?
when others => ch_data <= x"00";
end case;
else
ch_data <= x"00";
end if;
else
ch_data <= x"00";
end if;
end process;
end cl_select_text; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end component;
-- Declaring NI component
component NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end component; --component NI
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
signal link_faults_0 : std_logic_vector(4 downto 0);
signal turn_faults_0 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0 : std_logic_vector(3 downto 0);
signal Reconfig_command_0 : std_logic;
signal link_faults_1 : std_logic_vector(4 downto 0);
signal turn_faults_1 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_1 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_1 : std_logic_vector(3 downto 0);
signal Reconfig_command_1 : std_logic;
signal link_faults_2 : std_logic_vector(4 downto 0);
signal turn_faults_2 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_2 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_2 : std_logic_vector(3 downto 0);
signal Reconfig_command_2 : std_logic;
signal link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_3 : std_logic;
-- NI testing signals
signal reserved_address : std_logic_vector(29 downto 0):= "000000000000000001111111111111";
signal flag_address : std_logic_vector(29 downto 0):= "000000000000000010000000000000" ; -- reserved address for the memory mapped I/O
signal counter_address : std_logic_vector(29 downto 0):= "000000000000000010000000000001";
signal reconfiguration_address : std_logic_vector(29 downto 0):= "000000000000000010000000000010"; -- reserved address for reconfiguration register
signal self_diagnosis_address : std_logic_vector(29 downto 0):= "000000000000000010000000000011";
signal irq_out_0, irq_out_1, irq_out_2, irq_out_3: std_logic;
signal test_0, test_1, test_2, test_3: std_logic_vector(31 downto 0);
signal enable_0, enable_1, enable_2, enable_3: std_logic;
signal write_byte_enable_0, write_byte_enable_1, write_byte_enable_2, write_byte_enable_3: std_logic_vector(3 downto 0);
signal address_0, address_1, address_2, address_3: std_logic_vector(31 downto 2);
signal data_write_0, data_write_1, data_write_2, data_write_3: std_logic_vector(31 downto 0);
signal data_read_0, data_read_1, data_read_2, data_read_3: std_logic_vector(31 downto 0);
--------------
--------------
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
-- should be connected to NI
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
not_reset <= not reset;
-- connecting the NIs
NI_0: NI
generic map(current_address => 0
)
port map(clk => clk , reset => not_reset , enable => enable_0,
write_byte_enable => write_byte_enable_0,
address => address_0,
data_write => data_write_0,
data_read => data_read_0,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_0,
-- signals for sending packets to network
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
-- fault information signals from the router
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0
);
NI_1: NI
generic map(current_address => 1
)
port map(clk => clk , reset => not_reset , enable => enable_1,
write_byte_enable => write_byte_enable_1,
address => address_1,
data_write => data_write_1,
data_read => data_read_1,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_1,
-- signals for sending packets to network
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
-- fault information signals from the router
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1
);
NI_2: NI
generic map(current_address => 2
)
port map(clk => clk , reset => not_reset , enable => enable_2,
write_byte_enable => write_byte_enable_2,
address => address_2,
data_write => data_write_2,
data_read => data_read_2,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_2,
-- signals for sending packets to network
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
-- fault information signals from the router
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2
);
NI_3: NI
generic map(current_address => 3
)
port map(clk => clk , reset => not_reset , enable => enable_3,
write_byte_enable => write_byte_enable_3,
address => address_3,
data_write => data_write_3,
data_read => data_read_3,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_3,
-- signals for sending packets to network
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
-- fault information signals from the router
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3
);
-- connecting the packet generators
NI_control(2, 100, 0, 12, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_0, write_byte_enable_0, address_0, data_write_0, data_read_0, test_0);
NI_control(2, 100, 1, 3, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_1, write_byte_enable_1, address_1, data_write_1, data_read_1, test_1);
NI_control(2, 100, 2, 13, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_2, write_byte_enable_2, address_2, data_write_2, data_read_2, test_2);
NI_control(2, 100, 3, 14, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_3, write_byte_enable_3, address_3, data_write_3, data_read_3, test_3);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end component;
-- Declaring NI component
component NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end component; --component NI
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
signal link_faults_0 : std_logic_vector(4 downto 0);
signal turn_faults_0 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0 : std_logic_vector(3 downto 0);
signal Reconfig_command_0 : std_logic;
signal link_faults_1 : std_logic_vector(4 downto 0);
signal turn_faults_1 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_1 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_1 : std_logic_vector(3 downto 0);
signal Reconfig_command_1 : std_logic;
signal link_faults_2 : std_logic_vector(4 downto 0);
signal turn_faults_2 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_2 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_2 : std_logic_vector(3 downto 0);
signal Reconfig_command_2 : std_logic;
signal link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_3 : std_logic;
-- NI testing signals
signal reserved_address : std_logic_vector(29 downto 0):= "000000000000000001111111111111";
signal flag_address : std_logic_vector(29 downto 0):= "000000000000000010000000000000" ; -- reserved address for the memory mapped I/O
signal counter_address : std_logic_vector(29 downto 0):= "000000000000000010000000000001";
signal reconfiguration_address : std_logic_vector(29 downto 0):= "000000000000000010000000000010"; -- reserved address for reconfiguration register
signal self_diagnosis_address : std_logic_vector(29 downto 0):= "000000000000000010000000000011";
signal irq_out_0, irq_out_1, irq_out_2, irq_out_3: std_logic;
signal test_0, test_1, test_2, test_3: std_logic_vector(31 downto 0);
signal enable_0, enable_1, enable_2, enable_3: std_logic;
signal write_byte_enable_0, write_byte_enable_1, write_byte_enable_2, write_byte_enable_3: std_logic_vector(3 downto 0);
signal address_0, address_1, address_2, address_3: std_logic_vector(31 downto 2);
signal data_write_0, data_write_1, data_write_2, data_write_3: std_logic_vector(31 downto 0);
signal data_read_0, data_read_1, data_read_2, data_read_3: std_logic_vector(31 downto 0);
--------------
--------------
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
-- should be connected to NI
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
not_reset <= not reset;
-- connecting the NIs
NI_0: NI
generic map(current_address => 0
)
port map(clk => clk , reset => not_reset , enable => enable_0,
write_byte_enable => write_byte_enable_0,
address => address_0,
data_write => data_write_0,
data_read => data_read_0,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_0,
-- signals for sending packets to network
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
-- fault information signals from the router
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0
);
NI_1: NI
generic map(current_address => 1
)
port map(clk => clk , reset => not_reset , enable => enable_1,
write_byte_enable => write_byte_enable_1,
address => address_1,
data_write => data_write_1,
data_read => data_read_1,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_1,
-- signals for sending packets to network
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
-- fault information signals from the router
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1
);
NI_2: NI
generic map(current_address => 2
)
port map(clk => clk , reset => not_reset , enable => enable_2,
write_byte_enable => write_byte_enable_2,
address => address_2,
data_write => data_write_2,
data_read => data_read_2,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_2,
-- signals for sending packets to network
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
-- fault information signals from the router
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2
);
NI_3: NI
generic map(current_address => 3
)
port map(clk => clk , reset => not_reset , enable => enable_3,
write_byte_enable => write_byte_enable_3,
address => address_3,
data_write => data_write_3,
data_read => data_read_3,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_3,
-- signals for sending packets to network
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
-- fault information signals from the router
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3
);
-- connecting the packet generators
NI_control(2, 100, 0, 12, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_0, write_byte_enable_0, address_0, data_write_0, data_read_0, test_0);
NI_control(2, 100, 1, 3, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_1, write_byte_enable_1, address_1, data_write_1, data_read_1, test_1);
NI_control(2, 100, 2, 13, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_2, write_byte_enable_2, address_2, data_write_2, data_read_2, test_2);
NI_control(2, 100, 3, 14, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_3, write_byte_enable_3, address_3, data_write_3, data_read_3, test_3);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end component;
-- Declaring NI component
component NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end component; --component NI
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
signal link_faults_0 : std_logic_vector(4 downto 0);
signal turn_faults_0 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0 : std_logic_vector(3 downto 0);
signal Reconfig_command_0 : std_logic;
signal link_faults_1 : std_logic_vector(4 downto 0);
signal turn_faults_1 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_1 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_1 : std_logic_vector(3 downto 0);
signal Reconfig_command_1 : std_logic;
signal link_faults_2 : std_logic_vector(4 downto 0);
signal turn_faults_2 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_2 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_2 : std_logic_vector(3 downto 0);
signal Reconfig_command_2 : std_logic;
signal link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_3 : std_logic;
-- NI testing signals
signal reserved_address : std_logic_vector(29 downto 0):= "000000000000000001111111111111";
signal flag_address : std_logic_vector(29 downto 0):= "000000000000000010000000000000" ; -- reserved address for the memory mapped I/O
signal counter_address : std_logic_vector(29 downto 0):= "000000000000000010000000000001";
signal reconfiguration_address : std_logic_vector(29 downto 0):= "000000000000000010000000000010"; -- reserved address for reconfiguration register
signal self_diagnosis_address : std_logic_vector(29 downto 0):= "000000000000000010000000000011";
signal irq_out_0, irq_out_1, irq_out_2, irq_out_3: std_logic;
signal test_0, test_1, test_2, test_3: std_logic_vector(31 downto 0);
signal enable_0, enable_1, enable_2, enable_3: std_logic;
signal write_byte_enable_0, write_byte_enable_1, write_byte_enable_2, write_byte_enable_3: std_logic_vector(3 downto 0);
signal address_0, address_1, address_2, address_3: std_logic_vector(31 downto 2);
signal data_write_0, data_write_1, data_write_2, data_write_3: std_logic_vector(31 downto 0);
signal data_read_0, data_read_1, data_read_2, data_read_3: std_logic_vector(31 downto 0);
--------------
--------------
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
-- should be connected to NI
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
not_reset <= not reset;
-- connecting the NIs
NI_0: NI
generic map(current_address => 0
)
port map(clk => clk , reset => not_reset , enable => enable_0,
write_byte_enable => write_byte_enable_0,
address => address_0,
data_write => data_write_0,
data_read => data_read_0,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_0,
-- signals for sending packets to network
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
-- fault information signals from the router
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0
);
NI_1: NI
generic map(current_address => 1
)
port map(clk => clk , reset => not_reset , enable => enable_1,
write_byte_enable => write_byte_enable_1,
address => address_1,
data_write => data_write_1,
data_read => data_read_1,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_1,
-- signals for sending packets to network
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
-- fault information signals from the router
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1
);
NI_2: NI
generic map(current_address => 2
)
port map(clk => clk , reset => not_reset , enable => enable_2,
write_byte_enable => write_byte_enable_2,
address => address_2,
data_write => data_write_2,
data_read => data_read_2,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_2,
-- signals for sending packets to network
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
-- fault information signals from the router
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2
);
NI_3: NI
generic map(current_address => 3
)
port map(clk => clk , reset => not_reset , enable => enable_3,
write_byte_enable => write_byte_enable_3,
address => address_3,
data_write => data_write_3,
data_read => data_read_3,
-- interrupt signal: generated evertime a packet is recieved!
irq_out => irq_out_3,
-- signals for sending packets to network
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3, -- data sent to the NoC
-- signals for reciving packets from the network
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
-- fault information signals from the router
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3
);
-- connecting the packet generators
NI_control(2, 100, 0, 12, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_0, write_byte_enable_0, address_0, data_write_0, data_read_0, test_0);
NI_control(2, 100, 1, 3, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_1, write_byte_enable_1, address_1, data_write_1, data_read_1, test_1);
NI_control(2, 100, 2, 13, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_2, write_byte_enable_2, address_2, data_write_2, data_read_2, test_2);
NI_control(2, 100, 3, 14, 8, 8, 10000 ns, clk,
-- NI configuration
reserved_address, flag_address, counter_address, reconfiguration_address, self_diagnosis_address,
-- NI signals
enable_3, write_byte_enable_3, address_3, data_write_3, data_read_3, test_3);
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Fri May 6 14:51:06 2016
-- Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
-- Command : write_vhdl -force -mode synth_stub /home/guest/cae/fpga/ntpserver/ip/ocxo_clk_pll/ocxo_clk_pll_stub.vhdl
-- Design : ocxo_clk_pll
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ocxo_clk_pll is
Port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
end ocxo_clk_pll;
architecture stub of ocxo_clk_pll is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,resetn,locked";
begin
end;
|
-------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
use work.cpu_xadc_wiz_0_0_pselect_f;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
use work.cpu_xadc_wiz_0_0_family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity cpu_xadc_wiz_0_0_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of cpu_xadc_wiz_0_0_address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.cpu_xadc_wiz_0_0_pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.cpu_xadc_wiz_0_0_pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package VECTOR_FUNC is
function bit_position(s : std_logic_vector) return integer;
end VECTOR_FUNC;
package body VECTOR_FUNC is
function bit_position(s : std_logic_vector) return integer is
variable position : natural := 0;
begin
for i in s'range loop
if s(i) = '1' then
position := i;
end if;
end loop;
return position;
end function bit_position;
end VECTOR_FUNC;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_src1_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_src1_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_src1_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_src1_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_src1_rows_V is
component FIFO_image_filter_src1_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_src1_rows_V_shiftReg : FIFO_image_filter_src1_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_src1_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_src1_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_src1_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_src1_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_src1_rows_V is
component FIFO_image_filter_src1_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_src1_rows_V_shiftReg : FIFO_image_filter_src1_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc41.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00041ent IS
END c04s03b01x01p02n01i00041ent;
ARCHITECTURE c04s03b01x01p02n01i00041arch OF c04s03b01x01p02n01i00041ent IS
constant B1 : Bit := '0'; -- No_failure_here
constant B2 : Character := '0'; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( B1 = '0' and B2 = '0' )
report "***PASSED TEST: c04s03b01x01p02n01i00041"
severity NOTE;
assert ( B1 = '0' and B2 = '0' )
report "***FAILED TEST: c04s03b01x01p02n01i00041 - Same element contained in two different types assigned to both types in a constant statement test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00041arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc41.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00041ent IS
END c04s03b01x01p02n01i00041ent;
ARCHITECTURE c04s03b01x01p02n01i00041arch OF c04s03b01x01p02n01i00041ent IS
constant B1 : Bit := '0'; -- No_failure_here
constant B2 : Character := '0'; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( B1 = '0' and B2 = '0' )
report "***PASSED TEST: c04s03b01x01p02n01i00041"
severity NOTE;
assert ( B1 = '0' and B2 = '0' )
report "***FAILED TEST: c04s03b01x01p02n01i00041 - Same element contained in two different types assigned to both types in a constant statement test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00041arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc41.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00041ent IS
END c04s03b01x01p02n01i00041ent;
ARCHITECTURE c04s03b01x01p02n01i00041arch OF c04s03b01x01p02n01i00041ent IS
constant B1 : Bit := '0'; -- No_failure_here
constant B2 : Character := '0'; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( B1 = '0' and B2 = '0' )
report "***PASSED TEST: c04s03b01x01p02n01i00041"
severity NOTE;
assert ( B1 = '0' and B2 = '0' )
report "***FAILED TEST: c04s03b01x01p02n01i00041 - Same element contained in two different types assigned to both types in a constant statement test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00041arch;
|
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`protect end_protected
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
package interfaces is
-------------------------------------------------------------------------------
-- Wishbone slave
-------------------------------------------------------------------------------
----------------------------------------------
type wbs_in_type is record
----------------------------------------------
clk : std_logic;
-- standard wishbone signals
rst : std_logic;
dat : std_logic_vector(WB_DW-1 downto 0);
adr : std_logic_vector(WB_REG_AW-1 downto 0);
stb : std_logic;
cyc : std_logic;
we : std_logic;
end record;
----------------------------------------------
type wbs_out_type is record
----------------------------------------------
-- standard wishbone signals
dat : std_logic_vector(WB_DW-1 downto 0);
ack : std_logic;
-- interrupt request
irq : std_logic;
end record;
-------------------------------------------------------------------------------
-- Wishbone Master (part of frame controller)
-------------------------------------------------------------------------------
----------------------------------------------
type wbm_in_type is record
----------------------------------------------
clk : std_logic;
dat : std_logic_vector(WB_DW-1 downto 0);
ack : std_logic;
-- interrupt related:
girq : std_logic;
int_adr : std_logic_vector(WB_CORE_AW-1 downto 0);
end record;
----------------------------------------------
type wbm_out_type is record
----------------------------------------------
dat : std_logic_vector(WB_DW-1 downto 0);
adr : std_logic_vector(WB_AW-1 downto 0);
stb : std_logic;
we : std_logic;
cyc : std_logic;
end record;
-------------------------------------------------------------------------------
-- Frame controller
-------------------------------------------------------------------------------
----------------------------------------------
type frame_ctrl_in_type is record
----------------------------------------------
recbuf_complete : std_logic;
recbuf_frame : std_logic_vector((PROTO_WC_RX_MAX*FIFO_WIDTH)-1 downto 0);
trabuf_busy : std_logic;
end record;
----------------------------------------------
type frame_ctrl_out_type is record
----------------------------------------------
recbuf_clear : std_logic;
trabuf_frame : std_logic_vector((PROTO_WC_TX_MAX*FIFO_WIDTH)-1 downto 0);
trabuf_valid : std_logic;
mcu_select : std_logic;
transmitter_mode : std_logic;
trabuf_length : integer range 0 to PROTO_WC_TX_MAX;
end record;
----------------------------------------------
component frame_ctrl
----------------------------------------------
port (
clk : in std_logic;
rst : in std_logic;
d : in frame_ctrl_in_type;
q : out frame_ctrl_out_type;
wbi : in wbm_in_type;
wbo : out wbm_out_type
);
end component;
end package;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1406.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01406ent IS
END c08s05b00x00p07n01i01406ent;
ARCHITECTURE c08s05b00x00p07n01i01406arch OF c08s05b00x00p07n01i01406ent IS
BEGIN
TESTING: PROCESS
type arr is array (1 to 3) of integer;
variable p : arr;
BEGIN
p := (1=>3, 2=>2.3, 3=>3);
assert FALSE
report "***FAILED TEST: c08s05b00x00p07n01i01406 - Type of the subelement does not match the type of the aggregate element."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01406arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1406.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01406ent IS
END c08s05b00x00p07n01i01406ent;
ARCHITECTURE c08s05b00x00p07n01i01406arch OF c08s05b00x00p07n01i01406ent IS
BEGIN
TESTING: PROCESS
type arr is array (1 to 3) of integer;
variable p : arr;
BEGIN
p := (1=>3, 2=>2.3, 3=>3);
assert FALSE
report "***FAILED TEST: c08s05b00x00p07n01i01406 - Type of the subelement does not match the type of the aggregate element."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01406arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1406.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p07n01i01406ent IS
END c08s05b00x00p07n01i01406ent;
ARCHITECTURE c08s05b00x00p07n01i01406arch OF c08s05b00x00p07n01i01406ent IS
BEGIN
TESTING: PROCESS
type arr is array (1 to 3) of integer;
variable p : arr;
BEGIN
p := (1=>3, 2=>2.3, 3=>3);
assert FALSE
report "***FAILED TEST: c08s05b00x00p07n01i01406 - Type of the subelement does not match the type of the aggregate element."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p07n01i01406arch;
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/06/2017 10:33:06 AM
-- Module Name: decode - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Decode Unit
-- Determines the intruction type
-- Parses out all possible fields (whether or not they are relevant)
-- May sign extend and prepare a full immediate address, I'm not sure if
-- this is the right place to do this yet. For now, just pulls the 12 or 20 bit
-- raw immediate value based on instruction type. See config.vhd for typedefs and constants
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity decoder is
Port(
instr : in std_logic_vector(31 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20);
sext_imm12 : out std_logic_vector(63 downto 0);
sext_imm20 : out std_logic_vector(63 downto 0);
reg_A : out integer;
reg_B : out integer;
reg_C : out integer;
reg_D : out integer
);
end decoder;
architecture Behavioral of decoder is
signal s_imm12 : std_logic_vector(11 downto 0);
signal s_imm20 : std_logic_vector(19 downto 0);
signal s_instr_t: instr_t;
signal s_shamt: std_logic_vector(4 downto 0);
signal s_csr: std_logic_vector(11 downto 0);
signal s_rs1 : reg_t;
signal s_rs2 : reg_t;
signal s_rs3 : reg_t;
signal s_rd : reg_t;
begin
-- Update instruction type whenever it changes
process(instr)
begin
s_imm12 <= (others => '0');
s_imm20 <= (others => '0');
s_instr_t<= (others => '1');
s_shamt <= (others => '0');
s_csr <= (others => '0');
case instr(6 downto 0) is
when LUI_T => ----
s_instr_t <= instr_LUI;
s_imm20 <= instr(31 downto 12);
when AUIPC_T =>
s_instr_t <= instr_AUIPC;
s_imm20 <= instr(31 downto 12);
when JAL_T =>
s_instr_t <= instr_JAL;
s_imm20 <= instr(31) & instr(19 downto 12) & instr(20) & instr(30 downto 21);
when JALR_T =>
s_instr_t <= instr_JALR;
s_imm12 <= instr(31 downto 20);
when BRANCH_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_BEQ;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "001" =>
s_instr_t <= instr_BNE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "100" =>
s_instr_t <= instr_BLT;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "101" =>
s_instr_t <= instr_BGE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "110" =>
s_instr_t <= instr_BLTU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "111" =>
s_instr_t <= instr_BGEU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when others => -- error state
end case;
when LOAD_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_LB;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_LH;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_LW;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_LBU;
s_imm12 <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_LHU;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_LWU;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_LD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when STORE_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_SB;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "001" =>
s_instr_t <= instr_SH;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "010" =>
s_instr_t <= instr_SW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_SD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => -- error state
end case;
when ALUI_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDI;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_SLTI;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_SLTIU;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_XORI;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_ORI;
s_imm12 <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_ANDI;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLI;
s_shamt <= instr(24 downto 20);
when "101" =>
if (instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAI;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLI;
s_shamt <= instr(24 downto 20);
end if;
when others => -- error state
end case;
when ALU_T =>
if(instr(31 downto 25)="0000001") then
-- Case RV32M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MUL;
when "001" => s_instr_t <= instr_MULH;
when "010" => s_instr_t <= instr_MULHSU;
when "011" => s_instr_t <= instr_MULHU;
when "100" => s_instr_t <= instr_DIV;
when "101" => s_instr_t <= instr_DIVU;
when "110" => s_instr_t <= instr_REM;
when "111" => s_instr_t <= instr_REMU;
when others => -- error state
end case;
else
-- Case RV32I
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUB;
else
s_instr_t <= instr_ADD;
end if;
when "001" =>
s_instr_t <= instr_SLL;
when "010" =>
s_instr_t <= instr_SLT;
when "011" =>
s_instr_t <= instr_SLTU;
when "100" =>
s_instr_t <= instr_XOR;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRA;
else
s_instr_t <= instr_SRL;
end if;
when "110" =>
s_instr_t <= instr_OR;
when "111" =>
s_instr_t <= instr_AND;
when others => -- error state
end case;
end if;
when FENCE_T =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FENCE;
else
s_instr_t <= instr_FENCEI;
end if;
when CSR_T =>
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 20) = "000000000000") then
s_instr_t <= instr_EBREAK;
elsif(instr(31 downto 20) = "000000000001") then
s_instr_t <= instr_ECALL;
elsif(instr(31 downto 20) = "000000000010") then
s_instr_t <= instr_URET;
elsif(instr(31 downto 20) = "000100000010") then
s_instr_t <= instr_SRET;
elsif(instr(31 downto 20) = "001100000010") then
s_instr_t <= instr_MRET;
elsif(instr(31 downto 20) = "000100000101") then
s_instr_t <= instr_WFI;
elsif(instr(31 downto 25) = "0001001") then
s_instr_t <= instr_SFENCEVM;
else
end if;
when "001" =>
s_instr_t <= instr_CSRRW;
s_csr <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_CSRRS;
s_csr <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_CSRRC;
s_csr <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_CSRRWI;
s_csr <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_CSRRSI;
s_csr <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_CSRRCI;
s_csr <= instr(31 downto 20);
when others => -- error state
end case;
when ALUW_T =>
if(instr(31 downto 25) = "0000001") then
-- Case RV64M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MULW;
when "100" => s_instr_t <= instr_DIVW;
when "101" => s_instr_t <= instr_DIVUW;
when "110" => s_instr_t <= instr_REMW;
when "111" => s_instr_t <= instr_REMUW;
when others => --error state
end case;
else
-- Case 64I ALU
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUBW;
else
s_instr_t <= instr_ADDW;
end if;
when "001" =>
s_instr_t <= instr_SLLW;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAW;
else
s_instr_t <= instr_SRLW;
end if;
when others => -- error state
end case;
end if;
when ALUIW_T =>
-- case RV64I
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDIW;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLIW;
s_shamt <= instr(24 downto 20);
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAIW;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLIW;
s_shamt <= instr(24 downto 20);
end if;
when others => --error state
end case;
when ATOM_T =>
if(instr(14 downto 12)="011") then
-- case RV64A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRD;
when "00011" => s_instr_t <= instr_SCD;
when "00001" => s_instr_t <= instr_AMOSWAPD;
when "00000" => s_instr_t <= instr_AMOADDD;
when "00100" => s_instr_t <= instr_AMOXORD;
when "01100" => s_instr_t <= instr_AMOANDD;
when "01000" => s_instr_t <= instr_AMOORD;
when "10000" => s_instr_t <= instr_AMOMIND;
when "10100" => s_instr_t <= instr_AMOMAXD;
when "11000" => s_instr_t <= instr_AMOMINUD;
when "11100" => s_instr_t <= instr_AMOMAXUD;
when others => --error state
end case;
else
-- case RV32A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRW;
when "00011" => s_instr_t <= instr_SCW;
when "00001" => s_instr_t <= instr_AMOSWAPW;
when "00000" => s_instr_t <= instr_AMOADDW;
when "00100" => s_instr_t <= instr_AMOXORW;
when "01100" => s_instr_t <= instr_AMOANDW;
when "01000" => s_instr_t <= instr_AMOORW;
when "10000" => s_instr_t <= instr_AMOMINW;
when "10100" => s_instr_t <= instr_AMOMAXW;
when "11000" => s_instr_t <= instr_AMOMINUW;
when "11100" => s_instr_t <= instr_AMOMAXUW;
when others => --error state
end case;
end if;
when FLOAD_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FLW;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_FLD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when FSTORE_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FSW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_FSD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => --error state
end case;
when FMADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMADDS;
else
s_instr_t <= instr_FMADDD;
end if;
when FMSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMSUBS;
else
s_instr_t <= instr_FMSUBD;
end if;
when FNADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMADDS;
else
s_instr_t <= instr_FNMADDD;
end if;
when FNSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMSUBS;
else
s_instr_t <= instr_FNMSUBD;
end if;
when FPALU_T =>
case instr(31 downto 25) is
when "0000000" =>
s_instr_t <= instr_FADDS;
when "0000100" =>
s_instr_t <= instr_FSUBS;
when "0001000" =>
s_instr_t <= instr_FMULS;
when "0001100" =>
s_instr_t <= instr_FDIVS;
when "0101100" =>
s_instr_t <= instr_FSQRTS;
when "0010000" =>
if (instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJS;
elsif (instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJNS;
else
s_instr_t <= instr_FSGNJXS;
end if;
when "0010100" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMINS;
else
s_instr_t <= instr_FMAXS;
end if;
when "1100000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWS;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUS;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLS;
else
s_instr_t <= instr_FCVTLUS;
end if;
when "1110000" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMVXW;
else
s_instr_t <= instr_FCLASSS;
end if;
when "1010000" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQS;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTS;
else
s_instr_t <= instr_FLES;
end if;
when "1101000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTSW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTSWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTSL;
else
s_instr_t <= instr_FCVTSLU;
end if;
when "1111000" =>
s_instr_t <= instr_FMVWX;
when "0000001" =>
s_instr_t <= instr_FADDD;
when "0000101" =>
s_instr_t <= instr_FSUBD;
when "0001001" =>
s_instr_t <= instr_FMULD;
when "0001101" =>
s_instr_t <= instr_FDIVD;
when "0101101" =>
s_instr_t <= instr_FSQRTD;
when "0010001" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJND;
else
s_instr_t <= instr_FSGNJXD;
end if;
when "0010101" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMIND;
else
s_instr_t <= instr_FMAXD;
end if;
when "0100000" =>
s_instr_t <= instr_FCVTSD;
when "0100001" =>
s_instr_t <= instr_FCVTDS;
when "1010001" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTD;
else
s_instr_t <= instr_FLED;
end if;
when "1110001" =>
if(instr(14 downto 12) = "001") then
s_instr_t <= instr_FCLASSD;
else
s_instr_t <= instr_FMVXD;
end if;
when "1100001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWD;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUD;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLD;
else
s_instr_t <= instr_FCVTLUD;
end if;
when "1101001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTDW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTDWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTDL;
else
s_instr_t <= instr_FCVTDLU;
end if;
when "1111001" =>
s_instr_t <= instr_FMVDX;
when others => --error state
end case;
when others => -- error state
end case;
end process;
s_rd <= instr(11 downto 7);
s_rs1 <= instr(19 downto 15);
s_rs2 <= instr(24 downto 20);
s_rs3 <= instr(31 downto 27);
rd <= s_rd;
rs1 <= s_rs1;
rs2 <= s_rs2;
rs3 <= s_rs3;
reg_A <= to_integer(unsigned(s_rs1));
reg_B <= to_integer(unsigned(s_rs2));
reg_C <= to_integer(unsigned(s_rs3));
reg_D <= to_integer(unsigned(s_rd));
funct3 <= instr(14 downto 12);
funct6 <= instr(31 downto 26);
funct7 <= instr(31 downto 25);
opcode <= instr(6 downto 0);
imm12 <= s_imm12;
imm20 <= s_imm20;
shamt <= s_shamt;
csr <= s_csr;
instr_code <= s_instr_t;
sext_imm12(63 downto 12) <= (others => s_imm12(11));
sext_imm12(11 downto 0) <= s_imm12;
sext_imm20(63 downto 20) <= (others => s_imm20(19));
sext_imm20(19 downto 0) <= s_imm20;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_master
-- File: pt_pci_master.vhd
-- Author: Nils Johan Wessman, Aeroflex Gaisler
-- Description: PCI Testbench Master
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
use grlib.stdlib.tost;
use grlib.testlib.print;
entity pt_pci_master is
generic (
slot : integer := 0;
tval : time := 7 ns);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- Debug interface signals
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end pt_pci_master;
architecture behav of pt_pci_master is
-- NEW =>
type access_element_type;
type access_element_ptr is access access_element_type;
type access_element_type is record
acc : pt_pci_access_type;
nxt : access_element_ptr;
end record;
constant idle_acc : pt_pci_access_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'),
0, 0, 0, 0, false, false, false, false, 0, 0);
signal pci_core : pt_pci_master_in_type;
signal core_pci : pt_pci_master_out_type;
-- Description: Insert a access at the "tail" of the linked list of accesses
procedure add_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type) is
variable elem : access_element_ptr;
begin -- insert_access
elem := acc_tail;
if elem /= NULL then
elem.nxt := new access_element_type'(acc, NULL);
acc_tail := elem.nxt;
else
acc_head := new access_element_type'(acc, NULL);
acc_tail := acc_head;
end if;
end add_acc;
-- Description: Get the access at the "head" of the linked list of accesses
-- and remove if from the list
procedure pop_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem : access_element_ptr;
begin -- pop_access
elem := acc_head;
if elem /= NULL then
found := true;
acc <= elem.acc;
if elem = acc_tail then
acc_head := NULL;
acc_tail := NULL;
else
acc_head := elem.nxt;
end if;
deallocate(elem);
else
found := false;
acc <= idle_acc;
end if;
end pop_acc;
-- Description: Searches the list for a result to a particular id.
procedure get_res (
variable res_head : inout access_element_ptr;
variable res_tail : inout access_element_ptr;
signal accin : in pt_pci_access_type;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- get_result
prev := res_head;
elem := res_head;
while elem /= NULL and not lfound loop
-- Check if result is a match for id
if accin.id = elem.acc.id then
acc <= elem.acc;
lfound := true;
if prev = res_head then
res_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = res_tail then
res_tail := NULL;
end if;
deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
if lfound then found := true;
else found := false; acc <= idle_acc; end if;
end get_res;
-- Description:
procedure rm_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type;
constant rmall : in boolean )is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- rm_access
prev := acc_head;
elem := acc_head;
while elem /= NULL and not lfound loop
if rmall = true then
prev := elem;
elem := elem.nxt;
deallocate(prev);
else
if acc.addr = elem.acc.addr then
if prev = acc_head then
acc_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = acc_tail then
acc_tail := NULL;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end if;
end loop;
if rmall = true then
acc_head := NULL;
acc_tail := NULL;
end if;
end rm_acc;
-- <= NEW
type state_type is(idle, addr, data, turn, active, done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
perren : std_logic_vector(1 downto 0);
read : std_logic;
grant : std_logic;
perr_ad : std_logic_vector(31 downto 0);
perr_cbe : std_logic_vector(3 downto 0);
devsel_timeout : integer range 0 to 3;
pci : pci_type;
acc : pt_pci_access_type;
parerr : std_logic;
end record;
signal r,rin : reg_type;
begin
-- NEW =>
core_acc : process
variable acc_head : access_element_ptr := NULL;
variable acc_tail : access_element_ptr := NULL;
variable res_head : access_element_ptr := NULL;
variable res_tail : access_element_ptr := NULL;
variable res_to_find : pt_pci_access_type := idle_acc;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
dbgo.res_found <= '0';
if dbgi.add = true then
add_acc(acc_head, acc_tail, dbgi.acc);
elsif dbgi.remove = true then
rm_acc(acc_head, acc_tail, dbgi.acc, dbgi.rmall);
elsif dbgi.get_res = true then
dbgo.valid <= false;
get_res(res_head, res_tail, dbgi.acc, dbgo.acc, found);
if found = true then dbgo.valid <= true; res_to_find := idle_acc;
else res_to_find := dbgi.acc; end if;
else
dbgo.valid <= false;
pop_acc(acc_head, acc_tail, dbgo.acc, found);
if found = true then dbgo.valid <= true; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.add = true then
add_acc(acc_head, acc_tail, pci_core.acc);
elsif pci_core.add_res = true then
add_acc(res_head, res_tail, pci_core.acc);
if res_to_find.valid = true and pci_core.acc.id = res_to_find.id then
dbgo.res_found <= '1';
end if;
else
core_pci.valid <= false;
pop_acc(acc_head, acc_tail, core_pci.acc, found);
if found = true then core_pci.valid <= true; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
-- <= NEW
pt_pci_core : process
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
function check_data(
constant pci_data : std_logic_vector(31 downto 0);
constant comp_data : std_logic_vector(31 downto 0);
constant cbe : std_logic_vector(3 downto 0))
return boolean is
variable res : boolean := true;
variable data : std_logic_vector(31 downto 0);
begin
data := comp_data;
if cbe(0) = '1' then data(7 downto 0) := (others => '-'); end if;
if cbe(1) = '1' then data(15 downto 8) := (others => '-'); end if;
if cbe(2) = '1' then data(23 downto 16) := (others => '-'); end if;
if cbe(3) = '1' then data(31 downto 24) := (others => '-'); end if;
for i in 0 to 31 loop
if pci_data(i) /= data(i) and data(i) /= '-' then res := false; end if;
end loop;
return res;
end check_data;
variable v : reg_type;
begin
if to_x01(pciin.syst.rst) = '0' then
v.state := idle;
v.pcien := (others => '0');
v.pci := pci_idle;
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
v.read := '0';
v.perren := (others => '0');
v.parerr := '0';
elsif rising_edge(pciin.syst.clk) then
v := r;
v.grant := to_x01(pciin.ifc.frame) and to_x01(pciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(pciin.arb.gnt(slot));
v.pcien(1) := r.pcien(0); v.pcien(2) := r.pcien(1);
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe & r.parerr);
v.perr_ad := pciin.ad.ad; v.perr_cbe := pciin.ad.cbe;
v.pci.err.perr := (not xorv(r.perr_ad & r.perr_cbe & to_x01(pciin.ad.par))) or not r.read;
v.perren(1) := r.perren(0);
case r.state is
when idle =>
if core_pci.valid = true then
if r.acc.idle = false then
v.pci.arb.req(slot) := '0';
if v.grant = '1' then
v.pcien(0) := '1';
v.pci.ifc.frame := '0';
v.pci.ad.ad := core_pci.acc.addr;
v.pci.ad.cbe := core_pci.acc.cbe_cmd;
if core_pci.acc.parerr = 2 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := addr;
v.read := '0';
v.perren := (others => '0');
end if;
else -- Idle cycle
if r.acc.ws <= 0 then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
else
v.acc.ws := r.acc.ws - 1;
end if;
end if;
else
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
end if;
when addr =>
if r.acc.last = true and r.acc.ws <= 0 then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
if (r.acc.cbe_cmd = MEM_READ or r.acc.cbe_cmd = MEM_R_MULT or r.acc.cbe_cmd = MEM_R_LINE
or r.acc.cbe_cmd = IO_READ or r.acc.cbe_cmd = CONF_READ) then
v.read := '1';
end if;
if r.acc.ws <= 0 then v.pci.ifc.irdy := '0'; v.pci.ad.ad := r.acc.data;
else v.acc.ws := r.acc.ws - 1; v.pci.ad.ad := (others => '-'); end if;
v.pci.ad.cbe := r.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := data;
v.devsel_timeout := 0;
when data =>
if r.pci.ifc.irdy = '1' and r.acc.ws /= 0 then
v.acc.ws := r.acc.ws - 1;
else
v.pci.ifc.irdy := '0';
v.pci.ad.ad := r.acc.data;
if r.acc.last = true or to_x01(pciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
end if;
if to_x01(pciin.ifc.devsel) = '1' then
if r.devsel_timeout < 3 then
v.devsel_timeout := r.devsel_timeout + 1;
else
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
if r.pci.ifc.frame = '1' then
v.pcien(0) := '0';
v.state := idle;
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- FIXME: should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: MASTER ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: MASTER ABORT");
end if;
end if;
end if;
end if;
end if;
--if to_x01(pciin.ifc.trdy) = '0' and r.pci.ifc.irdy = '0' then
if (to_x01(pciin.ifc.trdy) = '0' or (r.acc.cod = 1 and to_x01(pciin.ifc.stop) = '0')) and r.pci.ifc.irdy = '0' then
if r.read = '1' then v.perren(0) := '1'; end if; -- only drive perr from read
if r.pci.ifc.frame = '1' then -- done
v.pcien(0) := '0'; v.pci.ifc.irdy := '1';
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= pciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
v.state := idle;
else
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= pciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if core_pci.valid = true then
v.pci.ad.cbe := v.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
if v.acc.ws <= 0 then
v.pci.ad.ad := v.acc.data;
if v.acc.last = true or to_x01(pciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
else
v.pci.ad.ad := (others => '-');
if v.pci.ifc.frame = '0' then v.pci.ifc.irdy := '1'; end if; -- If frame => '1', do not add waitstates (irdey => '1')
v.acc.ws := v.acc.ws - 1;
end if;
else
assert false
report "No valid acces in list, access required! (no access is marked LAST)"
severity FAILURE;
end if;
end if;
if r.acc.debug >= 1 then
if r.acc.cod = 1 and to_x01(pciin.ifc.stop) = '0' and to_x01(pciin.ifc.trdy) = '1' then
if r.read = '1' then
print("PCITBM Read[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
else
print("PCITBM WRITE[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
end if;
else
if r.read = '1' then
if check_data(pciin.ad.ad, r.pci.ad.ad, r.pci.ad.cbe) = false then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad) & " != " & tost(r.pci.ad.ad));
elsif r.acc.debug >= 2 then
print("PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad));
end if;
else
if r.acc.debug >= 2 then
print("PCITBM Write[" & tost(r.acc.addr) & "]: " & tost(pciin.ad.ad));
end if;
end if;
end if;
end if;
elsif to_x01(pciin.ifc.stop) = '0' and r.pci.ifc.frame = '1' then -- Disconnect
v.pcien(0) := '0';
v.pci.ifc.irdy := '1';
v.state := idle;
if to_x01(pciin.ifc.devsel) = '1' then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- FIXME: should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: TARGET ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: TARGET ABORT");
end if;
end if;
end if;
end if;
when turn =>
when active =>
when done =>
when others =>
end case;
end if;
r <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.pcien(0) and not r.read) = '1' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '1' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.pcien(1) = '1' and (r.read = '0' or r.pcien(3 downto 0) = "0011")) else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '1' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '1' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when (r.pcien(2) and r.perren(1)) = '1' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '1' else 'Z' after tval;
-- Unused signals
pciout.arb <= arb_const;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
-- Unused signals
pciout.ifc.trdy <= 'Z';
pciout.ifc.stop <= 'Z';
pciout.ifc.devsel <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
|
-------------------------------------------------------------------------------
-- $Id: dma_sg.vhd,v 1.5 2003/11/04 20:11:33 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg entity (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg.vhd
--
-- Description: Entity declaration for dma_sg.
-- This entity defines a DMA capability that is intended
-- for embodiement inside the IPIF (IP Interface).
--
-- Four types of DMA channels are available:
-- (1) Simple DMA
-- (2) Scatter gather DMA
-- (3) Scatter gather packet transmit
-- (4) Scatter gather packet receive
--
-- An arbitrary number of channels, each of any of the types,
-- may be included in an instantiation through appropriate
-- generic settings.
--
-- Packet transmit and receive channels may be outfitted with
-- optional interrupt-coalescing support.
--
-- The maximum length of DMA transfers is user selectable and
-- using the smallest feasible value may reduce FPGA resource
-- usage.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
-- -- Channels fixed at two for this version
-- -- to allow XST E.33 compatibility.
--
-- FLO 06/07/02 -- Added generic C_WFIFO_VACANCY_WIDTH.
--
-- FLO 01/30/03
-- ^^^^^^
-- Fixed Bus2IP_Data and DMA2Bus_Data at 32 bits, 0 to 31.
-- Fixed Bus2IP_BE 4 bits, 0 to 3.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- Added generics C_DMA_SHORT_BURST_REMAINDER and C_DMA_BURST_SIZE.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_BURST_SIZE: positive := 16; -- Must be a power of 2
C_DMA_SHORT_BURST_REMAINDER : integer := 1;
C_MA2SA_NUM_WIDTH : INTEGER := 8;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to C_DMA_CHAN_TYPE'length-1)
);
constant TPB : positive := C_DMA_BURST_SIZE;
end dma_sg;
|
-------------------------------------------------------------------------------
-- $Id: dma_sg.vhd,v 1.5 2003/11/04 20:11:33 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg entity (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg.vhd
--
-- Description: Entity declaration for dma_sg.
-- This entity defines a DMA capability that is intended
-- for embodiement inside the IPIF (IP Interface).
--
-- Four types of DMA channels are available:
-- (1) Simple DMA
-- (2) Scatter gather DMA
-- (3) Scatter gather packet transmit
-- (4) Scatter gather packet receive
--
-- An arbitrary number of channels, each of any of the types,
-- may be included in an instantiation through appropriate
-- generic settings.
--
-- Packet transmit and receive channels may be outfitted with
-- optional interrupt-coalescing support.
--
-- The maximum length of DMA transfers is user selectable and
-- using the smallest feasible value may reduce FPGA resource
-- usage.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
-- -- Channels fixed at two for this version
-- -- to allow XST E.33 compatibility.
--
-- FLO 06/07/02 -- Added generic C_WFIFO_VACANCY_WIDTH.
--
-- FLO 01/30/03
-- ^^^^^^
-- Fixed Bus2IP_Data and DMA2Bus_Data at 32 bits, 0 to 31.
-- Fixed Bus2IP_BE 4 bits, 0 to 3.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- Added generics C_DMA_SHORT_BURST_REMAINDER and C_DMA_BURST_SIZE.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_BURST_SIZE: positive := 16; -- Must be a power of 2
C_DMA_SHORT_BURST_REMAINDER : integer := 1;
C_MA2SA_NUM_WIDTH : INTEGER := 8;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to C_DMA_CHAN_TYPE'length-1)
);
constant TPB : positive := C_DMA_BURST_SIZE;
end dma_sg;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
------------------------------------------------------------------------------
-- Title : Wishbone Ethernet MAC Wrapper
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-26-08
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone Wrapper for RS232 Master
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-26-08 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
entity wb_rs232_syscon is
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
m_wb_adr_o : out std_logic_vector(31 downto 0);
m_wb_sel_o : out std_logic_vector(3 downto 0);
m_wb_we_o : out std_logic;
m_wb_dat_o : out std_logic_vector(31 downto 0);
m_wb_dat_i : in std_logic_vector(31 downto 0);
m_wb_cyc_o : out std_logic;
m_wb_stb_o : out std_logic;
m_wb_ack_i : in std_logic;
m_wb_err_i : in std_logic;
m_wb_stall_i : in std_logic;
m_wb_rty_i : in std_logic
);
end wb_rs232_syscon;
architecture rtl of wb_rs232_syscon is
signal rst : std_logic;
signal rst_out : std_logic;
signal m_wb_adr_out : std_logic_vector(31 downto 0);
signal m_wb_sel_out : std_logic_vector(3 downto 0);
signal m_wb_we_out : std_logic;
signal m_wb_dat_out : std_logic_vector(31 downto 0);
signal m_wb_dat_in : std_logic_vector(31 downto 0);
signal m_wb_cyc_out : std_logic;
signal m_wb_stb_out : std_logic;
signal m_wb_ack_in : std_logic;
signal m_wb_err_in : std_logic;
signal m_wb_stall_in : std_logic;
signal m_wb_rty_in : std_logic;
component rs232_syscon_top_1_0
port (
clk_i : in std_logic;
reset_i : in std_logic;
ack_i : in std_logic;
err_i : in std_logic;
rs232_rxd_i : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
cyc_o : out std_logic;
adr_o : out std_logic_vector(31 downto 0);
we_o : out std_logic;
rs232_txd_o : out std_logic;
sel_o : out std_logic_vector(3 downto 0)
);
end component;
begin
rst <= not wb_rstn_i;
-- ETHMAC master interface is byte addressed, classic wishbone
cmp_ma_iface_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => false,
g_master_mode => g_ma_interface_mode,
g_master_granularity => g_ma_address_granularity,
g_slave_use_struct => false,
g_slave_mode => CLASSIC,
g_slave_granularity => BYTE
)
port map (
clk_sys_i => wb_clk_i,
rst_n_i => wb_rstn_i,
sl_adr_i => m_wb_adr_out,
sl_dat_i => m_wb_dat_out,
sl_sel_i => m_wb_sel_out,
sl_cyc_i => m_wb_cyc_out,
sl_stb_i => m_wb_stb_out,
sl_we_i => m_wb_we_out,
sl_dat_o => m_wb_dat_in,
sl_ack_o => m_wb_ack_in,
sl_stall_o => open,
sl_int_o => open,
sl_rty_o => open,
sl_err_o => m_wb_err_in,
ma_adr_o => m_wb_adr_o,
ma_dat_o => m_wb_dat_o,
ma_sel_o => m_wb_sel_o,
ma_cyc_o => m_wb_cyc_o,
ma_stb_o => m_wb_stb_o,
ma_we_o => m_wb_we_o,
ma_dat_i => m_wb_dat_i,
ma_ack_i => m_wb_ack_i,
ma_stall_i => m_wb_stall_i,
ma_rty_i => m_wb_rty_i,
ma_err_i => m_wb_err_i
);
cmp_rs232_syscon_top_1_0 : rs232_syscon_top_1_0
port map (
clk_i => wb_clk_i,
reset_i => rst,
ack_i => m_wb_ack_in,
err_i => m_wb_err_in,
rs232_rxd_i => rs232_rxd_i,
data_in => m_wb_dat_in,
data_out => m_wb_dat_out,
rst_o => rst_out,
stb_o => m_wb_stb_out,
cyc_o => m_wb_cyc_out,
adr_o => m_wb_adr_out,
we_o => m_wb_we_out,
rs232_txd_o => rs232_txd_o,
sel_o => m_wb_sel_out
);
rstn_o <= not rst_out;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2032.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02032ent IS
END c07s02b04x00p01n01i02032ent;
ARCHITECTURE c07s02b04x00p01n01i02032arch OF c07s02b04x00p01n01i02032ent IS
BEGIN
TESTING: PROCESS
variable CHARV : CHARACTER := '0';
BEGIN
CHARV := '0' - '2';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02032 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02032arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2032.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02032ent IS
END c07s02b04x00p01n01i02032ent;
ARCHITECTURE c07s02b04x00p01n01i02032arch OF c07s02b04x00p01n01i02032ent IS
BEGIN
TESTING: PROCESS
variable CHARV : CHARACTER := '0';
BEGIN
CHARV := '0' - '2';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02032 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02032arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2032.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02032ent IS
END c07s02b04x00p01n01i02032ent;
ARCHITECTURE c07s02b04x00p01n01i02032arch OF c07s02b04x00p01n01i02032ent IS
BEGIN
TESTING: PROCESS
variable CHARV : CHARACTER := '0';
BEGIN
CHARV := '0' - '2';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02032 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02032arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAZE is
port (CLK : in std_logic;
-- EN : in std_logic;
ADDR : in std_logic_vector(13 downto 0);
DATA : out std_logic);
end MAZE;
architecture syn of MAZE is
type rom_type is array (0 to 9599) of std_logic;
constant ROM : rom_type:= (
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);
signal rdata : std_logic;
begin
rdata <= ROM(conv_integer(ADDR));
process (CLK)
begin
if (rising_edge(CLK)) then
-- if (EN = '1') then
DATA <= rdata;
-- end if;
end if;
end process;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAZE is
port (CLK : in std_logic;
-- EN : in std_logic;
ADDR : in std_logic_vector(13 downto 0);
DATA : out std_logic);
end MAZE;
architecture syn of MAZE is
type rom_type is array (0 to 9599) of std_logic;
constant ROM : rom_type:= (
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);
signal rdata : std_logic;
begin
rdata <= ROM(conv_integer(ADDR));
process (CLK)
begin
if (rising_edge(CLK)) then
-- if (EN = '1') then
DATA <= rdata;
-- end if;
end if;
end process;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAZE is
port (CLK : in std_logic;
-- EN : in std_logic;
ADDR : in std_logic_vector(13 downto 0);
DATA : out std_logic);
end MAZE;
architecture syn of MAZE is
type rom_type is array (0 to 9599) of std_logic;
constant ROM : rom_type:= (
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);
signal rdata : std_logic;
begin
rdata <= ROM(conv_integer(ADDR));
process (CLK)
begin
if (rising_edge(CLK)) then
-- if (EN = '1') then
DATA <= rdata;
-- end if;
end if;
end process;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAZE is
port (CLK : in std_logic;
-- EN : in std_logic;
ADDR : in std_logic_vector(13 downto 0);
DATA : out std_logic);
end MAZE;
architecture syn of MAZE is
type rom_type is array (0 to 9599) of std_logic;
constant ROM : rom_type:= (
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);
signal rdata : std_logic;
begin
rdata <= ROM(conv_integer(ADDR));
process (CLK)
begin
if (rising_edge(CLK)) then
-- if (EN = '1') then
DATA <= rdata;
-- end if;
end if;
end process;
end syn;
|
library verilog;
use verilog.vl_types.all;
entity AD9273_SPI_Config is
generic(
CHIP_PORT_CONFIG: integer := 24;
CHIP_ID : integer := 47;
CHIP_GRADE : integer := 16;
DEVICE_INDEX2 : integer := 15;
DEVICE_INDEX1 : integer := 15;
DEVICE_UPDATE_EN: integer := 1;
DEVICE_UPDATE_DIS: integer := 0;
Modes : integer := 0;
Clock : integer := 1;
TEST_IO : integer := 0;
FLEX_CHANNEL_INPUT: integer := 14;
FLEX_OFFSET : integer := 32;
FLEX_GAIN : integer := 14;
BIAS_CURRENT : integer := 8;
OUTPUT_MODE : integer := 0;
OUTPUT_ADJUST : integer := 49;
OUTPUT_PHASE : integer := 3;
FLEX_VREF : integer := 0;
USER_PATT1_LSB : integer := 0;
USER_PATT1_MSB : integer := 0;
USER_PATT2_LSB : integer := 0;
USER_PATT2_MSB : integer := 0;
SERIAL_CONTROL : integer := 0;
SERIAL_CH_STAT : integer := 0;
FLEX_FILTER : integer := 0;
ANALOG_INPUT : integer := 1;
CROSS_POINT_SWITCH: integer := 0;
DELAY_A : integer := 3;
DELAY_B : integer := 3;
DELAY_C : integer := 3;
DELAY_D : integer := 3;
DELAY_E : integer := 3;
DELAY_F : integer := 3;
DELAY_G : integer := 3;
DELAY_H : integer := 3;
SPI_PR : integer := 0;
SPI_REQ : integer := 1;
SPI_WAIT : integer := 2;
SPI_END : integer := 3
);
port(
RST_n : in vl_logic;
SPI_CLK : in vl_logic;
SPI_Data : inout vl_logic;
SPI_CS : out vl_logic
);
end AD9273_SPI_Config;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instruct_blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruct_blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END instruct_blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF instruct_blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT instruct_blk_mem_gen_v7_3 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : instruct_blk_mem_gen_v7_3
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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PKRjDpHeJeFLxfpAkPo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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F0wZ7hvMbQHoQpFHp7E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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utTL7KxYKEy+2SzcXba2pWK0oH+GTNkedg2TSg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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bugTtI5qAw==
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14816)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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bugTtI5qAw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14816)
`protect data_block
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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QEy0WVnszcNG6mFB+Xm/GmE/2FqfPBI9FbOkciuShjkfM63h7Kc6F9O04OuM7FkfcCZMm+a3U5YJ
QRuIDOy5R9BlgH+Bbwq0/KOTJOLT5ukxlRSVyh6W3bcsxkoBv3SdNeo/QNrp3MApGDSaF3bzQYO5
u9BNULCKmS1QOmBSq24JlnsdYPoNcIcQnXZ2r01c+WZGbn3XNdOAd7RStq9VXZZtAjUQLG8HdLsr
Yf84b0gl8zNifan/lVvyqUq7QSgUiuXH++8lfy3mJHs0w6YJi6OdLGV0TPgJOU0GaOGm1WlTlEe7
+2l1kUAdnAX6iYY28rZ6SiRHesODhL2Wi8klfP5S64FutLE7Zp1SykGkbzcor5JYKt0Hj4VXxjDT
Q//2aEIdx0gqZ6DN4pS/iKEsurPQflZLNyWP0NmV0vpaYY5Xmu1dM/NTHAcMGXf80HpnDi2pzHq6
bjpCHARcIZAdYlHsOVm00e7M7DXhQWzECsw8HOt6bDiQrSds0ourccqESUcYAt9p9C7JbczrY7bB
qun56x2ol7G52TFeHC5gpIex6VzlaNcqnnvVf/P/J6ZBsP1Y2RO/uYTGWD1UI1q5w9I9uskNMi7t
279oblJM+Heoa2hZkjrKa1CA+pItTlymRRn9ChXONTVZNclznSCwSfNz8REqxwk3rvqRX6XlF+pa
ohLlUpaOBCQZn+YXdaafFmdmVh0nqAh+GpzAOa5JqF2y37avVQXDr0yF0FT/UAnAsR9zUam5BGk0
3GmSAiDSFHQVosdE+kBmzkx/Wdc2uzHpSALWaAsZ/ElRnlKSv1A97+ao4E/PB2DvmwGJYPxgvY+x
0QYUt5eIatkb+N06dRZM7jXXIM4NHoTz84i430NYCqCNf3Gm8uOxiUokxVTzasNJawt1/oK7zIjZ
QzbP2Q7M4L8lsymQMw1dnY08h6SLpEGl3D5sdQDgcrj1yRiz4lvlj5ciEI0iXvToKRQJiBmox36q
PsiMR4c1k0eKmzrZLKDtmlYrZucFwiIUkJnT0M7mjWY/nEJoKdLpEnAB5sbmKo92/jvsPBs=
`protect end_protected
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity mux_1hot is
generic (
data_bits : natural := 1;
sel_bits : natural := 2
);
port (
din : in std_ulogic_vector2(sel_bits-1 downto 0, data_bits-1 downto 0);
sel : in std_ulogic_vector(sel_bits-1 downto 0);
dout : out std_ulogic_vector(data_bits-1 downto 0)
);
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: dataMemory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 1
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : dataMemory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 1
-- C_RST_PRIORITY_A : SR
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 4
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 64
-- C_READ_DEPTH_A : 64
-- C_ADDRA_WIDTH : 32
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 4
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 64
-- C_READ_DEPTH_B : 64
-- C_ADDRB_WIDTH : 32
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dataMemory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END dataMemory_prod;
ARCHITECTURE xilinx OF dataMemory_prod IS
COMPONENT dataMemory_exdes IS
PORT (
--Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : dataMemory_exdes
PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:12 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_debounce_0_0 -prefix
-- system_debounce_0_0_ system_debounce_0_0_sim_netlist.vhdl
-- Design : system_debounce_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0_debounce is
port (
signal_out : out STD_LOGIC;
clk : in STD_LOGIC;
signal_in : in STD_LOGIC
);
end system_debounce_0_0_debounce;
architecture STRUCTURE of system_debounce_0_0_debounce is
signal \c[0]_i_3_n_0\ : STD_LOGIC;
signal \c[0]_i_4_n_0\ : STD_LOGIC;
signal \c[0]_i_5_n_0\ : STD_LOGIC;
signal \c[0]_i_6_n_0\ : STD_LOGIC;
signal \c[12]_i_2_n_0\ : STD_LOGIC;
signal \c[12]_i_3_n_0\ : STD_LOGIC;
signal \c[12]_i_4_n_0\ : STD_LOGIC;
signal \c[12]_i_5_n_0\ : STD_LOGIC;
signal \c[16]_i_2_n_0\ : STD_LOGIC;
signal \c[16]_i_3_n_0\ : STD_LOGIC;
signal \c[16]_i_4_n_0\ : STD_LOGIC;
signal \c[16]_i_5_n_0\ : STD_LOGIC;
signal \c[20]_i_2_n_0\ : STD_LOGIC;
signal \c[20]_i_3_n_0\ : STD_LOGIC;
signal \c[20]_i_4_n_0\ : STD_LOGIC;
signal \c[20]_i_5_n_0\ : STD_LOGIC;
signal \c[4]_i_2_n_0\ : STD_LOGIC;
signal \c[4]_i_3_n_0\ : STD_LOGIC;
signal \c[4]_i_4_n_0\ : STD_LOGIC;
signal \c[4]_i_5_n_0\ : STD_LOGIC;
signal \c[8]_i_2_n_0\ : STD_LOGIC;
signal \c[8]_i_3_n_0\ : STD_LOGIC;
signal \c[8]_i_4_n_0\ : STD_LOGIC;
signal \c[8]_i_5_n_0\ : STD_LOGIC;
signal c_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \c_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_7\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal signal_out_i_1_n_0 : STD_LOGIC;
signal signal_out_i_2_n_0 : STD_LOGIC;
signal signal_out_i_3_n_0 : STD_LOGIC;
signal signal_out_i_4_n_0 : STD_LOGIC;
signal signal_out_i_5_n_0 : STD_LOGIC;
signal \NLW_c_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\c[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => signal_in,
O => clear
);
\c[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(3),
O => \c[0]_i_3_n_0\
);
\c[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(2),
O => \c[0]_i_4_n_0\
);
\c[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(1),
O => \c[0]_i_5_n_0\
);
\c[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => c_reg(0),
O => \c[0]_i_6_n_0\
);
\c[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(15),
O => \c[12]_i_2_n_0\
);
\c[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(14),
O => \c[12]_i_3_n_0\
);
\c[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(13),
O => \c[12]_i_4_n_0\
);
\c[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(12),
O => \c[12]_i_5_n_0\
);
\c[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(19),
O => \c[16]_i_2_n_0\
);
\c[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(18),
O => \c[16]_i_3_n_0\
);
\c[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(17),
O => \c[16]_i_4_n_0\
);
\c[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(16),
O => \c[16]_i_5_n_0\
);
\c[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(23),
O => \c[20]_i_2_n_0\
);
\c[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(22),
O => \c[20]_i_3_n_0\
);
\c[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(21),
O => \c[20]_i_4_n_0\
);
\c[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(20),
O => \c[20]_i_5_n_0\
);
\c[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(7),
O => \c[4]_i_2_n_0\
);
\c[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(6),
O => \c[4]_i_3_n_0\
);
\c[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(5),
O => \c[4]_i_4_n_0\
);
\c[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(4),
O => \c[4]_i_5_n_0\
);
\c[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(11),
O => \c[8]_i_2_n_0\
);
\c[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(10),
O => \c[8]_i_3_n_0\
);
\c[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(9),
O => \c[8]_i_4_n_0\
);
\c[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(8),
O => \c[8]_i_5_n_0\
);
\c_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_7\,
Q => c_reg(0),
R => clear
);
\c_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \c_reg[0]_i_2_n_0\,
CO(2) => \c_reg[0]_i_2_n_1\,
CO(1) => \c_reg[0]_i_2_n_2\,
CO(0) => \c_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \c_reg[0]_i_2_n_4\,
O(2) => \c_reg[0]_i_2_n_5\,
O(1) => \c_reg[0]_i_2_n_6\,
O(0) => \c_reg[0]_i_2_n_7\,
S(3) => \c[0]_i_3_n_0\,
S(2) => \c[0]_i_4_n_0\,
S(1) => \c[0]_i_5_n_0\,
S(0) => \c[0]_i_6_n_0\
);
\c_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_5\,
Q => c_reg(10),
R => clear
);
\c_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_4\,
Q => c_reg(11),
R => clear
);
\c_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_7\,
Q => c_reg(12),
R => clear
);
\c_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[8]_i_1_n_0\,
CO(3) => \c_reg[12]_i_1_n_0\,
CO(2) => \c_reg[12]_i_1_n_1\,
CO(1) => \c_reg[12]_i_1_n_2\,
CO(0) => \c_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[12]_i_1_n_4\,
O(2) => \c_reg[12]_i_1_n_5\,
O(1) => \c_reg[12]_i_1_n_6\,
O(0) => \c_reg[12]_i_1_n_7\,
S(3) => \c[12]_i_2_n_0\,
S(2) => \c[12]_i_3_n_0\,
S(1) => \c[12]_i_4_n_0\,
S(0) => \c[12]_i_5_n_0\
);
\c_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_6\,
Q => c_reg(13),
R => clear
);
\c_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_5\,
Q => c_reg(14),
R => clear
);
\c_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_4\,
Q => c_reg(15),
R => clear
);
\c_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_7\,
Q => c_reg(16),
R => clear
);
\c_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[12]_i_1_n_0\,
CO(3) => \c_reg[16]_i_1_n_0\,
CO(2) => \c_reg[16]_i_1_n_1\,
CO(1) => \c_reg[16]_i_1_n_2\,
CO(0) => \c_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[16]_i_1_n_4\,
O(2) => \c_reg[16]_i_1_n_5\,
O(1) => \c_reg[16]_i_1_n_6\,
O(0) => \c_reg[16]_i_1_n_7\,
S(3) => \c[16]_i_2_n_0\,
S(2) => \c[16]_i_3_n_0\,
S(1) => \c[16]_i_4_n_0\,
S(0) => \c[16]_i_5_n_0\
);
\c_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_6\,
Q => c_reg(17),
R => clear
);
\c_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_5\,
Q => c_reg(18),
R => clear
);
\c_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_4\,
Q => c_reg(19),
R => clear
);
\c_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_6\,
Q => c_reg(1),
R => clear
);
\c_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_7\,
Q => c_reg(20),
R => clear
);
\c_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[16]_i_1_n_0\,
CO(3) => \NLW_c_reg[20]_i_1_CO_UNCONNECTED\(3),
CO(2) => \c_reg[20]_i_1_n_1\,
CO(1) => \c_reg[20]_i_1_n_2\,
CO(0) => \c_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[20]_i_1_n_4\,
O(2) => \c_reg[20]_i_1_n_5\,
O(1) => \c_reg[20]_i_1_n_6\,
O(0) => \c_reg[20]_i_1_n_7\,
S(3) => \c[20]_i_2_n_0\,
S(2) => \c[20]_i_3_n_0\,
S(1) => \c[20]_i_4_n_0\,
S(0) => \c[20]_i_5_n_0\
);
\c_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_6\,
Q => c_reg(21),
R => clear
);
\c_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_5\,
Q => c_reg(22),
R => clear
);
\c_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_4\,
Q => c_reg(23),
R => clear
);
\c_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_5\,
Q => c_reg(2),
R => clear
);
\c_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_4\,
Q => c_reg(3),
R => clear
);
\c_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_7\,
Q => c_reg(4),
R => clear
);
\c_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[0]_i_2_n_0\,
CO(3) => \c_reg[4]_i_1_n_0\,
CO(2) => \c_reg[4]_i_1_n_1\,
CO(1) => \c_reg[4]_i_1_n_2\,
CO(0) => \c_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[4]_i_1_n_4\,
O(2) => \c_reg[4]_i_1_n_5\,
O(1) => \c_reg[4]_i_1_n_6\,
O(0) => \c_reg[4]_i_1_n_7\,
S(3) => \c[4]_i_2_n_0\,
S(2) => \c[4]_i_3_n_0\,
S(1) => \c[4]_i_4_n_0\,
S(0) => \c[4]_i_5_n_0\
);
\c_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_6\,
Q => c_reg(5),
R => clear
);
\c_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_5\,
Q => c_reg(6),
R => clear
);
\c_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_4\,
Q => c_reg(7),
R => clear
);
\c_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_7\,
Q => c_reg(8),
R => clear
);
\c_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[4]_i_1_n_0\,
CO(3) => \c_reg[8]_i_1_n_0\,
CO(2) => \c_reg[8]_i_1_n_1\,
CO(1) => \c_reg[8]_i_1_n_2\,
CO(0) => \c_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[8]_i_1_n_4\,
O(2) => \c_reg[8]_i_1_n_5\,
O(1) => \c_reg[8]_i_1_n_6\,
O(0) => \c_reg[8]_i_1_n_7\,
S(3) => \c[8]_i_2_n_0\,
S(2) => \c[8]_i_3_n_0\,
S(1) => \c[8]_i_4_n_0\,
S(0) => \c[8]_i_5_n_0\
);
\c_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_6\,
Q => c_reg(9),
R => clear
);
signal_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => signal_out_i_2_n_0,
I1 => signal_out_i_3_n_0,
I2 => signal_out_i_4_n_0,
I3 => c_reg(0),
I4 => signal_out_i_5_n_0,
O => signal_out_i_1_n_0
);
signal_out_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(3),
I1 => c_reg(4),
I2 => c_reg(1),
I3 => c_reg(2),
I4 => c_reg(6),
I5 => c_reg(5),
O => signal_out_i_2_n_0
);
signal_out_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(21),
I1 => c_reg(22),
I2 => c_reg(19),
I3 => c_reg(20),
I4 => signal_in,
I5 => c_reg(23),
O => signal_out_i_3_n_0
);
signal_out_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(15),
I1 => c_reg(16),
I2 => c_reg(13),
I3 => c_reg(14),
I4 => c_reg(18),
I5 => c_reg(17),
O => signal_out_i_4_n_0
);
signal_out_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(9),
I1 => c_reg(10),
I2 => c_reg(7),
I3 => c_reg(8),
I4 => c_reg(12),
I5 => c_reg(11),
O => signal_out_i_5_n_0
);
signal_out_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => signal_out_i_1_n_0,
Q => signal_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_debounce_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_debounce_0_0 : entity is "system_debounce_0_0,debounce,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_debounce_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_debounce_0_0 : entity is "debounce,Vivado 2016.4";
end system_debounce_0_0;
architecture STRUCTURE of system_debounce_0_0 is
begin
U0: entity work.system_debounce_0_0_debounce
port map (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/30/14
--Last Modified: 11/2/14
--
--Description: This takes in 16 bit data and displays them on an external display
-- using GPIO and SPI communication.
--
--Version: 1.1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SPI_display is
Generic (constant BoardClockSpeed : integer := 100000000;
constant SCKSpeed : integer := 250000);
Port ( BoardClock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
SCK : out STD_LOGIC;
SS : out STD_LOGIC;
MOSI : out STD_LOGIC
);
end SPI_display;
architecture Behavioral of SPI_display is
signal clkMax : integer := (BoardClockSpeed/SCKSpeed)-1;
signal clkCnt : integer := 0;
signal StateClock : std_logic :='0';
type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,
state10,state11,state12,state13,state14,state15,state16,state17,state18);
signal currentState : state_type :=state0;
signal nextState : state_type;
signal dataSection : std_logic_vector(7 downto 0);
signal byteChoice: integer :=0;
signal byteMax: integer :=8;
begin
ClkEnable : process(BoardClock)
begin
if rising_edge(BoardClock) then
if clkCnt = clkMax then
StateClock <= '1';
clkCnt <= 0;
else
clkCnt<=clkCnt+1;
StateClock <= '0';
end if;
end if;
end process ClkEnable;
StateChange: process (BoardClock,StateClock)
begin
if (rising_edge(BoardClock) and StateClock='1') then
if currentState = state18 then
if byteChoice = byteMax then
byteChoice <= byteChoice-3;
else
byteChoice<=byteChoice+1;
end if;
end if;
currentState <= nextState;
end if;
end process StateChange;
States: process(currentState)
begin
case currentState is
when state0=>
SCK<='0';
SS<='1';
MOSI<='Z';
nextState<=state1;
when state1=>
SCK<='0';
SS<='0';
MOSI<=dataSection(7);
nextState<=state2;
when state2=>
SCK<='1';
SS<='0';
MOSI<=dataSection(7);
nextState<=state3;
when state3=>
SCK<='0';
SS<='0';
MOSI<=dataSection(6);
nextState<=state4;
when state4=>
SCK<='1';
SS<='0';
MOSI<=dataSection(6);
nextState<=state5;
when state5=>
SCK<='0';
SS<='0';
MOSI<=dataSection(5);
nextState<=state6;
when state6=>
SCK<='1';
SS<='0';
MOSI<=dataSection(5);
nextState<=state7;
when state7=>
SCK<='0';
SS<='0';
MOSI<=dataSection(4);
nextState<=state8;
when state8=>
SCK<='1';
SS<='0';
MOSI<=dataSection(4);
nextState<=state9;
when state9=>
SCK<='0';
SS<='0';
MOSI<=dataSection(3);
nextState<=state10;
when state10=>
SCK<='1';
SS<='0';
MOSI<=dataSection(3);
nextState<=state11;
when state11=>
SCK<='0';
SS<='0';
MOSI<=dataSection(2);
nextState<=state12;
when state12=>
SCK<='1';
SS<='0';
MOSI<=dataSection(2);
nextState<=state13;
when state13=>
SCK<='0';
SS<='0';
MOSI<=dataSection(1);
nextState<=state14;
when state14=>
SCK<='1';
SS<='0';
MOSI<=dataSection(1);
nextState<=state15;
when state15=>
SCK<='0';
SS<='0';
MOSI<=dataSection(0);
nextState<=state16;
when state16=>
SCK<='1';
SS<='0';
MOSI<=dataSection(0);
nextState<=state17;
when state17=>
SCK<='0';
SS<='0';
MOSI<=datasection(0);
nextState<=state18;
when state18=>
SCK<='0';
SS<='1';
MOSI<='Z';
nextState<=state1;
end case;
end process States;
ByteSelection: process(byteChoice)
begin
case byteChoice is
when 0 => dataSection<=x"76";
when 1 => dataSection<=x"76";
when 2 => dataSection<=x"76";
when 3 => dataSection<=x"76";
when 4 => dataSection<=x"76";
when 5 => dataSection <=x"0" & Data(15 downto 12);
when 6 => dataSection <=x"0" & Data(11 downto 8);
when 7 => dataSection <=x"0" & Data(7 downto 4);
when 8 => dataSection <=x"0" & Data(3 downto 0);
when others => dataSection <="11111111";
end case;
end process ByteSelection;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: cham_rom_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : cham_rom.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 16384
-- C_READ_DEPTH_A : 16384
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 16384
-- C_READ_DEPTH_B : 16384
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cham_rom_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END cham_rom_prod;
ARCHITECTURE xilinx OF cham_rom_prod IS
COMPONENT cham_rom_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : cham_rom_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
entity issue115 is
end issue115;
architecture behav of issue115 is
signal PC_OUT_bus : BIT_VECTOR (7 DOWNTO 0);
signal tmp : BIT_VECTOR (7 DOWNTO 0);
begin
process
procedure pc_read (signal register_data : out bit_vector(7 downto 0)) is
begin
register_data <= PC_OUT_bus;
end procedure pc_read;
begin
PC_OUT_BUS <= X"ab";
wait for 1 ns;
pc_read(tmp);
wait for 1 ns;
assert tmp = X"ab";
wait;
end process;
end behav;
|
entity issue115 is
end issue115;
architecture behav of issue115 is
signal PC_OUT_bus : BIT_VECTOR (7 DOWNTO 0);
signal tmp : BIT_VECTOR (7 DOWNTO 0);
begin
process
procedure pc_read (signal register_data : out bit_vector(7 downto 0)) is
begin
register_data <= PC_OUT_bus;
end procedure pc_read;
begin
PC_OUT_BUS <= X"ab";
wait for 1 ns;
pc_read(tmp);
wait for 1 ns;
assert tmp = X"ab";
wait;
end process;
end behav;
|
entity issue115 is
end issue115;
architecture behav of issue115 is
signal PC_OUT_bus : BIT_VECTOR (7 DOWNTO 0);
signal tmp : BIT_VECTOR (7 DOWNTO 0);
begin
process
procedure pc_read (signal register_data : out bit_vector(7 downto 0)) is
begin
register_data <= PC_OUT_bus;
end procedure pc_read;
begin
PC_OUT_BUS <= X"ab";
wait for 1 ns;
pc_read(tmp);
wait for 1 ns;
assert tmp = X"ab";
wait;
end process;
end behav;
|
entity issue115 is
end issue115;
architecture behav of issue115 is
signal PC_OUT_bus : BIT_VECTOR (7 DOWNTO 0);
signal tmp : BIT_VECTOR (7 DOWNTO 0);
begin
process
procedure pc_read (signal register_data : out bit_vector(7 downto 0)) is
begin
register_data <= PC_OUT_bus;
end procedure pc_read;
begin
PC_OUT_BUS <= X"ab";
wait for 1 ns;
pc_read(tmp);
wait for 1 ns;
assert tmp = X"ab";
wait;
end process;
end behav;
|
entity issue115 is
end issue115;
architecture behav of issue115 is
signal PC_OUT_bus : BIT_VECTOR (7 DOWNTO 0);
signal tmp : BIT_VECTOR (7 DOWNTO 0);
begin
process
procedure pc_read (signal register_data : out bit_vector(7 downto 0)) is
begin
register_data <= PC_OUT_bus;
end procedure pc_read;
begin
PC_OUT_BUS <= X"ab";
wait for 1 ns;
pc_read(tmp);
wait for 1 ns;
assert tmp = X"ab";
wait;
end process;
end behav;
|
-- $Id: nexys3_fusp_cuff_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived nexys3_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_cuff_dummy is -- NEXYS 3 dummy (+fusp+cuff; loopback)
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys3_fusp_cuff_dummy;
architecture syn of nexys3_fusp_cuff_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
-- Generic comparator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Generic_zero_comparator IS
GENERIC (N : integer := 8);
PORT (
OP : IN std_logic_vector(N-1 downto 0);
EN : IN std_logic;
EQ : OUT std_logic);
END Generic_zero_comparator;
ARCHITECTURE structural OF Generic_zero_comparator IS
SIGNAL equals : std_logic;
BEGIN
equals <= '1' when (OP = (OP'range => '0')) else '0';
EQ <= EN AND equals;
END structural;
|
----------------------------------------------------------------------------
-- Title : Interfacing RHINO with 4DSP-FMC150
----------------------------------------------------------------------------
-- Project : RHINO SDR Processing Blocks
----------------------------------------------------------------------------
--
-- Author : Lekhobola Tsoeunyane
-- Company : University Of Cape Town
-- Email : [email protected]
----------------------------------------------------------------------------
-- Revisions :
----------------------------------------------------------------------------
-- Features
-- 1) SPI configuration of ADS62P49, DAC3283, CDCE72010, ADS4249 and AMC7823
-- 2) LVDS interface to ADS62P49 and DAC3283
-- 2) ADS62P49 auto-calibration
--
-----------------------------------------------------------------------------
-- Library declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity fmc150_if is
port (
--RHINO Resources
sysrst : in std_logic;
clk_100MHz : in std_logic;
mmcm_locked : in std_logic;
clk_61_44MHz : in std_logic;
clk_122_88MHz : in std_logic;
mmcm_adac_locked : in std_logic;
dac_fpga_clk : out std_logic;
-------------- user design interface -----------------------
-- ADC
adc_cha_dout : out std_logic_vector(13 downto 0);
adc_chb_dout : out std_logic_vector(13 downto 0);
-- DAC
dac_chc_din : in std_logic_vector(15 downto 0);
dac_chd_din : in std_logic_vector(15 downto 0);
calibration_ok : out std_logic;
-------------- physical external interface -----------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
clk_ab_p : in std_logic;
clk_ab_n : in std_logic;
cha_p : in std_logic_vector(6 downto 0);
cha_n : in std_logic_vector(6 downto 0);
chb_p : in std_logic_vector(6 downto 0);
chb_n : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga : in std_logic;
ext_trigger : in std_logic;
--Serial Peripheral Interface (SPI)
spi_sclk : out std_logic; -- Shared SPI clock line
spi_sdata : out std_logic; -- Shared SPI sata line
-- ADC specific signals
adc_n_en : out std_logic; -- SPI chip select
adc_sdo : in std_logic; -- SPI data out
adc_reset : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en : out std_logic; -- SPI chip select
cdce_sdo : in std_logic; -- SPI data out
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
-- DAC specific signals
dac_n_en : out std_logic; -- SPI chip select
dac_sdo : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en : out std_logic; -- SPI chip select
mon_sdo : in std_logic; -- SPI data out
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
--FMC Present status
nfmc0_prsnt : in std_logic
-- debug signals
);
end fmc150_if;
architecture rtl of fmc150_if is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
constant CLK_IDELAY : integer := 0; -- Initial number of delay taps on ADC clock input
constant CHA_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port A -- error-free capture range measured between 20 ... 30
constant CHB_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port B -- error-free capture range measured between 20 ... 30
constant MAX_PATTERN_CNT : integer := 600;--16383; -- value of 15000 = approx 1 sec for ramp of length 2^14 samples @ 245.76 MSPS
-- Define the phase increment word for the DDC and DUC blocks (aka NCO)
-- dec2bin(round(Fc/Fs*2^28)), where Fc = -12 MHz, Fs = 61.44 MHz
--constant FREQ_DEFAULT : std_logic_vector(27 downto 0) := x"CE00000";
constant FREQ_DEFAULT : std_logic_vector(27 downto 0) := x"3200000";
component mmcm_adac
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component MMCM
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component fmc150_spi_ctrl is
port (
init_done : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
rst : in std_logic;
clk : in std_logic;
external_clock : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic
);
end component fmc150_spi_ctrl;
component dac3283_serializer is
port(
--System Control Inputs
RST_I : in STD_LOGIC;
--Signal Channel Inputs
DAC_CLK_O : out STD_LOGIC;
DAC_CLK_DIV4_O : out STD_LOGIC;
DAC_READY : out STD_LOGIC;
CH_C_I : in STD_LOGIC_VECTOR(15 downto 0);
CH_D_I : in STD_LOGIC_VECTOR(15 downto 0);
-- DAC interface
FMC150_CLK : in STD_LOGIC;
DAC_DCLK_P : out STD_LOGIC;
DAC_DCLK_N : out STD_LOGIC;
DAC_DATA_P : out STD_LOGIC_VECTOR(7 downto 0);
DAC_DATA_N : out STD_LOGIC_VECTOR(7 downto 0);
FRAME_P : out STD_LOGIC;
FRAME_N : out STD_LOGIC;
-- Testing
IO_TEST_EN : in STD_LOGIC
);
end component dac3283_serializer;
component ADC_auto_calibration is
generic (
MAX_PATTERN_CNT : integer := 1000; -- value of 15000 = approx 1 sec for ramp of length 2^14 samples @ 245.76 MSPS
INIT_IDELAY : integer -- Initial number of delay taps on ADC data port
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ADC_calibration_start : in STD_LOGIC;
ADC_data : in STD_LOGIC_VECTOR (13 downto 0);
re_mux_polarity : out STD_LOGIC;
trace_edge : out STD_LOGIC;
ADC_calibration_state : out STD_LOGIC_VECTOR(2 downto 0);
iDelay_cnt : out STD_LOGIC_VECTOR (4 downto 0);
iDelay_inc_en : out std_logic;
ADC_calibration_done : out BOOLEAN;
ADC_calibration_good : out STD_LOGIC);
end component;
----------------------------------------------------------------------------------------------------
-- Debugging Components and Signals
----------------------------------------------------------------------------------------------------
component icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
component ila0
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component ila1
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
component vio
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal CONTROL1 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal CONTROL2 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal ila_data0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal ila_data1 : STD_LOGIC_VECTOR(127 DOWNTO 0);
signal trig0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal trig1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vio_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Signal declaration
----------------------------------------------------------------------------------------------------
--signal clk_100Mhz : std_logic;
--signal clk_200Mhz : std_logic;
--signal mmcm_locked : std_logic;
signal arst : std_logic := '0';
signal rst : std_logic;
signal rst_duc_ddc : std_logic;
signal clk_ab_l : std_logic;
signal clk_ab_dly : std_logic;
signal clk_ab_i : std_logic;
signal cha_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal cha_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal cha_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal chb_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal chb_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal chb_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_dout_i : std_logic_vector(13 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_dout_q : std_logic_vector(13 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_vout : std_logic;
signal freq : std_logic_vector(27 downto 0);
signal cmplx_aresetn_duc : std_logic;
signal dds_reset_duc : std_logic;
signal cmplx_aresetn_ddc : std_logic;
signal dds_reset_ddc : std_logic;
signal signal_ce : std_logic;
signal signal_ce_prev : std_logic;
signal signal_vout : std_logic;
signal imp_dout_i : std_logic_vector(15 downto 0);
signal imp_dout_q : std_logic_vector(15 downto 0);
signal delay_update : std_logic;
signal clk_cntvaluein : std_logic_vector(4 downto 0);
signal cha_cntvaluein : std_logic_vector(4 downto 0);
signal chb_cntvaluein : std_logic_vector(4 downto 0);
signal clk_cntvalueout : std_logic_vector(4 downto 0);
type cha_cntvalueout_array is array(cha_p'length-1 downto 0) of std_logic_vector(4 downto 0);
signal cha_cntvalueout : cha_cntvalueout_array;
type chb_cntvalueout_array is array(chb_p'length-1 downto 0) of std_logic_vector(4 downto 0);
signal chb_cntvalueout : chb_cntvalueout_array;
signal rd_n_wr : std_logic;
signal addr : std_logic_vector(15 downto 0);
signal idata : std_logic_vector(31 downto 0);
signal odata : std_logic_vector(31 downto 0);
signal busy : std_logic;
signal cdce72010_valid : std_logic;
signal ads62p49_valid : std_logic;
signal dac3283_valid : std_logic;
signal amc7823_valid : std_logic;
--signal clk_66MHz : std_logic;
--signal clk_61_44MHz : std_logic;
signal clk_61_44MHz_n : std_logic;
--signal clk_122_88MHz : std_logic;
--signal clk_368_64MHz : std_logic;
--signal mmcm_adac_locked : std_logic;
signal dac_din_i : std_logic_vector(15 downto 0);
signal dac_din_q : std_logic_vector(15 downto 0);
signal frame : std_logic;
signal io_rst : std_logic;
signal dac_dclk_prebuf : std_logic;
signal dac_data_prebuf : std_logic_vector(7 downto 0);
signal dac_frame_prebuf : std_logic;
signal digital_mode : std_logic;
signal external_clock : std_logic := '0';
signal ADC_cha_calibration_start : std_logic;
signal ADC_chb_calibration_start : std_logic;
signal ADC_cha_calibration_done : boolean;
signal ADC_cha_calibration_done_r : boolean;
signal ADC_cha_calibration_done_rr : boolean;
signal ADC_chb_calibration_done : boolean;
signal ADC_chb_calibration_done_r : boolean;
signal ADC_chb_calibration_done_rr : boolean;
signal ADC_chb_calibration_test_pattern_mode_command_sent : boolean;
signal ADC_cha_calibration_test_pattern_mode_command_sent : boolean;
signal ADC_chb_normal_mode_command_sent : boolean;
signal ADC_cha_normal_mode_command_sent : boolean;
signal ADC_chb_trace_edge : std_logic;
signal ADC_cha_trace_edge : std_logic;
signal ADC_chb_calibration_state : std_logic_vector(2 downto 0);
signal ADC_cha_calibration_state : std_logic_vector(2 downto 0);
signal ADC_chb_calibration_good : std_logic;
signal ADC_cha_calibration_good : std_logic;
signal ADC_calibration_good : std_logic;
signal ADC_chb_ready : boolean;
signal ADC_cha_ready : boolean;
signal ADC_ready : boolean;
signal cha_cntvaluein_update : std_logic_vector(4 downto 0);
signal clk_cntvaluein_update : std_logic_vector(4 downto 0);
signal fmc150_spi_ctrl_done : std_logic;
signal fmc150_spi_ctrl_done_r : std_logic;
signal sysclk : std_logic;
signal busy_reg : std_logic;
signal cha_cntvaluein_update_61_44MHz : std_logic_vector(4 downto 0);
signal cha_cntvaluein_update_100MHz : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update_vio : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update_61_44MHz : std_logic_vector(4 downto 0);
signal chb_cntvaluein_update_100MHz : std_logic_vector(4 downto 0);
signal adc_dout_i_prev : std_logic_vector(13 downto 0);
signal adc_dout_61_44_MSPS_valid : std_logic;
signal clk_61_44MHz_count : std_logic;
signal adc_cha_re_mux_polarity : std_logic := '1'; -- initial state '1' is contrary to actual default behaviour in hardware, but desired for simulation to verify correctness of state machine
signal adc_chb_re_mux_polarity : std_logic := '1'; -- initial state '1' is contrary to actual default behaviour in hardware, but desired for simulation to verify correctness of state machine
signal sclk : std_logic;
signal sclk_n : std_logic;
signal ce_a : std_logic := '0';
signal ce_b : std_logic := '0';
signal cha_inc_update : std_logic;
signal cha_inc_update_100MHz : std_logic;
signal cha_inc_update_61_44MHz : std_logic;
signal cha_incin : std_logic;
signal chb_inc_update : std_logic;
signal chb_inc_update_100MHz : std_logic;
signal chb_inc_update_61_44MHz : std_logic;
signal chb_incin : std_logic;
signal dac_ready : std_logic;
signal txen : std_logic := '0';
signal dac_cnt : std_logic_vector(13 downto 0) := (others => '0');
--signal dac_sample_clk : std_logic;
signal ftw : std_logic_vector(31 downto 0);
----------------------------------------------------------------------------------------------------
-- Begin
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
-- Perform ADC auto calibration
----------------------------------------------------------------------------------
routing_to_SPI: process (arst, clk_100Mhz)
begin
if (arst = '1') then
busy_reg <= '0';
cdce72010_valid <= '0';
ads62p49_valid <= '0';
dac3283_valid <= '0';
amc7823_valid <= '0';
cha_cntvaluein_update_100MHz <= conv_std_logic_vector(CHA_IDELAY, 5);
cha_cntvaluein_update <= conv_std_logic_vector(CHA_IDELAY, 5);
chb_cntvaluein_update_100MHz <= conv_std_logic_vector(CHB_IDELAY, 5);
chb_cntvaluein_update <= conv_std_logic_vector(CHB_IDELAY, 5);
clk_cntvaluein_update <= conv_std_logic_vector(CLK_IDELAY, 5);
ADC_chb_calibration_done_r <= FALSE;
ADC_chb_calibration_done_rr <= FALSE;
ADC_cha_calibration_done_r <= FALSE;
ADC_cha_calibration_done_rr <= FALSE;
ADC_chb_calibration_test_pattern_mode_command_sent <= FALSE;
ADC_cha_calibration_test_pattern_mode_command_sent <= FALSE;
ADC_chb_normal_mode_command_sent <= FALSE;
ADC_cha_normal_mode_command_sent <= FALSE;
ADC_chb_calibration_start <= '0';
ADC_cha_calibration_start <= '0';
fmc150_spi_ctrl_done_r <= '0';
ADC_cha_ready <= FALSE;
ADC_chb_ready <= FALSE;
ADC_ready <= FALSE;
elsif (rising_edge(clk_100Mhz)) then
busy_reg <= busy;
fmc150_spi_ctrl_done_r <= fmc150_spi_ctrl_done;
ADC_chb_calibration_done_r <= ADC_chb_calibration_done; -- double-register to cross from clock domain of 'ADC_auto_calibration'
ADC_chb_calibration_done_rr <= ADC_chb_calibration_done_r; -- where 'ADC_chb_calibration_done' is set
ADC_chb_calibration_done_rr <= TRUE;
ADC_cha_calibration_done_r <= ADC_cha_calibration_done;
ADC_cha_calibration_done_rr <= ADC_cha_calibration_done_r;
-------------------Debugging-------------
--ADC_chb_ready <= TRUE;
-------------------Debugging-------------
if not ADC_chb_ready then
chb_cntvaluein_update_100MHz <= chb_cntvaluein_update_61_44MHz;
chb_cntvaluein_update <= chb_cntvaluein_update_100MHz;
chb_inc_update_100MHz <= chb_inc_update_61_44MHz;
chb_inc_update <= chb_inc_update_100MHz;
if not ADC_chb_calibration_done_rr then
if not ADC_chb_calibration_test_pattern_mode_command_sent then
if (fmc150_spi_ctrl_done = '1' and fmc150_spi_ctrl_done_r = '0') then -- rising edge of 'fmc150_spi_ctrl_done' indicates reset-time
-- initialization of FMC150 SPI devices has completed
addr <= x"0075";
idata <= x"00000004"; -- send SPI command to ads62p49 for test-mode / ramp pattern on Ch B
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_chb_calibration_test_pattern_mode_command_sent <= TRUE;
else
ads62p49_valid <= ads62p49_valid;
ADC_chb_calibration_test_pattern_mode_command_sent <= FALSE;
end if;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 for test-mode
ADC_chb_calibration_start <= '1'; -- ... ADC auto-calibration state-machine 'ADC_auto_calibration' is awaiting this event to start
else
ADC_chb_calibration_start <= '0';
end if;
end if;
else
if not ADC_chb_normal_mode_command_sent then
addr <= x"0075";
idata <= x"00000000"; -- send SPI command to ads62p49 for normal capture mode
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_chb_normal_mode_command_sent <= TRUE;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 to resume normal capture mode after ADC calibration sequence
ADC_chb_ready <= TRUE; -- ADC auto-calibration is done and ADS62P49 is now in normal capture mode ... allow RX FIFO to read
else
ADC_chb_ready <= FALSE;
end if;
end if;
end if;
elsif not ADC_cha_ready then
cha_cntvaluein_update_100MHz <= cha_cntvaluein_update_61_44MHz;
cha_cntvaluein_update <= cha_cntvaluein_update_100MHz;
cha_inc_update_100MHz <= cha_inc_update_61_44MHz;
cha_inc_update <= cha_inc_update_100MHz;
if not ADC_cha_calibration_done_rr then
if not ADC_cha_calibration_test_pattern_mode_command_sent then
addr <= x"0062";
idata <= x"00000004"; -- send SPI command to ads62p49 for test-mode / ramp pattern on Ch A
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_cha_calibration_test_pattern_mode_command_sent <= TRUE;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 for test-mode
ADC_cha_calibration_start <= '1'; -- ... ADC auto-calibration state-machine 'ADC_auto_calibration' is awaiting this event to start
else
ADC_cha_calibration_start <= '0';
end if;
end if;
else
if not ADC_cha_normal_mode_command_sent then
addr <= x"0062";
idata <= x"00000000"; -- send SPI command to ads62p49 for normal capture mode
rd_n_wr <= '0';
ads62p49_valid <= not ads62p49_valid; -- toggle triggers transaction with SPI device on FMC150
ADC_cha_normal_mode_command_sent <= TRUE;
else
if (busy = '0' and busy_reg = '1') then -- wait for falling edge of 'busy' indicating SPI port has sent command to ADS62P49 to resume normal capture mode after ADC calibration sequence
ADC_cha_ready <= TRUE; -- ADC auto-calibration is done and ADS62P49 is now in normal capture mode
ADC_ready <= TRUE; -- allow RX FIFO to read
else
ADC_cha_ready <= FALSE;
ADC_ready <= FALSE;
end if;
end if;
end if;
end if;
end if;
end process routing_to_SPI;
calibration_ok <= '1' when ADC_cha_calibration_done_r and ADC_chb_calibration_done_r else
'0';
----------------------------------------------------------------------------------
-- Update iDelay values for incoming ADC data, clock
----------------------------------------------------------------------------------
iDelay_update: process (arst, clk_100Mhz)
begin
if (arst = '1') then
delay_update <= '1';
clk_cntvaluein <= conv_std_logic_vector(CLK_IDELAY, 5);
cha_cntvaluein <= conv_std_logic_vector(CHA_IDELAY, 5);
chb_cntvaluein <= conv_std_logic_vector(CHB_IDELAY, 5);
cha_incin <= '0';
chb_incin <= '0';
elsif (rising_edge(clk_100Mhz)) then
-- Generate an delay_update pulse in case one of the cntvaluein values has changed
if (cha_cntvaluein /= cha_cntvaluein_update) then
delay_update <= '1';
clk_cntvaluein <= clk_cntvaluein;
chb_cntvaluein <= chb_cntvaluein;
cha_cntvaluein <= cha_cntvaluein_update;
chb_incin <= '0';
cha_incin <= cha_inc_update;
elsif (chb_cntvaluein /= chb_cntvaluein_update) then
delay_update <= '1';
clk_cntvaluein <= clk_cntvaluein;
chb_cntvaluein <= chb_cntvaluein_update;
cha_cntvaluein <= cha_cntvaluein;
chb_incin <= chb_inc_update;
cha_incin <= '0';
elsif (clk_cntvaluein /= clk_cntvaluein_update) then
delay_update <= '1';
clk_cntvaluein <= clk_cntvaluein_update;
chb_cntvaluein <= chb_cntvaluein;
cha_cntvaluein <= cha_cntvaluein;
chb_incin <= '0';
cha_incin <= '0';
else
delay_update <= '0';
clk_cntvaluein <= clk_cntvaluein;
chb_cntvaluein <= chb_cntvaluein;
cha_cntvaluein <= cha_cntvaluein;
chb_incin <= '0';
cha_incin <= '0';
end if;
end if;
end process iDelay_update;
----------------------------------------------------------------------------------
-- ADC calibration Channel B
----------------------------------------------------------------------------------
ADC_auto_calibration_chB: ADC_auto_calibration
generic map(
MAX_PATTERN_CNT => MAX_PATTERN_CNT,
INIT_IDELAY => CHB_IDELAY
)
Port map(
reset => arst,
clk => clk_61_44Mhz,
ADC_calibration_start => ADC_chb_calibration_start,
ADC_data => adc_dout_q,
re_mux_polarity => adc_chb_re_mux_polarity,
trace_edge => ADC_chb_trace_edge,
ADC_calibration_state => ADC_chb_calibration_state,
iDelay_cnt => chb_cntvaluein_update_61_44MHz,
iDelay_inc_en => chb_inc_update_61_44MHz,
ADC_calibration_done => ADC_chb_calibration_done,
ADC_calibration_good => ADC_chb_calibration_good);
----------------------------------------------------------------------------------
-- ADC calibration Channel A
----------------------------------------------------------------------------------
ADC_auto_calibration_chA: ADC_auto_calibration
generic map(
MAX_PATTERN_CNT => MAX_PATTERN_CNT,
INIT_IDELAY => CHA_IDELAY
)
Port map(
reset => arst,
clk => clk_61_44Mhz,
ADC_calibration_start => ADC_cha_calibration_start,
ADC_data => adc_dout_i,
re_mux_polarity => adc_cha_re_mux_polarity,
trace_edge => ADC_cha_trace_edge,
ADC_calibration_state => ADC_cha_calibration_state,
iDelay_cnt => cha_cntvaluein_update_61_44MHz,
iDelay_inc_en => cha_inc_update_61_44MHz,
ADC_calibration_done => ADC_cha_calibration_done,
ADC_calibration_good => ADC_cha_calibration_good);
ADC_calibration_good <= ADC_chb_calibration_good AND ADC_cha_calibration_good;
----------------------------------------------------------------------------------------------------
-- IDELAY Control
----------------------------------------------------------------------------------------------------
ce_a <= cha_incin;
ce_b <= chb_incin;
arst <= vio_data(0) or not mmcm_locked;
--arst <= vio_data(0);
clk_61_44MHz_n <= not clk_61_44MHz;
----------------------------------------------------------------------------------------------------
-- Reset sequence
----------------------------------------------------------------------------------------------------
process (mmcm_adac_locked, clk_61_44MHz)
variable cnt : integer range 0 to 1023 := 0;
begin
if (mmcm_adac_locked = '0') then
rst <= '1';
io_rst <= '0';
frame <= '0';
txenable <= '0';
elsif (rising_edge(clk_61_44MHz)) then
-- Finally the TX enable for the DAC can by pulled high.
-- DDC and DUC are kept in reset state for a while...
if (cnt < 1023) then
cnt := cnt + 1;
rst <= '1';
else
cnt := cnt;
rst <= '0';
end if;
-- The OSERDES blocks are synchronously reset for one clock cycle...
if (cnt = 255) then
io_rst <= '1';
else
io_rst <= '0';
end if;
if (cnt = 1023) then
txenable <= '1';
txen <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Channel A data from ADC
----------------------------------------------------------------------------------------------------
adc_data_a: for i in 0 to 6 generate
-- Differantial input buffer with termination (LVDS)
ibufds_inst : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => cha_p(i),
ib => cha_n(i),
o => cha_ddr(i)
);
-- Input delay
iodelay_inst : iodelay2
generic map (
DATA_RATE => "DDR",
IDELAY_VALUE => CHA_IDELAY,
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
COUNTER_WRAPAROUND => "STAY_AT_LIMIT",
DELAY_SRC => "IDATAIN",
SERDES_MODE => "NONE",
SIM_TAPDELAY_VALUE => 75
)
port map (
idatain => cha_ddr(i),
dataout => cha_ddr_dly(i),
t => '1',
odatain => '0',
ioclk0 => clk_61_44MHz,
ioclk1 => clk_61_44MHz_n,
clk => clk_61_44MHz,
cal => '0',
inc => cha_incin,
ce => ce_a,
busy => open,
rst => sysrst
);
-- DDR to SDR
iddr_inst_cha : IDDR2
generic map (
-- DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
DDR_ALIGNMENT => "NONE",
INIT_Q0 => '0',
INIT_Q1 => '0',
SRTYPE => "SYNC")
port map (
q0 => cha_sdr(2*i),
q1 => cha_sdr(2*i+1),
c0 => clk_61_44MHz,
c1 => clk_61_44MHz_n,
ce => '1',
d => cha_ddr_dly(i), --cha_ddr_dly
r => sysrst,
s => '0'
);
end generate;
----------------------------------------------------------------------------------------------------
-- Channel B data from ADC
----------------------------------------------------------------------------------------------------
adc_data_b: for i in 0 to 6 generate
-- Differantial input buffer with termination (LVDS)
ibufds_inst : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => chb_p(i),
ib => chb_n(i),
o => chb_ddr(i)
);
-- Input delay
iodelay_inst : iodelay2
generic map (
DATA_RATE => "DDR",
IDELAY_VALUE => CHB_IDELAY,
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
COUNTER_WRAPAROUND => "STAY_AT_LIMIT",
DELAY_SRC => "IDATAIN",
SERDES_MODE => "NONE",
SIM_TAPDELAY_VALUE => 75
)
port map (
idatain => chb_ddr(i),
dataout => chb_ddr_dly(i),
t => '1',
odatain => '0',
ioclk0 => clk_61_44MHz,
ioclk1 => clk_61_44MHz_n,
clk => clk_61_44MHz,
cal => '0',
inc => chb_incin,
ce => ce_b,
busy => open,
rst => sysrst
);
-- DDR to SDR
iddr_inst_chb : IDDR2
generic map (
-- DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
DDR_ALIGNMENT => "NONE",
INIT_Q0 => '0',
INIT_Q1 => '0',
SRTYPE => "SYNC")
port map (
q0 => chb_sdr(2*i),
q1 => chb_sdr(2*i+1),
c0 => clk_61_44MHz,
c1 => clk_61_44MHz_n,
ce => '1',
d => chb_ddr_dly(i), --chb_ddr_dly
r => sysrst,
s => '0'
);
end generate;
----------------------------------------------------------------------------------------------------
-- Ouput 16-bit digital samples
----------------------------------------------------------------------------------------------------
process (clk_61_44MHz)
begin
if (rising_edge(clk_61_44MHz)) then
adc_cha_dout <= cha_sdr;
adc_chb_dout <= chb_sdr;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Output MUX - Select data connected to the physical DAC interface
----------------------------------------------------------------------------------------------------
process (clk_61_44MHz)
begin
if (rising_edge(clk_61_44MHz)) then
dac_cnt <= dac_cnt + 1024;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Output serdes and LVDS buffer for DAC clock
----------------------------------------------------------------------------------------------------
dac : dac3283_serializer
port map(
RST_I => sysrst,
DAC_CLK_O => dac_fpga_clk,
DAC_CLK_DIV4_O => open,
DAC_READY => dac_ready,
CH_C_I => dac_chc_din,
CH_D_I => dac_chd_din,
FMC150_CLK => clk_to_fpga,
DAC_DCLK_P => dac_dclk_p,
DAC_DCLK_N => dac_dclk_n,
DAC_DATA_P => dac_data_p,
DAC_DATA_N => dac_data_n,
FRAME_P => dac_frame_p,
FRAME_N => dac_frame_n,
IO_TEST_EN => '0'
);
----------------------------------------------------------------------------------------------------
-- Configuring the FMC150 card
----------------------------------------------------------------------------------------------------
-- the fmc150_spi_ctrl component configures the devices on the FMC150 card through the Serial
-- Peripheral Interfaces (SPI) and some additional direct control signals.
----------------------------------------------------------------------------------------------------
fmc150_spi_ctrl_inst : fmc150_spi_ctrl
port map (
init_done => fmc150_spi_ctrl_done,
rd_n_wr => rd_n_wr,
addr => addr,
idata => idata,
odata => odata,
busy => busy,
cdce72010_valid => cdce72010_valid,
ads62p49_valid => ads62p49_valid,
dac3283_valid => dac3283_valid,
amc7823_valid => amc7823_valid,
rst => arst,
clk => clk_100MHz,
external_clock => external_clock,
spi_sclk => sclk,
spi_sdata => spi_sdata,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
prsnt_m2c_l => nfmc0_prsnt
);
-- ODDR2 is needed instead of the following
-- and limiting in Spartan 6
txclk_ODDR2_inst : ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => spi_sclk, -- 1-bit DDR output data
C0 => sclk, -- clock is your signal from PLL
C1 => sclk_n, -- n
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => sysrst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
sclk_n <= not sclk;
-------------------------------------------END------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Debugging Section
----------------------------------------------------------------------------------------------------
-- ila_data0(0) <= fmc150_spi_ctrl_done;
-- ila_data0(1) <= external_clock;
-- ila_data0(2) <= busy;
-- ila_data0(3) <= mmcm_adac_locked;
-- ila_data0(4) <= mmcm_locked;
-- ila_data0(5) <= pll_status;
-- ila_data0(6) <= '1' when ADC_cha_ready = TRUE else '0';
-- ila_data0(7) <= '1' when ADC_chb_ready = TRUE else '0';
-- ila_data0(8) <= txen;
-- ila_data1(13 downto 0) <= adc_dout_i;
-- ila_data1(27 downto 14)<= adc_dout_q;
-- ila_data1(41 downto 28) <= dac_cnt;
-- ila_data1(44 downto 42) <= ADC_chb_calibration_state;
-- ila_data1(49 downto 45) <= cha_cntvaluein;
-- ila_data1(50) <= ADC_calibration_good;
--trig0(0) <= busy;--cmd_state(3 downto 0);--busy;--init_done;
-- trig1(2 downto 0) <= ADC_chb_calibration_state;
------ instantiate chipscope components -------
-- icon_inst : icon
-- port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2
-- );
-- ila_data0_inst : ila0
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_100MHz,--clk_245_76MHz,
-- DATA => ila_data0,
-- TRIG0 => TRIG0);
-- ila_data1_inst : ila1
-- port map (
-- CONTROL => CONTROL2,
-- CLK => clk_61_44MHz,
-- DATA => ila_data1,
-- TRIG0 => TRIG1);
-- vio_inst : vio
-- port map (
-- CONTROL => CONTROL1,
-- ASYNC_OUT => vio_data);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1023.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n02i01023ent IS
END c06s03b00x00p10n02i01023ent;
ARCHITECTURE c06s03b00x00p10n02i01023arch OF c06s03b00x00p10n02i01023ent IS
BEGIN
TESTING: PROCESS
variable j : integer;
BEGIN
L1: for i in 1 to 10 loop
e.j := L1.i;
end loop;
j := L1.i; -- illegal as reference to L1.i is allowed within the
-- loop L1 only.
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01023 - An expanded name denoting an entity declared within a named construct is allowed only within the construct."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n02i01023arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1023.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n02i01023ent IS
END c06s03b00x00p10n02i01023ent;
ARCHITECTURE c06s03b00x00p10n02i01023arch OF c06s03b00x00p10n02i01023ent IS
BEGIN
TESTING: PROCESS
variable j : integer;
BEGIN
L1: for i in 1 to 10 loop
e.j := L1.i;
end loop;
j := L1.i; -- illegal as reference to L1.i is allowed within the
-- loop L1 only.
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01023 - An expanded name denoting an entity declared within a named construct is allowed only within the construct."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n02i01023arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1023.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n02i01023ent IS
END c06s03b00x00p10n02i01023ent;
ARCHITECTURE c06s03b00x00p10n02i01023arch OF c06s03b00x00p10n02i01023ent IS
BEGIN
TESTING: PROCESS
variable j : integer;
BEGIN
L1: for i in 1 to 10 loop
e.j := L1.i;
end loop;
j := L1.i; -- illegal as reference to L1.i is allowed within the
-- loop L1 only.
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01023 - An expanded name denoting an entity declared within a named construct is allowed only within the construct."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n02i01023arch;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 10:38:54 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_funcsim.vhdl
-- Design : scfifo_32in_32out_1kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_dmem : entity is "dmem";
end scfifo_32in_32out_1kb_dmem;
architecture STRUCTURE of scfifo_32in_32out_1kb_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_30_31: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_bin_cntr is
port (
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]_0\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_32in_32out_1kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_bin_cntr is
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair4";
begin
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCC8888CCCC8888"
)
port map (
I0 => ram_full_i_i_4_n_0,
I1 => p_18_out,
I2 => ram_empty_fb_i_i_2_n_0,
I3 => \gpregsm1.curr_fwft_state_reg[0]\,
I4 => ram_full_fb_i_reg,
I5 => ram_empty_fb_i_i_5_n_0,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \gcc0.gc0.count_d1_reg[4]\(1),
I2 => \gcc0.gc0.count_d1_reg[4]\(0),
I3 => rd_pntr_plus1(0),
I4 => \gcc0.gc0.count_d1_reg[4]\(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
O => ram_empty_fb_i_i_5_n_0
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFA8A8FFA8A8A8A8"
)
port map (
I0 => ram_full_fb_i_reg_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]_0\,
I2 => ram_full_i_i_4_n_0,
I3 => \^gpr1.dout_i_reg[1]\(0),
I4 => \gcc0.gc0.count_reg[2]\(0),
I5 => ram_full_i_i_5_n_0,
O => ram_full_comb
);
ram_full_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_full_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(2),
I1 => \gcc0.gc0.count_reg[2]\(2),
I2 => \^gpr1.dout_i_reg[1]\(1),
I3 => \gcc0.gc0.count_reg[2]\(1),
I4 => ram_empty_fb_i_reg_0,
I5 => \gcc0.gc0.count_reg[3]\,
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_full_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_fwft is
port (
empty : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_fwft : entity is "rd_fwft";
end scfifo_32in_32out_1kb_rd_fwft;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair2";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[31]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gpr1.dout_i[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_full_i_i_3 : label is "soft_lutpair1";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gc0.count_d1_reg[4]\(0)
);
\goreg_dm.dout_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => E(0)
);
\gpr1.dout_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gpr1.dout_i_reg[0]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => ram_empty_fb_i_reg
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I2 => rd_en,
I3 => p_18_out,
O => ram_full_i_reg_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I3 => curr_fwft_state(0),
I4 => wr_en,
I5 => p_1_out,
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_status_flags_ss is
port (
p_18_out : out STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_32in_32out_1kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_32in_32out_1kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_32in_32out_1kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 3 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair7";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => p_9_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_9_out(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => p_9_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gpr1.dout_i_reg[1]\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gpr1.dout_i_reg[1]\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gpr1.dout_i_reg[1]\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(3),
Q => \gpr1.dout_i_reg[1]\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(4),
Q => \gpr1.dout_i_reg[1]\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_9_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_9_out(4)
);
ram_full_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_9_out(3),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_9_out(4),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_status_flags_ss is
port (
\gcc0.gc0.count_reg[4]\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_32in_32out_1kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_status_flags_ss is
signal \^gcc0.gc0.count_reg[4]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair6";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair6";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gcc0.gc0.count_reg[4]\ <= \^gcc0.gc0.count_reg[4]\;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^gcc0.gc0.count_reg[4]\,
O => E(0)
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^gcc0.gc0.count_reg[4]\
);
ram_full_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => rst_full_gen_i,
O => ram_full_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_memory : entity is "memory";
end scfifo_32in_32out_1kb_memory;
architecture STRUCTURE of scfifo_32in_32out_1kb_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
\gdm.dm\: entity work.scfifo_32in_32out_1kb_dmem
port map (
E(0) => E(0),
Q(31 downto 0) => p_0_out(31 downto 0),
clk => clk,
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => Q(0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_logic is
port (
empty : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_logic : entity is "rd_logic";
end scfifo_32in_32out_1kb_rd_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_logic is
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_5\ : STD_LOGIC;
signal \gr1.rfwft_n_6\ : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_5 : STD_LOGIC;
begin
\gr1.rfwft\: entity work.scfifo_32in_32out_1kb_rd_fwft
port map (
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[4]\(0) => p_14_out,
\gpr1.dout_i_reg[0]\(0) => \gpr1.dout_i_reg[0]\(0),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gr1.rfwft_n_5\,
ram_full_i_reg => \gr1.rfwft_n_1\,
ram_full_i_reg_0 => \gr1.rfwft_n_6\,
rd_en => rd_en,
wr_en => wr_en
);
\grss.rsts\: entity work.scfifo_32in_32out_1kb_rd_status_flags_ss
port map (
Q(0) => Q(0),
clk => clk,
p_18_out => p_18_out,
ram_empty_fb_i_reg_0 => rpntr_n_5
);
rpntr: entity work.scfifo_32in_32out_1kb_rd_bin_cntr
port map (
E(0) => p_14_out,
Q(0) => Q(0),
clk => clk,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => \gcc0.gc0.count_reg[2]\(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gcc0.gc0.count_reg[3]\,
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.rfwft_n_5\,
\gpregsm1.curr_fwft_state_reg[0]_0\ => \gr1.rfwft_n_6\,
p_18_out => p_18_out,
ram_empty_fb_i_reg => rpntr_n_5,
ram_empty_fb_i_reg_0 => \gr1.rfwft_n_1\,
ram_full_comb => ram_full_comb,
ram_full_fb_i_reg => ram_full_fb_i_reg,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_logic is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_logic : entity is "wr_logic";
end scfifo_32in_32out_1kb_wr_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.scfifo_32in_32out_1kb_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\gcc0.gc0.count_reg[4]\ => p_1_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
ram_full_i_reg_0 => ram_full_i_reg_0,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
wpntr: entity work.scfifo_32in_32out_1kb_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gc0.count_d1_reg[4]\(1 downto 0) => \gc0.count_d1_reg[4]\(1 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
ram_full_i_reg => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_32in_32out_1kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_10_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal rstblk_n_4 : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_32in_32out_1kb_rd_logic
port map (
E(0) => p_15_out,
Q(0) => RD_RST,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => p_9_out(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\gpr1.dout_i_reg[0]\(0) => ram_rd_en_i,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_20_out(4 downto 0),
p_1_out => p_1_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_32in_32out_1kb_wr_logic
port map (
AR(0) => \^rst\,
E(0) => p_4_out,
Q(2 downto 0) => p_9_out(2 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[4]\(1 downto 0) => p_20_out(4 downto 3),
\gpr1.dout_i_reg[1]\(4 downto 0) => p_10_out(4 downto 0),
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_32in_32out_1kb_memory
port map (
E(0) => ram_rd_en_i,
Q(0) => rstblk_n_4,
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_15_out,
ram_full_fb_i_reg(0) => p_4_out
);
rstblk: entity work.scfifo_32in_32out_1kb_reset_blk_ramfifo
port map (
AR(0) => \^rst\,
Q(1) => RD_RST,
Q(0) => rstblk_n_4,
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_32in_32out_1kb_fifo_generator_top;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_ramfifo
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end scfifo_32in_32out_1kb_fifo_generator_v12_0_synth;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_top
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end scfifo_32in_32out_1kb_fifo_generator_v12_0;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0_synth
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_32in_32out_1kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_32in_32out_1kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_32in_32out_1kb : entity is "fifo_generator_v12_0,Vivado 2015.1";
end scfifo_32in_32out_1kb;
architecture STRUCTURE of scfifo_32in_32out_1kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 10:38:54 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_funcsim.vhdl
-- Design : scfifo_32in_32out_1kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_dmem : entity is "dmem";
end scfifo_32in_32out_1kb_dmem;
architecture STRUCTURE of scfifo_32in_32out_1kb_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_30_31: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_bin_cntr is
port (
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]_0\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_32in_32out_1kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_bin_cntr is
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair4";
begin
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCC8888CCCC8888"
)
port map (
I0 => ram_full_i_i_4_n_0,
I1 => p_18_out,
I2 => ram_empty_fb_i_i_2_n_0,
I3 => \gpregsm1.curr_fwft_state_reg[0]\,
I4 => ram_full_fb_i_reg,
I5 => ram_empty_fb_i_i_5_n_0,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \gcc0.gc0.count_d1_reg[4]\(1),
I2 => \gcc0.gc0.count_d1_reg[4]\(0),
I3 => rd_pntr_plus1(0),
I4 => \gcc0.gc0.count_d1_reg[4]\(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
O => ram_empty_fb_i_i_5_n_0
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFA8A8FFA8A8A8A8"
)
port map (
I0 => ram_full_fb_i_reg_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]_0\,
I2 => ram_full_i_i_4_n_0,
I3 => \^gpr1.dout_i_reg[1]\(0),
I4 => \gcc0.gc0.count_reg[2]\(0),
I5 => ram_full_i_i_5_n_0,
O => ram_full_comb
);
ram_full_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_full_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(2),
I1 => \gcc0.gc0.count_reg[2]\(2),
I2 => \^gpr1.dout_i_reg[1]\(1),
I3 => \gcc0.gc0.count_reg[2]\(1),
I4 => ram_empty_fb_i_reg_0,
I5 => \gcc0.gc0.count_reg[3]\,
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_full_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_fwft is
port (
empty : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_fwft : entity is "rd_fwft";
end scfifo_32in_32out_1kb_rd_fwft;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair2";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[31]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gpr1.dout_i[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_full_i_i_3 : label is "soft_lutpair1";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gc0.count_d1_reg[4]\(0)
);
\goreg_dm.dout_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => E(0)
);
\gpr1.dout_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gpr1.dout_i_reg[0]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => ram_empty_fb_i_reg
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I2 => rd_en,
I3 => p_18_out,
O => ram_full_i_reg_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I3 => curr_fwft_state(0),
I4 => wr_en,
I5 => p_1_out,
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_status_flags_ss is
port (
p_18_out : out STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_32in_32out_1kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_32in_32out_1kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_32in_32out_1kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 3 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair7";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => p_9_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_9_out(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => p_9_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gpr1.dout_i_reg[1]\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gpr1.dout_i_reg[1]\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gpr1.dout_i_reg[1]\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(3),
Q => \gpr1.dout_i_reg[1]\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(4),
Q => \gpr1.dout_i_reg[1]\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_9_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_9_out(4)
);
ram_full_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_9_out(3),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_9_out(4),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_status_flags_ss is
port (
\gcc0.gc0.count_reg[4]\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_32in_32out_1kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_status_flags_ss is
signal \^gcc0.gc0.count_reg[4]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair6";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair6";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gcc0.gc0.count_reg[4]\ <= \^gcc0.gc0.count_reg[4]\;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^gcc0.gc0.count_reg[4]\,
O => E(0)
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^gcc0.gc0.count_reg[4]\
);
ram_full_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => rst_full_gen_i,
O => ram_full_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_memory : entity is "memory";
end scfifo_32in_32out_1kb_memory;
architecture STRUCTURE of scfifo_32in_32out_1kb_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
\gdm.dm\: entity work.scfifo_32in_32out_1kb_dmem
port map (
E(0) => E(0),
Q(31 downto 0) => p_0_out(31 downto 0),
clk => clk,
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => Q(0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_logic is
port (
empty : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_logic : entity is "rd_logic";
end scfifo_32in_32out_1kb_rd_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_logic is
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_5\ : STD_LOGIC;
signal \gr1.rfwft_n_6\ : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_5 : STD_LOGIC;
begin
\gr1.rfwft\: entity work.scfifo_32in_32out_1kb_rd_fwft
port map (
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[4]\(0) => p_14_out,
\gpr1.dout_i_reg[0]\(0) => \gpr1.dout_i_reg[0]\(0),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gr1.rfwft_n_5\,
ram_full_i_reg => \gr1.rfwft_n_1\,
ram_full_i_reg_0 => \gr1.rfwft_n_6\,
rd_en => rd_en,
wr_en => wr_en
);
\grss.rsts\: entity work.scfifo_32in_32out_1kb_rd_status_flags_ss
port map (
Q(0) => Q(0),
clk => clk,
p_18_out => p_18_out,
ram_empty_fb_i_reg_0 => rpntr_n_5
);
rpntr: entity work.scfifo_32in_32out_1kb_rd_bin_cntr
port map (
E(0) => p_14_out,
Q(0) => Q(0),
clk => clk,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => \gcc0.gc0.count_reg[2]\(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gcc0.gc0.count_reg[3]\,
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.rfwft_n_5\,
\gpregsm1.curr_fwft_state_reg[0]_0\ => \gr1.rfwft_n_6\,
p_18_out => p_18_out,
ram_empty_fb_i_reg => rpntr_n_5,
ram_empty_fb_i_reg_0 => \gr1.rfwft_n_1\,
ram_full_comb => ram_full_comb,
ram_full_fb_i_reg => ram_full_fb_i_reg,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_logic is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_logic : entity is "wr_logic";
end scfifo_32in_32out_1kb_wr_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.scfifo_32in_32out_1kb_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\gcc0.gc0.count_reg[4]\ => p_1_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
ram_full_i_reg_0 => ram_full_i_reg_0,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
wpntr: entity work.scfifo_32in_32out_1kb_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gc0.count_d1_reg[4]\(1 downto 0) => \gc0.count_d1_reg[4]\(1 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
ram_full_i_reg => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_32in_32out_1kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_10_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal rstblk_n_4 : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_32in_32out_1kb_rd_logic
port map (
E(0) => p_15_out,
Q(0) => RD_RST,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => p_9_out(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\gpr1.dout_i_reg[0]\(0) => ram_rd_en_i,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_20_out(4 downto 0),
p_1_out => p_1_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_32in_32out_1kb_wr_logic
port map (
AR(0) => \^rst\,
E(0) => p_4_out,
Q(2 downto 0) => p_9_out(2 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[4]\(1 downto 0) => p_20_out(4 downto 3),
\gpr1.dout_i_reg[1]\(4 downto 0) => p_10_out(4 downto 0),
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_32in_32out_1kb_memory
port map (
E(0) => ram_rd_en_i,
Q(0) => rstblk_n_4,
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_15_out,
ram_full_fb_i_reg(0) => p_4_out
);
rstblk: entity work.scfifo_32in_32out_1kb_reset_blk_ramfifo
port map (
AR(0) => \^rst\,
Q(1) => RD_RST,
Q(0) => rstblk_n_4,
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_32in_32out_1kb_fifo_generator_top;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_ramfifo
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end scfifo_32in_32out_1kb_fifo_generator_v12_0_synth;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_top
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end scfifo_32in_32out_1kb_fifo_generator_v12_0;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0_synth
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_32in_32out_1kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_32in_32out_1kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_32in_32out_1kb : entity is "fifo_generator_v12_0,Vivado 2015.1";
end scfifo_32in_32out_1kb;
architecture STRUCTURE of scfifo_32in_32out_1kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 10:38:54 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_funcsim.vhdl
-- Design : scfifo_32in_32out_1kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_dmem : entity is "dmem";
end scfifo_32in_32out_1kb_dmem;
architecture STRUCTURE of scfifo_32in_32out_1kb_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_30_31: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_31_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_bin_cntr is
port (
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]_0\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_32in_32out_1kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_bin_cntr is
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair4";
begin
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCC8888CCCC8888"
)
port map (
I0 => ram_full_i_i_4_n_0,
I1 => p_18_out,
I2 => ram_empty_fb_i_i_2_n_0,
I3 => \gpregsm1.curr_fwft_state_reg[0]\,
I4 => ram_full_fb_i_reg,
I5 => ram_empty_fb_i_i_5_n_0,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \gcc0.gc0.count_d1_reg[4]\(1),
I2 => \gcc0.gc0.count_d1_reg[4]\(0),
I3 => rd_pntr_plus1(0),
I4 => \gcc0.gc0.count_d1_reg[4]\(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
O => ram_empty_fb_i_i_5_n_0
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFA8A8FFA8A8A8A8"
)
port map (
I0 => ram_full_fb_i_reg_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]_0\,
I2 => ram_full_i_i_4_n_0,
I3 => \^gpr1.dout_i_reg[1]\(0),
I4 => \gcc0.gc0.count_reg[2]\(0),
I5 => ram_full_i_i_5_n_0,
O => ram_full_comb
);
ram_full_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_full_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(2),
I1 => \gcc0.gc0.count_reg[2]\(2),
I2 => \^gpr1.dout_i_reg[1]\(1),
I3 => \gcc0.gc0.count_reg[2]\(1),
I4 => ram_empty_fb_i_reg_0,
I5 => \gcc0.gc0.count_reg[3]\,
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_full_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_fwft is
port (
empty : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_fwft : entity is "rd_fwft";
end scfifo_32in_32out_1kb_rd_fwft;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair2";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[31]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gpr1.dout_i[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_full_i_i_3 : label is "soft_lutpair1";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gc0.count_d1_reg[4]\(0)
);
\goreg_dm.dout_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => E(0)
);
\gpr1.dout_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => \gpr1.dout_i_reg[0]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => ram_empty_fb_i_reg
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I2 => rd_en,
I3 => p_18_out,
O => ram_full_i_reg_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I3 => curr_fwft_state(0),
I4 => wr_en,
I5 => p_1_out,
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_status_flags_ss is
port (
p_18_out : out STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_32in_32out_1kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_32in_32out_1kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_32in_32out_1kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 3 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair7";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => p_9_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_9_out(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => p_9_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gpr1.dout_i_reg[1]\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gpr1.dout_i_reg[1]\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gpr1.dout_i_reg[1]\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(3),
Q => \gpr1.dout_i_reg[1]\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_9_out(4),
Q => \gpr1.dout_i_reg[1]\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_9_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_9_out(4)
);
ram_full_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_9_out(3),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_9_out(4),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_status_flags_ss is
port (
\gcc0.gc0.count_reg[4]\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_32in_32out_1kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_status_flags_ss is
signal \^gcc0.gc0.count_reg[4]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair6";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair6";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gcc0.gc0.count_reg[4]\ <= \^gcc0.gc0.count_reg[4]\;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^gcc0.gc0.count_reg[4]\,
O => E(0)
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^gcc0.gc0.count_reg[4]\
);
ram_full_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gcc0.gc0.count_reg[4]\,
I1 => rst_full_gen_i,
O => ram_full_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_memory : entity is "memory";
end scfifo_32in_32out_1kb_memory;
architecture STRUCTURE of scfifo_32in_32out_1kb_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
\gdm.dm\: entity work.scfifo_32in_32out_1kb_dmem
port map (
E(0) => E(0),
Q(31 downto 0) => p_0_out(31 downto 0),
clk => clk,
din(31 downto 0) => din(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => Q(0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_rd_logic is
port (
empty : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gcc0.gc0.count_reg[3]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_rd_logic : entity is "rd_logic";
end scfifo_32in_32out_1kb_rd_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_rd_logic is
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_5\ : STD_LOGIC;
signal \gr1.rfwft_n_6\ : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_5 : STD_LOGIC;
begin
\gr1.rfwft\: entity work.scfifo_32in_32out_1kb_rd_fwft
port map (
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[4]\(0) => p_14_out,
\gpr1.dout_i_reg[0]\(0) => \gpr1.dout_i_reg[0]\(0),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gr1.rfwft_n_5\,
ram_full_i_reg => \gr1.rfwft_n_1\,
ram_full_i_reg_0 => \gr1.rfwft_n_6\,
rd_en => rd_en,
wr_en => wr_en
);
\grss.rsts\: entity work.scfifo_32in_32out_1kb_rd_status_flags_ss
port map (
Q(0) => Q(0),
clk => clk,
p_18_out => p_18_out,
ram_empty_fb_i_reg_0 => rpntr_n_5
);
rpntr: entity work.scfifo_32in_32out_1kb_rd_bin_cntr
port map (
E(0) => p_14_out,
Q(0) => Q(0),
clk => clk,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => \gcc0.gc0.count_reg[2]\(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gcc0.gc0.count_reg[3]\,
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.rfwft_n_5\,
\gpregsm1.curr_fwft_state_reg[0]_0\ => \gr1.rfwft_n_6\,
p_18_out => p_18_out,
ram_empty_fb_i_reg => rpntr_n_5,
ram_empty_fb_i_reg_0 => \gr1.rfwft_n_1\,
ram_full_comb => ram_full_comb,
ram_full_fb_i_reg => ram_full_fb_i_reg,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_wr_logic is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_wr_logic : entity is "wr_logic";
end scfifo_32in_32out_1kb_wr_logic;
architecture STRUCTURE of scfifo_32in_32out_1kb_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.scfifo_32in_32out_1kb_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\gcc0.gc0.count_reg[4]\ => p_1_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
ram_full_i_reg_0 => ram_full_i_reg_0,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
wpntr: entity work.scfifo_32in_32out_1kb_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gc0.count_d1_reg[4]\(1 downto 0) => \gc0.count_d1_reg[4]\(1 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
ram_full_i_reg => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_32in_32out_1kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_10_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal rstblk_n_4 : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_32in_32out_1kb_rd_logic
port map (
E(0) => p_15_out,
Q(0) => RD_RST,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gcc0.gc0.count_reg[2]\(2 downto 0) => p_9_out(2 downto 0),
\gcc0.gc0.count_reg[3]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\gpr1.dout_i_reg[0]\(0) => ram_rd_en_i,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_20_out(4 downto 0),
p_1_out => p_1_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_32in_32out_1kb_wr_logic
port map (
AR(0) => \^rst\,
E(0) => p_4_out,
Q(2 downto 0) => p_9_out(2 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[4]\(1 downto 0) => p_20_out(4 downto 3),
\gpr1.dout_i_reg[1]\(4 downto 0) => p_10_out(4 downto 0),
p_1_out => p_1_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_8\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_32in_32out_1kb_memory
port map (
E(0) => ram_rd_en_i,
Q(0) => rstblk_n_4,
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_10_out(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_15_out,
ram_full_fb_i_reg(0) => p_4_out
);
rstblk: entity work.scfifo_32in_32out_1kb_reset_blk_ramfifo
port map (
AR(0) => \^rst\,
Q(1) => RD_RST,
Q(0) => rstblk_n_4,
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_32in_32out_1kb_fifo_generator_top;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_ramfifo
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end scfifo_32in_32out_1kb_fifo_generator_v12_0_synth;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_32in_32out_1kb_fifo_generator_top
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_32in_32out_1kb_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end scfifo_32in_32out_1kb_fifo_generator_v12_0;
architecture STRUCTURE of scfifo_32in_32out_1kb_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0_synth
port map (
clk => clk,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_32in_32out_1kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_32in_32out_1kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_32in_32out_1kb : entity is "scfifo_32in_32out_1kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_32in_32out_1kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_32in_32out_1kb : entity is "fifo_generator_v12_0,Vivado 2015.1";
end scfifo_32in_32out_1kb;
architecture STRUCTURE of scfifo_32in_32out_1kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.scfifo_32in_32out_1kb_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY pikachu_jump_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END pikachu_jump_pixel;
ARCHITECTURE pikachu_jump_pixel_arch OF pikachu_jump_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF pikachu_jump_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF pikachu_jump_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF pikachu_jump_pixel_arch : ARCHITECTURE IS "pikachu_jump_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF pikachu_jump_pixel_arch: ARCHITECTURE IS "pikachu_jump_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=" &
"pikachu_jump_pixel.mif,C_INIT_FILE=pikachu_jump_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=6804,C_READ_DEPTH_A=6804,C_ADDRA_WIDTH=13,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12," &
"C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=6804,C_READ_DEPTH_B=6804,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0" &
",C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=3,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.016775 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "pikachu_jump_pixel.mif",
C_INIT_FILE => "pikachu_jump_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 6804,
C_READ_DEPTH_A => 6804,
C_ADDRA_WIDTH => 13,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 6804,
C_READ_DEPTH_B => 6804,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "3",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.016775 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END pikachu_jump_pixel_arch;
|
library ieee; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
--library std;
--use std.all;
library ocpi; use ocpi.types.all; use ocpi.wci.all;
package props is
--
-- Property storage entities to attach to a wci.decoder
--
-- Declarations for various property implementationss
--
-- registered bool property value, with write pulse
--
component bool_property
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(0 downto 0);
value : out bool_t;
written : out bool_t);
end component;
--
-- registered bool property array value, with write pulse
--
component bool_array_property
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out bool_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_bool_property
generic (worker : worker_t; property : property_t);
port (value : in bool_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_bool_array_property
generic (worker : worker_t; property : property_t);
port (value : in bool_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered char property value, with write pulse
--
component char_property
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(char_t'range);
value : out char_t;
written : out bool_t);
end component;
--
-- registered char property array value, with write pulse
--
component char_array_property
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out char_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_char_property
generic (worker : worker_t; property : property_t);
port (value : in char_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_char_array_property
generic (worker : worker_t; property : property_t);
port (value : in char_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered double property value, with write pulse
--
component double_property
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_t;
written : out bool_t;
hi32 : in bool_t);
end component;
--
-- registered double property array value, with write pulse
--
component double_array_property
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property
--
component read_double_property
generic (worker : worker_t; property : property_t);
port (value : in double_t;
data_out : out std_logic_vector(31 downto 0);
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property array
--
component read_double_array_property
generic (worker : worker_t; property : property_t);
port (value : in double_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end component;
--
-- registered float property value, with write pulse
--
component float_property
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(float_t'range);
value : out float_t;
written : out bool_t);
end component;
--
-- registered float property array value, with write pulse
--
component float_array_property
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out float_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_float_property
generic (worker : worker_t; property : property_t);
port (value : in float_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_float_array_property
generic (worker : worker_t; property : property_t);
port (value : in float_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered short property value, with write pulse
--
component short_property
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(short_t'range);
value : out short_t;
written : out bool_t);
end component;
--
-- registered short property array value, with write pulse
--
component short_array_property
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out short_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_short_property
generic (worker : worker_t; property : property_t);
port (value : in short_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_short_array_property
generic (worker : worker_t; property : property_t);
port (value : in short_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered long property value, with write pulse
--
component long_property
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(long_t'range);
value : out long_t;
written : out bool_t);
end component;
--
-- registered long property array value, with write pulse
--
component long_array_property
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out long_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_long_property
generic (worker : worker_t; property : property_t);
port (value : in long_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_long_array_property
generic (worker : worker_t; property : property_t);
port (value : in long_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered uchar property value, with write pulse
--
component uchar_property
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(uchar_t'range);
value : out uchar_t;
written : out bool_t);
end component;
--
-- registered uchar property array value, with write pulse
--
component uchar_array_property
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out uchar_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_uchar_property
generic (worker : worker_t; property : property_t);
port (value : in uchar_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_uchar_array_property
generic (worker : worker_t; property : property_t);
port (value : in uchar_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered ulong property value, with write pulse
--
component ulong_property
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ulong_t'range);
value : out ulong_t;
written : out bool_t);
end component;
--
-- registered ulong property array value, with write pulse
--
component ulong_array_property
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_ulong_property
generic (worker : worker_t; property : property_t);
port (value : in ulong_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_ulong_array_property
generic (worker : worker_t; property : property_t);
port (value : in ulong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered ushort property value, with write pulse
--
component ushort_property
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ushort_t'range);
value : out ushort_t;
written : out bool_t);
end component;
--
-- registered ushort property array value, with write pulse
--
component ushort_array_property
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ushort_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end component;
--
-- readback scalar <=32 property
--
component read_ushort_property
generic (worker : worker_t; property : property_t);
port (value : in ushort_t;
data_out : out std_logic_vector(31 downto 0));
end component;
--
-- readback scalar <=32 property array
--
component read_ushort_array_property
generic (worker : worker_t; property : property_t);
port (value : in ushort_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end component;
--
-- registered longlong property value, with write pulse
--
component longlong_property
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_t;
written : out bool_t;
hi32 : in bool_t);
end component;
--
-- registered longlong property array value, with write pulse
--
component longlong_array_property
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property
--
component read_longlong_property
generic (worker : worker_t; property : property_t);
port (value : in longlong_t;
data_out : out std_logic_vector(31 downto 0);
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property array
--
component read_longlong_array_property
generic (worker : worker_t; property : property_t);
port (value : in longlong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end component;
--
-- registered ulonglong property value, with write pulse
--
component ulonglong_property
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_t;
written : out bool_t;
hi32 : in bool_t);
end component;
--
-- registered ulonglong property array value, with write pulse
--
component ulonglong_array_property
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property
--
component read_ulonglong_property
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_t;
data_out : out std_logic_vector(31 downto 0);
hi32 : in bool_t);
end component;
--
-- readback scalar >32 property array
--
component read_ulonglong_array_property
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end component;
--
-- registered string property value, with write pulse
--
component string_property
generic(worker : worker_t; property : property_t; default : string_t := ("00000000","00000000"));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_t(0 to property.string_length);
written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
--
-- registered string property array value, with write pulse
--
component string_array_property
generic(worker : worker_t; property : property_t; default : string_array_t := (("00000000","00000000"),("00000000","00000000")));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
--
-- readback scalar <=32 property
--
component read_string_property
generic (worker : worker_t; property : property_t);
port (value : in string_t;
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
--
-- readback string property array
--
component read_string_array_property
generic (worker : worker_t; property : property_t);
port (value : in string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end component;
end package props;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT WR_FLASH_PRE_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_SIGNED.ALL;
------------------------------------------------------------------------------
entity divider is
generic (
tag_width : integer := 6
);
port (
clk : IN std_logic;
Resetb : IN std_logic;
PhyReg_DivRsData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit
PhyReg_DivRtData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit --
Iss_RobTag : IN std_logic_vector( 4 downto 0); -- from divider issue queue unit
Iss_Div : IN std_logic; -- from issue unit
-------------------------------- Logic for the pics ( added by Atif) --------------------------------
Div_RdPhyAddr : out std_logic_vector(5 downto 0); -- output to CDB required
Div_RdWrite : out std_logic;
Iss_RdPhyAddr : in std_logic_vector(5 downto 0); -- incoming form issue queue, need to be carried as Iss_RobTag
Iss_RdWrite : in std_logic;
----------------------------------------------------------------------
-- translate_off
Iss_instructionDiv : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Div_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 ) ;
Div_Done : out std_logic ;
Div_RobTag : OUT std_logic_vector(4 downto 0);
Div_Rddata : OUT std_logic_vector(31 downto 0);
Div_ExeRdy : OUT std_logic -- divider is read for division ==> drives "div_exec_ready" in the TOP
);
end divider;
architecture behv of divider is
component divider_core is
Port ( Dividend : in std_logic_vector (31 downto 0 );
Divisor : in std_logic_vector ( 31 downto 0);
Rem_n_Quo : out std_logic_vector ( 31 downto 0)
);
end component divider_core;
-- component divider_core is
-- port ( DATA_A : in std_logic_vector (31 downto 0 );
-- DATA_B : in std_logic_vector (31 downto 0);
-- DIV_OUT : out std_logic_vector ( 31 downto 0)
-- );
-- end component divider_core;
subtype tag_type is std_logic_vector(4 downto 0);
type tag is array (0 to 5) of tag_type; -- changed from (0 to 4)
-- tag_valid: 0 through 5 for the 6 pipeline registers forming a 6-clock long combinational division
-- note: Since 1 clock is lost in holding the incoming operands in a register before starting the division
-- we can only take 6 clocks (including a clock long combinational logic upstream of the CDB mux)
signal tag_valid,rdwrite : std_logic_vector(5 downto 0); -- changed from (4 downto 0)
signal tag_div : tag;
subtype PhyAddr_Type is std_logic_vector(5 downto 0);
type PhyAddr is array (0 to 5) of PhyAddr_Type;
signal RdPhyAddr : PhyAddr;
-- signal div_rem_quo : std_logic_vector(31 downto 0);
-- signal result : std_logic_vector(31 downto 0);
signal divisor, dividend: std_logic_vector(31 downto 0);
signal rfd : std_logic; -- rfd = ready for division
signal BufferDepth :std_logic_vector ( 4 downto 0 ) ; -- for the instruction coming from the division issue queue
signal Buffer0Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer1Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer2Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer3Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer4Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer5Depth :std_logic_vector ( 4 downto 0 ) ;
begin
div : divider_core
port map (
Dividend => dividend,
Divisor => divisor,
Rem_n_Quo => Div_Rddata
);
-- port map (
-- DATA_A => divisor,
-- DATA_B => dividend,
-- DIV_OUT => result
-- );
Div_ExeRdy <= rfd;
-- Div_Rddata <= div_rem_quo;
-- translate_off
Div_instruction <= Iss_instructionDiv ;
-- translate_on
Div_Done <= tag_valid(5) ; -- previously 3? -- are you doing only 0 to 3? -- let us do 0 to 5 as our diagrams show 0 to 5
Div_RobTag <= tag_div(5);
Div_RdPhyAddr <= RdPhyAddr(5);
Div_RdWrite <= rdwrite(5);
BufferDepth <= unsigned(Iss_RobTag) - unsigned(Rob_TopPtr) ;
Buffer0Depth <= unsigned(tag_div(0)) - unsigned(Rob_TopPtr) ;
Buffer1Depth <= unsigned(tag_div(1)) - unsigned(Rob_TopPtr) ;
Buffer2Depth <= unsigned(tag_div(2)) - unsigned(Rob_TopPtr) ;
Buffer3Depth <= unsigned(tag_div(3)) - unsigned(Rob_TopPtr) ;
Buffer4Depth <= unsigned(tag_div(4)) - unsigned(Rob_TopPtr) ;
-- Note: On the tick of the clock, the six pipeline registers (0 to 5) will move one step down.
-- The top-most register 0 will receive a tag from divider issue unit.
-- When Cdb_Flush is activated, we are responsible to invalidate appropriate Flip-Flops
-- by the end of the clock. So we take care of the six valid-bit FFs, tag_valid(0 to 5) by looking at the 5 depths.
-- The CDB shall take care of invalidiating the outgoing div instruction
-- (going out of multiplier and entering the CDB register). So CDB will worry about Buf5Depth!
-- Hence the following line is not needed here
-- Buffer5Depth <= unsigned(tag_div(5)) - unsigned(Rob_TopPtr) ;
tag_carry : process (clk, Resetb)
begin
if (Resetb = '0') then
for i in 0 to 5 loop -- 0 to 5
tag_div(i) <= (others => '0'); -- Though we could have these as don't cares (others => '-'), for the sake of easy debugging, let us make them zeros;
RdPhyAddr(i) <= (others=>'0');
end loop;
tag_valid <= (others => '0');
rdwrite <= (others => '0');
rfd <= '1';
divisor <= (others => '-');
dividend <= (others => '-');
elsif(clk'event and clk = '1') then
-- if an instruction is coming in from divide issue queue
if(Iss_Div = '1' and rfd = '1' and ( (Cdb_Flush = '0') or ( Cdb_Flush = '1' and BufferDepth < Cdb_RobDepth ) ) ) then
-- (Iss_Div = '1' and rfd = '1' ) ? it is enough to say (Iss_Div = '1') as Iss_Div can not be made '1' by the issue unit unless rfd was '1'
divisor <= PhyReg_DivRtData;
dividend <= PhyReg_DivRsData;
tag_div(0) <= Iss_RobTag;
RdPhyAddr(0)<= Iss_RdPhyAddr;
rdwrite(0) <= Iss_RdWrite;
tag_valid(0)<= '1';
rfd <= '0';
else
tag_div(0) <= (others => '0'); -- though it is not necessary, we wish to clear to make debugging easy
RdPhyAddr(0) <= (others => '0');
tag_valid(0)<= '0';
rdwrite(0)<='0';
end if;
if ( Cdb_Flush = '1' and
( -- if there is an ongoing div operation which does not leave the divisor by the end of the clock
( Buffer0Depth > Cdb_RobDepth and tag_valid(0) = '1' ) or
( Buffer1Depth > Cdb_RobDepth and tag_valid(1) = '1' ) or
( Buffer2Depth > Cdb_RobDepth and tag_valid(2) = '1' ) or
( Buffer3Depth > Cdb_RobDepth and tag_valid(3) = '1' ) or
( Buffer4Depth > Cdb_RobDepth and tag_valid(4) = '1' )
-- ( Buffer5Depth > Cdb_RobDepth and tag_valid(5) = '1' ) -- see the above note regarding Buffer5Depth
) ) then
rfd <= '1' ;
for i in 1 to 5 loop -- note: it's 1 to 5, not 0 to 4 as these items are on move!
tag_valid(i) <= '0' ;
rdwrite(i)<='0';
tag_div(i) <= (others => '0'); -- Though we could have these tags as don't cares (others => '-'), for the sake of easy debugging, let us make them zeros;
RdPhyAddr(i) <= (others => '0');
end loop;
else
for i in 1 to 5 loop
tag_valid(i) <= tag_valid(i-1); -- tag_valid(0) receives a 1 or 0 depending on whether a new div instruction is issued or not.
tag_div(i) <= tag_div(i-1);
rdwrite(i) <= rdwrite(i-1);
RdPhyAddr(i) <= RdPhyAddr(i-1) ;
end loop;
if (rfd = '0' and
( (tag_valid(5) = '1') or -- it is unnecessary to qaulify with (rfd = '0' ) as (tag_valid(5) = '1') is enough for this part of the clause
( (tag_valid(0) = '0') and (tag_valid(1) = '0') and (tag_valid(2) = '0') and (tag_valid(3) = '0') and (tag_valid(4) = '0') ) ) )
-- if all the upper 5 tag valid bits (bits 0 to 4) are zeros -- this is perhaps redundant
-- However, if you do keep this piece of the clause, you do need the(rfd = '0' ) as a qualifier.
-- This is not apparent at first sight. This is an artifact of HDL coding!
-- Notice that, if we are initiating a division, we are assigning a '0' to the rfd signal (with delta-T delay) on line 125 above.
-- Then we come down here and override that assignment with '1' in line 162, resulting rfd continuing to be 1 for 1 extra clock.
-- To avoid this problem, you need to have (rfd = '0' ) as a qualifier for this part of the clause.
-- In fact, if the tag_valid[0:4] = 00000 and (rfd = '0' ) , then (tag_valid(5) = '1') is true and hence this clause is redundant as stated before.
then
rfd <= '1';
end if;
-- if (rfd = '1')then
-- div_rem_quo <= result; -- another clock? Result shall go directly to the CDB mux
-- end if;
-- Div_RobTag <= tag_div(4);
end if;
end if ;
end process tag_carry;
end architecture behv; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr11 is
port (val : std_logic_vector(3 downto 0);
res : out natural);
end arr11;
architecture behav of arr11 is
function find (s : string; c : character) return natural is
begin
for i in s'range loop
if s (i) = c then
return i;
end if;
end loop;
return 0;
end find;
constant str1 : string := "hello world";
constant pos1 : natural := find (str1, 'w');
alias str2 : string (str1'length downto 1) is str1;
constant str3 : string := str2;
constant pos3 : natural := find (str3, 'w');
begin
assert pos1 = 7;
assert pos3 = 5;
res <= pos1;
end behav;
|
--************************************************************************************************
-- Top entity for AVR microcontroller (for synthesis) with JTAG OCD and DMAs
-- Version 0.5 (Version for Xilinx)
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
--************************************************************************************************
-- Adapted for AtomFPGA
-- input clock is now 16MHz
--************************************************************************************************
--************************************************************************************************
--Adapted for the Papilio FPGA development board. To learn more visit http://papilio.cc
--Gadget Factory Note: This project is currently configured for the Papilio One board Version 2.03 or greater. It assumes a 32Mhz oscillator and a ucf with a period of 31.25.
--*************************************************************************************************
--*************************************************************************************************
--This is AVR8-based SoC for processing diode signals
--modifications by Zvonimir Bandic
--modified 01/05/2013
--*************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
use WORK.AVR_uC_CompPack.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.spi_mod_comp_pack.all; --SPI
use WORK.spi_slv_sel_comp_pack.all;
use WORK.MemAccessCtrlPack.all;
use WORK.MemAccessCompPack.all;
entity AVR8 is
generic (
CDATAMEMSIZE : integer;
CPROGMEMSIZE : integer
);
port (
nrst : in std_logic; --Uncomment this to connect reset to an external pushbutton. Must be defined in ucf.
clk16M : in std_logic;
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
portc : inout std_logic_vector(7 downto 0);
portdin : in std_logic_vector(7 downto 0);
portdout : out std_logic_vector(7 downto 0);
portein : in std_logic_vector(7 downto 0);
porteout : out std_logic_vector(7 downto 0);
portf : inout std_logic_vector(7 downto 0);
spi_mosio : out std_logic;
spi_scko : out std_logic;
spi_cs_n : out std_logic;
spi_misoi : in std_logic;
-- UART
rxd : in std_logic;
txd : out std_logic
);
end AVR8;
architecture Struct of AVR8 is
-- Use these setting to control which peripherals you want to include with your custom AVR8 implementation.
constant CImplPORTA : boolean := TRUE; -- set to false here for portA and portB, or DDRAreg and DDRBreg
constant CImplPORTB : boolean := TRUE;
constant CImplPORTC : boolean := FALSE;
constant CImplPORTD : boolean := TRUE;
constant CImplPORTE : boolean := TRUE;
constant CImplPORTF : boolean := FALSE;
constant CImplUART : boolean := TRUE; --AVR8 UART peripheral
constant CImplSPI : boolean := FALSE; -- adding SPI master
constant CImplTmrCnt : boolean := FALSE; --AVR8 Timer
constant CImplExtIRQ : boolean := FALSE; --AVR8 Interrupt Unit
-- ############################## Signals connected directly to the core ##########################################
signal core_cpuwait : std_logic;
-- Program memory
signal core_pc : std_logic_vector (15 downto 0); -- PROM address
signal core_inst : std_logic_vector (15 downto 0); -- PROM data
-- I/O registers
signal core_adr : std_logic_vector (15 downto 0);
signal core_iore : std_logic;
signal core_iowe : std_logic;
-- Data memery
signal core_ramadr : std_logic_vector (15 downto 0);
signal core_ramre : std_logic;
signal core_ramwe : std_logic;
signal core_dbusin : std_logic_vector (7 downto 0);
signal core_dbusout : std_logic_vector (7 downto 0);
-- Interrupts
signal core_irqlines : std_logic_vector(22 downto 0);
signal core_irqack : std_logic;
signal core_irqackad : std_logic_vector(4 downto 0);
-- ###############################################################################################################
-- ############################## Signals connected directly to the SRAM controller ###############################
signal ram_din : std_logic_vector(7 downto 0);
-- ###############################################################################################################
-- ####################### Signals connected directly to the external multiplexer ################################
signal io_port_out : ext_mux_din_type;
signal io_port_out_en : ext_mux_en_type;
signal ind_irq_ack : std_logic_vector(core_irqlines'range);
-- ###############################################################################################################
-- ################################## Reset signals #############################################
signal core_ireset : std_logic;
-- ##############################################################################################
-- Port signals
signal PortAReg : std_logic_vector(portain'range);
signal DDRAReg : std_logic_vector(portain'range);
signal PortBReg : std_logic_vector(portbin'range);
signal DDRBReg : std_logic_vector(portbin'range);
signal PortCReg : std_logic_vector(portc'range);
signal DDRCReg : std_logic_vector(portc'range);
signal PortDReg : std_logic_vector(portdin'range);
signal DDRDReg : std_logic_vector(portdin'range);
signal PortEReg : std_logic_vector(portein'range);
signal DDREReg : std_logic_vector(portein'range);
signal PortFReg : std_logic_vector(portf'range);
signal DDRFReg : std_logic_vector(portf'range);
-- Added for Synopsys compatibility
signal gnd : std_logic;
signal vcc : std_logic;
-- Sleep support
signal core_cp2 : std_logic; -- Global clock signal after gating(and global primitive)
signal sleep_en : std_logic;
signal sleepi : std_logic;
signal irqok : std_logic;
signal globint : std_logic;
signal nrst_clksw : std_logic; -- Separate reset for clock gating module
-- Watchdog related signals
signal wdtmout : std_logic; -- Watchdog overflow
signal core_wdri : std_logic; -- Watchdog clear
-- ********************** JTAG and memory **********************************************
-- PM address,data and control
signal pm_adr : std_logic_vector(core_pc'range);
signal pm_h_we : std_logic;
signal pm_l_we : std_logic;
signal pm_din : std_logic_vector(core_inst'range);
signal pm_dout : std_logic_vector(core_inst'range);
signal TDO_Out : std_logic;
signal TDO_OE : std_logic;
signal JTAG_Rst : std_logic;
-- ********************** JTAG and memory **********************************************
signal nrst_cp64m_tmp : std_logic;
signal ram_cp2_n : std_logic;
signal sleep_mode : std_logic;
-- "EEPROM" related signals
signal EEPrgSel : std_logic;
signal EEAdr : std_logic_vector(11 downto 0);
signal EEWrData : std_logic_vector(7 downto 0);
signal EERdData : std_logic_vector(7 downto 0);
signal EEWr : std_logic;
-- New
signal busmin : MastersOutBus_Type;
signal busmwait : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
signal slv_outs : SlavesOutBus_Type;
signal ram_sel : std_logic;
-- UART DMA
signal udma_mack : std_logic;
signal mem_mux_out : std_logic_vector (7 downto 0);
-- Place Holder Signals for JTAG instead of connecting them externally
signal TRSTn : std_logic;
signal TMS : std_logic;
signal TCK : std_logic;
signal TDI : std_logic;
signal TDO : std_logic;
-- AES
signal aes_mack : std_logic;
-- Address decoder
signal stb_IO : std_logic;
signal stb_IOmod : std_logic_vector (CNumOfSlaves-1 downto 0);
signal ram_ce : std_logic;
signal slv_cpuwait : std_logic;
-- Memory i/f
signal mem_ramadr : std_logic_vector (15 downto 0);
signal mem_ram_dbus_in : std_logic_vector (7 downto 0);
signal mem_ram_dbus_out : std_logic_vector (7 downto 0);
signal mem_ramwe : std_logic;
signal mem_ramre : std_logic;
-- RAM
signal ram_ramwe : std_logic;
-- nrst
--signal nrst : std_logic; --Comment this to connect reset to an external pushbutton.
-- ############################## Signals connected directly to the I/O registers ################################
-- PortA
signal porta_dbusout : std_logic_vector (7 downto 0);
signal porta_out_en : std_logic;
-- PortB
signal portb_dbusout : std_logic_vector (7 downto 0);
signal portb_out_en : std_logic;
-- PortC
signal portc_dbusout : std_logic_vector (7 downto 0);
signal portc_out_en : std_logic;
-- PortD
signal portd_dbusout : std_logic_vector (7 downto 0);
signal portd_out_en : std_logic;
-- PortE
signal porte_dbusout : std_logic_vector (7 downto 0);
signal porte_out_en : std_logic;
-- PortF
signal portf_dbusout : std_logic_vector (7 downto 0);
signal portf_out_en : std_logic;
-- Timer/Counter
signal tc_dbusout : std_logic_vector (7 downto 0);
signal tc_out_en : std_logic;
-- Ext IRQ Controller
signal extirq_dbusout : std_logic_vector (7 downto 0);
signal extirq_out_en : std_logic;
signal ext_irqlines : std_logic_vector(7 downto 0);
-- UART
signal uart_dbusout : std_logic_vector (7 downto 0);
signal uart_out_en : std_logic;
-- SPI
constant c_spi_slvs_num : integer := 1;
--signal spi_misoi : std_logic;
signal spi_mosii : std_logic;
signal spi_scki : std_logic;
signal spi_ss_b : std_logic;
signal spi_misoo : std_logic;
--signal spi_mosio : std_logic;
--signal spi_scko : std_logic;
signal spi_spe : std_logic;
signal spi_spimaster : std_logic;
signal spi_dbusout : std_logic_vector (7 downto 0);
signal spi_out_en : std_logic;
-- Slave selects
signal spi_slv_sel_n : std_logic_vector(c_spi_slvs_num-1 downto 0);
-- SPI
-- ###############################################################################################################
-- ############################## Define Signals for User Cores ##################################################
-- Example Core - - core9
--signal core9_input_sig : std_logic_vector(1 downto 0); --Define a signal for the inputs.
-- ###############################################################################################################
begin
-- Added for Synopsys compatibility
gnd <= '0';
vcc <= '1';
-- Added for Synopsys compatibility
--nrst <= '1'; --Comment this to connect reset to an external pushbutton.
core_inst <= pm_dout;
--Signals to connect peripherals controlled from Generics to the physical ports
-- ****************** User Cores - Instantiate User Cores Here **************************
-- ****************** END User Cores - Instantiate User Cores Here **************************
-- Unused IRQ lines
--core_irqlines(7 downto 4) <= ( others => '0');
--core_irqlines(3 downto 0) <= ( others => '0');
core_irqlines(13 downto 10) <= ( others => '0');
--core_irqlines(16) <= '0'; --now used by SPI
core_irqlines(22 downto 20) <= ( others => '0');
-- ************************
-- Unused out_en
io_port_out_en(11 to 15) <= (others => '0');
io_port_out(11 to 15) <= (others => (others => '0'));
AVR_Core_Inst:component AVR_Core port map(
--Clock and reset
cp2 => core_cp2,
cp2en => vcc,
ireset => core_ireset,
-- JTAG OCD support
valid_instr => open,
insert_nop => gnd,
block_irq => gnd,
change_flow => open,
-- Program Memory
pc => core_pc,
inst => core_inst,
-- I/O control
adr => core_adr,
iore => core_iore,
iowe => core_iowe,
-- Data memory control
ramadr => core_ramadr,
ramre => core_ramre,
ramwe => core_ramwe,
cpuwait => core_cpuwait,
-- Data paths
dbusin => core_dbusin,
dbusout => core_dbusout,
-- Interrupts
irqlines => core_irqlines,
irqack => core_irqack,
irqackad => core_irqackad,
--Sleep Control
sleepi => sleepi,
irqok => irqok,
globint => globint,
--Watchdog
wdri => core_wdri);
RAM_Data_Register:component RAMDataReg port map(
ireset => core_ireset,
cp2 => clk16M, -- clk,
cpuwait => core_cpuwait,
RAMDataIn => core_dbusout,
RAMDataOut => ram_din
);
EXT_MUX:component external_mux port map(
ramre => mem_ramre, -- ramre output of the arbiter and multiplexor
dbus_out => core_dbusin, -- Data input of the core
ram_data_out => mem_mux_out, -- Data output of the RAM mux(RAM or memory located I/O)
io_port_bus => io_port_out, -- Data outputs of the I/O
io_port_en_bus => io_port_out_en, -- Out enable outputs of I/O
irqack => core_irqack,
irqackad => core_irqackad,
ind_irq_ack => ind_irq_ack -- Individual interrupt acknolege for the peripheral
);
-- ****************** PORTA **************************
PORTA_Impl:if CImplPORTA generate
PORTA_COMP:component pport
generic map(PPortNum => 0)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porta_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porta_out_en,
-- External connection
portx => PortAReg,
ddrx => DDRAReg,
pinx => portain,
irqlines => open);
-- PORTA connection to the external multiplexer
io_port_out(0) <= porta_dbusout;
io_port_out_en(0) <= porta_out_en;
---- Tri-state control for PORTA
--PortAZCtrl:for i in porta'range generate
--porta(i) <= PortAReg(i) when DDRAReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTA
PortAZCtrl:for i in portaout'range generate
portaout(i) <= PortAReg(i) when DDRAReg(i)='1' else '0';
end generate;
end generate;
PORTA_Not_Impl:if not CImplPORTA generate
portaout <= (others => '0');
end generate;
-- ****************** PORTB **************************
PORTB_Impl:if CImplPORTB generate
PORTB_COMP:component pport
generic map (PPortNum => 1)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portb_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portb_out_en,
-- External connection
portx => PortBReg,
ddrx => DDRBReg,
pinx => portbin,
irqlines => ext_irqlines);
-- PORTB connection to the external multiplexer
io_port_out(1) <= portb_dbusout;
io_port_out_en(1) <= portb_out_en;
---- Tri-state control for PORTB
--PortBZCtrl:for i in portb'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTB
PortBZCtrl:for i in portbout'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
portbout(i) <= PortBReg(i) when DDRBReg(i)='1' else '0';
end generate;
end generate;
PORTB_Not_Impl:if not CImplPORTB generate
portbout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTC **************************
PORTC_Impl:if CImplPORTC generate
PORTC_COMP:component pport
generic map(PPortNum => 2)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portc_out_en,
-- External connection
portx => PortCReg,
ddrx => DDRCReg,
pinx => portc,
irqlines => open);
-- PORTC connection to the external multiplexer
io_port_out(5) <= portc_dbusout;
io_port_out_en(5) <= portc_out_en;
---- Tri-state control for PORTC
--PortCZCtrl:for i in portc'range generate
--portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTC
PortCZCtrl:for i in portc'range generate
portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
end generate;
end generate;
PORTC_Not_Impl:if not CImplPORTC generate
portc <= (others => 'Z');
end generate;
-- ****************** PORTD **************************
PORTD_Impl:if CImplPORTD generate
PORTD_COMP:component pport
generic map (PPortNum => 3)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portd_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portd_out_en,
-- External connection
portx => PortDReg,
ddrx => DDRDReg,
pinx => portdin,
irqlines => open);
-- PORTD connection to the external multiplexer
io_port_out(6) <= portd_dbusout;
io_port_out_en(6) <= portd_out_en;
---- Tri-state control for PORTD
--PortDZCtrl:for i in portd'range generate
--portd(i) <= PortDReg(i) when DDRDReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTD
PortDZCtrl:for i in portdout'range generate
portdout(i) <= PortDReg(i) when DDRDReg(i)='1' else '0';
end generate;
end generate;
PORTD_Not_Impl:if not CImplPORTD generate
portdout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTE **************************
PORTE_Impl:if CImplPORTE generate
PORTE_COMP:component pport
generic map(PPortNum => 4)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porte_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porte_out_en,
-- External connection
portx => PortEReg,
ddrx => DDREReg,
pinx => portein,
irqlines => open);
-- PORTE connection to the external multiplexer
io_port_out(7) <= porte_dbusout;
io_port_out_en(7) <= porte_out_en;
---- Tri-state control for PORTE
--PortEZCtrl:for i in porte'range generate
--porte(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTE
PortEZCtrl:for i in porteout'range generate
porteout(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
end generate;
end generate;
PORTE_Not_Impl:if not CImplPORTE generate
porteout <= (others => 'Z');
end generate;
-- ****************** PORTF **************************
PORTF_Impl:if CImplPORTF generate
PORTF_COMP:component pport
generic map (PPortNum => 5)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portf_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portf_out_en,
-- External connection
portx => PortFReg,
ddrx => DDRFReg,
pinx => portf,
irqlines => open);
-- PORTF connection to the external multiplexer
io_port_out(8) <= portf_dbusout;
io_port_out_en(8) <= portf_out_en;
-- Tri-state control for PORTF
PortFZCtrl:for i in portf'range generate
portf(i) <= PortFReg(i) when DDRFReg(i)='1' else 'Z';
end generate;
end generate;
PORTF_Not_Impl:if not CImplPORTF generate
portf <= (others => 'Z');
end generate;
-- ************************************************
--****************** External IRQ Controller**************************
ExtIRQ_Impl:if CImplExtIRQ generate
ExtIRQ_Inst:component ExtIRQ_Controller port map(
-- AVR Control
nReset => core_ireset,
clk => clk16M, -- clk,
clken => vcc,
irq_clken => vcc,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => extirq_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => extirq_out_en,
------------------------------------------------
extpins => ext_irqlines,
INTx => core_irqlines(7 downto 0));
-- ExtIRQ connection to the external multiplexer
io_port_out(10) <= extirq_dbusout;
io_port_out_en(10) <= extirq_out_en;
end generate;
--****************** Timer/Counter **************************
TmrCnt_Impl:if CImplTmrCnt generate
TmrCnt_Inst:component Timer_Counter port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
cp2en => vcc,
tmr_cp2en => vcc,
stopped_mode => gnd,
tmr_running => gnd,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => tc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => tc_out_en,
-- External inputs/outputs
EXT1 => gnd,
EXT2 => gnd,
OC0_PWM0 => open,
OC1A_PWM1A => open,
OC1B_PWM1B => open,
OC2_PWM2 => open,
-- Interrupt related signals
TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020)
TC0OvfIRQ_Ack => ind_irq_ack(15),
TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E)
TC0CmpIRQ_Ack => ind_irq_ack(14),
TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014)
TC2OvfIRQ_Ack => ind_irq_ack(9),
TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012)
TC2CmpIRQ_Ack => ind_irq_ack(8),
TC1OvfIRQ => open,
TC1OvfIRQ_Ack => gnd,
TC1CmpAIRQ => open,
TC1CmpAIRQ_Ack => gnd,
TC1CmpBIRQ => open,
TC1CmpBIRQ_Ack => gnd,
TC1ICIRQ => open,
TC1ICIRQ_Ack => gnd,
PWM0bit => open,
PWM10bit => open,
PWM11bit => open,
PWM2bit => open);
-- Timer/Counter connection to the external multiplexer
io_port_out(4) <= tc_dbusout;
io_port_out_en(4) <= tc_out_en;
end generate;
-- Watchdog is not implemented
wdtmout <= '0';
-- Reset generator
ResetGenerator_Inst:component ResetGenerator port map(
-- Clock inputs
cp2 => clk16M, -- clk,
cp64m => gnd,
-- Reset inputs
nrst => nrst,
npwrrst => vcc,
wdovf => wdtmout,
jtagrst => JTAG_Rst,
-- Reset outputs
nrst_cp2 => core_ireset,
nrst_cp64m => nrst_cp64m_tmp,
nrst_clksw => nrst_clksw
);
ClockGatingDis:if not CImplClockSw generate
core_cp2 <= clk16M;
end generate;
-- ********************** JTAG and memory **********************************************
ram_cp2_n <= not clk16M;
---- Data memory(8-bit)
DM_Inst : entity work.XDM
generic map (
WIDTH => 8,
SIZE => CDATAMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(f_log2(CDATAMEMSIZE) - 1 downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst : entity work.XPM
generic map (
WIDTH => 16,
SIZE => CPROGMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(f_log2(CPROGMEMSIZE) - 1 downto 0),
din => pm_din,
dout => pm_dout,
we => pm_l_we
);
-- ********************** JTAG and memory **********************************************
-- Sleep mode is not implemented
sleep_mode <= '0';
JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
-- JTAG related inputs/outputs
TRSTn => TRSTn, -- Optional
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO_Out,
TDO_OE => TDO_OE,
-- From the core
PC => core_pc,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr,
-- CPU reset
jtag_rst => JTAG_Rst
);
-- JTAG OCD module connection to the external multiplexer
io_port_out(3) <= (others => '0');
io_port_out_en(3) <= gnd;
TDO <= TDO_Out when TDO_OE='1' else 'Z';
-- *******************************************************************************************************
-- DMA, Memory decoder, ...
-- *******************************************************************************************************
-- ****************** SPI **************************
spi_is_used:if CImplSPI generate
spi_mod_inst:component spi_mod port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => spi_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => spi_out_en,
-- SPI i/f
misoi => spi_misoi,
mosii => spi_mosii,
scki => spi_scki,
ss_b => spi_ss_b,
misoo => spi_misoo,
mosio => spi_mosio,
scko => spi_scko,
spe => spi_spe,
spimaster => spi_spimaster,
-- IRQ
spiirq => core_irqlines(16),
spiack => ind_irq_ack(16),
-- Slave Programming Mode
por => gnd,
spiextload => gnd,
spidwrite => open,
spiload => open
);
-- SPI connection to the external multiplexer
io_port_out(9) <= spi_dbusout;
io_port_out_en(9) <= spi_out_en;
-- Pads
--mosi_SIG <= spi_mosio when (spi_spimaster='1') else 'Z';
--miso_SIG <= spi_misoo when (spi_spimaster='0') else 'Z';
--sck_SIG <= spi_scko when (spi_spimaster='1') else 'Z';
--
--spi_misoi <= miso_SIG;
--spi_mosii <= mosi_SIG;
--spi_scki <= sck_SIG;
spi_ss_b <= vcc;
-- Pads
spi_slv_sel_inst:component spi_slv_sel generic map(num_of_slvs => c_spi_slvs_num)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => open,
iore => core_iore,
iowe => core_iowe,
out_en => open,
-- Output
slv_sel_n => spi_slv_sel_n
);
end generate;
spi_cs_n <= spi_slv_sel_n(0);
no_spi:if not CImplSPI generate
--mosi_SIG <= 'Z';
--miso_SIG <= 'Z';
--sck_SIG <= 'Z';
--io_slv_out(1).dbusout <= (others => '0');
--io_slv_out(1).out_en <= gnd;
spi_slv_sel_n <= (others => '1');
end generate;
uart_Inst:component uart port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => uart_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => uart_out_en,
-- UART
rxd => rxd,
rx_en => open,
txd => txd,
tx_en => open,
-- IRQ
txcirq => core_irqlines(19),
txc_irqack => ind_irq_ack(19),
udreirq => core_irqlines(18),
rxcirq => core_irqlines(17)
);
-- UART connection to the external multiplexer
io_port_out(2) <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;
-- Arbiter and mux
ArbiterAndMux_Inst:component ArbiterAndMux port map(
--Clock and reset
ireset => core_ireset,
cp2 => core_cp2,
-- Bus masters
busmin => busmin,
busmwait => busmwait,
-- Memory Address,Data and Control
ramadr => mem_ramadr,
ramdout => mem_ram_dbus_in,
ramre => mem_ramre,
ramwe => mem_ramwe,
cpuwait => slv_cpuwait
);
-- cpuwait
slv_cpuwait <= '0';
-- Core connection
busmin(0).ramadr <= core_ramadr;
busmin(0).dout <= ram_din; -- !!!
busmin(0).ramre <= core_ramre;
busmin(0).ramwe <= core_ramwe;
core_cpuwait <= busmwait(0);
-- UART DMA connection
busmin(1).ramadr <= (others => '0');
busmin(1).dout <= (others => '0'); -- !!!
busmin(1).ramre <= gnd;
busmin(1).ramwe <= gnd;
udma_mack <= not busmwait(1);
-- AES DMA connection
busmin(2).ramadr <= (others => '0');
busmin(2).dout <= (others => '0');
busmin(2).ramre <= gnd;
busmin(2).ramwe <= gnd;
aes_mack <= not busmwait(2);
-- UART DMA slave part
slv_outs(0).dout <= (others => '0');
slv_outs(0).out_en <= gnd;
-- AES DMA slave part
slv_outs(1).dout <= (others => '0');
slv_outs(1).out_en <= gnd;
-- Memory read mux
MemRdMux_inst:component MemRdMux port map(
slv_outs => slv_outs,
ram_sel => ram_sel, -- Data RAM selection(optional input)
ram_dout => mem_ram_dbus_out, -- Data memory output (From RAM)
dout => mem_mux_out -- Data output (To the core and other bus masters)
);
-- Address decoder
RAMAdrDcd_Inst:component RAMAdrDcd port map(
ramadr => mem_ramadr,
ramre => mem_ramre,
ramwe => mem_ramwe,
-- Memory mapped I/O i/f
stb_IO => stb_IO,
stb_IOmod => stb_IOmod,
-- Data memory i/f
ram_we => ram_ramwe,
ram_ce => ram_ce,
ram_sel => ram_sel
);
end Struct;
|
--************************************************************************************************
-- Top entity for AVR microcontroller (for synthesis) with JTAG OCD and DMAs
-- Version 0.5 (Version for Xilinx)
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
--************************************************************************************************
-- Adapted for AtomFPGA
-- input clock is now 16MHz
--************************************************************************************************
--************************************************************************************************
--Adapted for the Papilio FPGA development board. To learn more visit http://papilio.cc
--Gadget Factory Note: This project is currently configured for the Papilio One board Version 2.03 or greater. It assumes a 32Mhz oscillator and a ucf with a period of 31.25.
--*************************************************************************************************
--*************************************************************************************************
--This is AVR8-based SoC for processing diode signals
--modifications by Zvonimir Bandic
--modified 01/05/2013
--*************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
use WORK.AVR_uC_CompPack.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.spi_mod_comp_pack.all; --SPI
use WORK.spi_slv_sel_comp_pack.all;
use WORK.MemAccessCtrlPack.all;
use WORK.MemAccessCompPack.all;
entity AVR8 is
generic (
CDATAMEMSIZE : integer;
CPROGMEMSIZE : integer
);
port (
nrst : in std_logic; --Uncomment this to connect reset to an external pushbutton. Must be defined in ucf.
clk16M : in std_logic;
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
portc : inout std_logic_vector(7 downto 0);
portdin : in std_logic_vector(7 downto 0);
portdout : out std_logic_vector(7 downto 0);
portein : in std_logic_vector(7 downto 0);
porteout : out std_logic_vector(7 downto 0);
portf : inout std_logic_vector(7 downto 0);
spi_mosio : out std_logic;
spi_scko : out std_logic;
spi_cs_n : out std_logic;
spi_misoi : in std_logic;
-- UART
rxd : in std_logic;
txd : out std_logic
);
end AVR8;
architecture Struct of AVR8 is
-- Use these setting to control which peripherals you want to include with your custom AVR8 implementation.
constant CImplPORTA : boolean := TRUE; -- set to false here for portA and portB, or DDRAreg and DDRBreg
constant CImplPORTB : boolean := TRUE;
constant CImplPORTC : boolean := FALSE;
constant CImplPORTD : boolean := TRUE;
constant CImplPORTE : boolean := TRUE;
constant CImplPORTF : boolean := FALSE;
constant CImplUART : boolean := TRUE; --AVR8 UART peripheral
constant CImplSPI : boolean := FALSE; -- adding SPI master
constant CImplTmrCnt : boolean := FALSE; --AVR8 Timer
constant CImplExtIRQ : boolean := FALSE; --AVR8 Interrupt Unit
-- ############################## Signals connected directly to the core ##########################################
signal core_cpuwait : std_logic;
-- Program memory
signal core_pc : std_logic_vector (15 downto 0); -- PROM address
signal core_inst : std_logic_vector (15 downto 0); -- PROM data
-- I/O registers
signal core_adr : std_logic_vector (15 downto 0);
signal core_iore : std_logic;
signal core_iowe : std_logic;
-- Data memery
signal core_ramadr : std_logic_vector (15 downto 0);
signal core_ramre : std_logic;
signal core_ramwe : std_logic;
signal core_dbusin : std_logic_vector (7 downto 0);
signal core_dbusout : std_logic_vector (7 downto 0);
-- Interrupts
signal core_irqlines : std_logic_vector(22 downto 0);
signal core_irqack : std_logic;
signal core_irqackad : std_logic_vector(4 downto 0);
-- ###############################################################################################################
-- ############################## Signals connected directly to the SRAM controller ###############################
signal ram_din : std_logic_vector(7 downto 0);
-- ###############################################################################################################
-- ####################### Signals connected directly to the external multiplexer ################################
signal io_port_out : ext_mux_din_type;
signal io_port_out_en : ext_mux_en_type;
signal ind_irq_ack : std_logic_vector(core_irqlines'range);
-- ###############################################################################################################
-- ################################## Reset signals #############################################
signal core_ireset : std_logic;
-- ##############################################################################################
-- Port signals
signal PortAReg : std_logic_vector(portain'range);
signal DDRAReg : std_logic_vector(portain'range);
signal PortBReg : std_logic_vector(portbin'range);
signal DDRBReg : std_logic_vector(portbin'range);
signal PortCReg : std_logic_vector(portc'range);
signal DDRCReg : std_logic_vector(portc'range);
signal PortDReg : std_logic_vector(portdin'range);
signal DDRDReg : std_logic_vector(portdin'range);
signal PortEReg : std_logic_vector(portein'range);
signal DDREReg : std_logic_vector(portein'range);
signal PortFReg : std_logic_vector(portf'range);
signal DDRFReg : std_logic_vector(portf'range);
-- Added for Synopsys compatibility
signal gnd : std_logic;
signal vcc : std_logic;
-- Sleep support
signal core_cp2 : std_logic; -- Global clock signal after gating(and global primitive)
signal sleep_en : std_logic;
signal sleepi : std_logic;
signal irqok : std_logic;
signal globint : std_logic;
signal nrst_clksw : std_logic; -- Separate reset for clock gating module
-- Watchdog related signals
signal wdtmout : std_logic; -- Watchdog overflow
signal core_wdri : std_logic; -- Watchdog clear
-- ********************** JTAG and memory **********************************************
-- PM address,data and control
signal pm_adr : std_logic_vector(core_pc'range);
signal pm_h_we : std_logic;
signal pm_l_we : std_logic;
signal pm_din : std_logic_vector(core_inst'range);
signal pm_dout : std_logic_vector(core_inst'range);
signal TDO_Out : std_logic;
signal TDO_OE : std_logic;
signal JTAG_Rst : std_logic;
-- ********************** JTAG and memory **********************************************
signal nrst_cp64m_tmp : std_logic;
signal ram_cp2_n : std_logic;
signal sleep_mode : std_logic;
-- "EEPROM" related signals
signal EEPrgSel : std_logic;
signal EEAdr : std_logic_vector(11 downto 0);
signal EEWrData : std_logic_vector(7 downto 0);
signal EERdData : std_logic_vector(7 downto 0);
signal EEWr : std_logic;
-- New
signal busmin : MastersOutBus_Type;
signal busmwait : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
signal slv_outs : SlavesOutBus_Type;
signal ram_sel : std_logic;
-- UART DMA
signal udma_mack : std_logic;
signal mem_mux_out : std_logic_vector (7 downto 0);
-- Place Holder Signals for JTAG instead of connecting them externally
signal TRSTn : std_logic;
signal TMS : std_logic;
signal TCK : std_logic;
signal TDI : std_logic;
signal TDO : std_logic;
-- AES
signal aes_mack : std_logic;
-- Address decoder
signal stb_IO : std_logic;
signal stb_IOmod : std_logic_vector (CNumOfSlaves-1 downto 0);
signal ram_ce : std_logic;
signal slv_cpuwait : std_logic;
-- Memory i/f
signal mem_ramadr : std_logic_vector (15 downto 0);
signal mem_ram_dbus_in : std_logic_vector (7 downto 0);
signal mem_ram_dbus_out : std_logic_vector (7 downto 0);
signal mem_ramwe : std_logic;
signal mem_ramre : std_logic;
-- RAM
signal ram_ramwe : std_logic;
-- nrst
--signal nrst : std_logic; --Comment this to connect reset to an external pushbutton.
-- ############################## Signals connected directly to the I/O registers ################################
-- PortA
signal porta_dbusout : std_logic_vector (7 downto 0);
signal porta_out_en : std_logic;
-- PortB
signal portb_dbusout : std_logic_vector (7 downto 0);
signal portb_out_en : std_logic;
-- PortC
signal portc_dbusout : std_logic_vector (7 downto 0);
signal portc_out_en : std_logic;
-- PortD
signal portd_dbusout : std_logic_vector (7 downto 0);
signal portd_out_en : std_logic;
-- PortE
signal porte_dbusout : std_logic_vector (7 downto 0);
signal porte_out_en : std_logic;
-- PortF
signal portf_dbusout : std_logic_vector (7 downto 0);
signal portf_out_en : std_logic;
-- Timer/Counter
signal tc_dbusout : std_logic_vector (7 downto 0);
signal tc_out_en : std_logic;
-- Ext IRQ Controller
signal extirq_dbusout : std_logic_vector (7 downto 0);
signal extirq_out_en : std_logic;
signal ext_irqlines : std_logic_vector(7 downto 0);
-- UART
signal uart_dbusout : std_logic_vector (7 downto 0);
signal uart_out_en : std_logic;
-- SPI
constant c_spi_slvs_num : integer := 1;
--signal spi_misoi : std_logic;
signal spi_mosii : std_logic;
signal spi_scki : std_logic;
signal spi_ss_b : std_logic;
signal spi_misoo : std_logic;
--signal spi_mosio : std_logic;
--signal spi_scko : std_logic;
signal spi_spe : std_logic;
signal spi_spimaster : std_logic;
signal spi_dbusout : std_logic_vector (7 downto 0);
signal spi_out_en : std_logic;
-- Slave selects
signal spi_slv_sel_n : std_logic_vector(c_spi_slvs_num-1 downto 0);
-- SPI
-- ###############################################################################################################
-- ############################## Define Signals for User Cores ##################################################
-- Example Core - - core9
--signal core9_input_sig : std_logic_vector(1 downto 0); --Define a signal for the inputs.
-- ###############################################################################################################
begin
-- Added for Synopsys compatibility
gnd <= '0';
vcc <= '1';
-- Added for Synopsys compatibility
--nrst <= '1'; --Comment this to connect reset to an external pushbutton.
core_inst <= pm_dout;
--Signals to connect peripherals controlled from Generics to the physical ports
-- ****************** User Cores - Instantiate User Cores Here **************************
-- ****************** END User Cores - Instantiate User Cores Here **************************
-- Unused IRQ lines
--core_irqlines(7 downto 4) <= ( others => '0');
--core_irqlines(3 downto 0) <= ( others => '0');
core_irqlines(13 downto 10) <= ( others => '0');
--core_irqlines(16) <= '0'; --now used by SPI
core_irqlines(22 downto 20) <= ( others => '0');
-- ************************
-- Unused out_en
io_port_out_en(11 to 15) <= (others => '0');
io_port_out(11 to 15) <= (others => (others => '0'));
AVR_Core_Inst:component AVR_Core port map(
--Clock and reset
cp2 => core_cp2,
cp2en => vcc,
ireset => core_ireset,
-- JTAG OCD support
valid_instr => open,
insert_nop => gnd,
block_irq => gnd,
change_flow => open,
-- Program Memory
pc => core_pc,
inst => core_inst,
-- I/O control
adr => core_adr,
iore => core_iore,
iowe => core_iowe,
-- Data memory control
ramadr => core_ramadr,
ramre => core_ramre,
ramwe => core_ramwe,
cpuwait => core_cpuwait,
-- Data paths
dbusin => core_dbusin,
dbusout => core_dbusout,
-- Interrupts
irqlines => core_irqlines,
irqack => core_irqack,
irqackad => core_irqackad,
--Sleep Control
sleepi => sleepi,
irqok => irqok,
globint => globint,
--Watchdog
wdri => core_wdri);
RAM_Data_Register:component RAMDataReg port map(
ireset => core_ireset,
cp2 => clk16M, -- clk,
cpuwait => core_cpuwait,
RAMDataIn => core_dbusout,
RAMDataOut => ram_din
);
EXT_MUX:component external_mux port map(
ramre => mem_ramre, -- ramre output of the arbiter and multiplexor
dbus_out => core_dbusin, -- Data input of the core
ram_data_out => mem_mux_out, -- Data output of the RAM mux(RAM or memory located I/O)
io_port_bus => io_port_out, -- Data outputs of the I/O
io_port_en_bus => io_port_out_en, -- Out enable outputs of I/O
irqack => core_irqack,
irqackad => core_irqackad,
ind_irq_ack => ind_irq_ack -- Individual interrupt acknolege for the peripheral
);
-- ****************** PORTA **************************
PORTA_Impl:if CImplPORTA generate
PORTA_COMP:component pport
generic map(PPortNum => 0)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porta_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porta_out_en,
-- External connection
portx => PortAReg,
ddrx => DDRAReg,
pinx => portain,
irqlines => open);
-- PORTA connection to the external multiplexer
io_port_out(0) <= porta_dbusout;
io_port_out_en(0) <= porta_out_en;
---- Tri-state control for PORTA
--PortAZCtrl:for i in porta'range generate
--porta(i) <= PortAReg(i) when DDRAReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTA
PortAZCtrl:for i in portaout'range generate
portaout(i) <= PortAReg(i) when DDRAReg(i)='1' else '0';
end generate;
end generate;
PORTA_Not_Impl:if not CImplPORTA generate
portaout <= (others => '0');
end generate;
-- ****************** PORTB **************************
PORTB_Impl:if CImplPORTB generate
PORTB_COMP:component pport
generic map (PPortNum => 1)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portb_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portb_out_en,
-- External connection
portx => PortBReg,
ddrx => DDRBReg,
pinx => portbin,
irqlines => ext_irqlines);
-- PORTB connection to the external multiplexer
io_port_out(1) <= portb_dbusout;
io_port_out_en(1) <= portb_out_en;
---- Tri-state control for PORTB
--PortBZCtrl:for i in portb'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTB
PortBZCtrl:for i in portbout'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
portbout(i) <= PortBReg(i) when DDRBReg(i)='1' else '0';
end generate;
end generate;
PORTB_Not_Impl:if not CImplPORTB generate
portbout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTC **************************
PORTC_Impl:if CImplPORTC generate
PORTC_COMP:component pport
generic map(PPortNum => 2)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portc_out_en,
-- External connection
portx => PortCReg,
ddrx => DDRCReg,
pinx => portc,
irqlines => open);
-- PORTC connection to the external multiplexer
io_port_out(5) <= portc_dbusout;
io_port_out_en(5) <= portc_out_en;
---- Tri-state control for PORTC
--PortCZCtrl:for i in portc'range generate
--portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTC
PortCZCtrl:for i in portc'range generate
portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
end generate;
end generate;
PORTC_Not_Impl:if not CImplPORTC generate
portc <= (others => 'Z');
end generate;
-- ****************** PORTD **************************
PORTD_Impl:if CImplPORTD generate
PORTD_COMP:component pport
generic map (PPortNum => 3)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portd_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portd_out_en,
-- External connection
portx => PortDReg,
ddrx => DDRDReg,
pinx => portdin,
irqlines => open);
-- PORTD connection to the external multiplexer
io_port_out(6) <= portd_dbusout;
io_port_out_en(6) <= portd_out_en;
---- Tri-state control for PORTD
--PortDZCtrl:for i in portd'range generate
--portd(i) <= PortDReg(i) when DDRDReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTD
PortDZCtrl:for i in portdout'range generate
portdout(i) <= PortDReg(i) when DDRDReg(i)='1' else '0';
end generate;
end generate;
PORTD_Not_Impl:if not CImplPORTD generate
portdout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTE **************************
PORTE_Impl:if CImplPORTE generate
PORTE_COMP:component pport
generic map(PPortNum => 4)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porte_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porte_out_en,
-- External connection
portx => PortEReg,
ddrx => DDREReg,
pinx => portein,
irqlines => open);
-- PORTE connection to the external multiplexer
io_port_out(7) <= porte_dbusout;
io_port_out_en(7) <= porte_out_en;
---- Tri-state control for PORTE
--PortEZCtrl:for i in porte'range generate
--porte(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTE
PortEZCtrl:for i in porteout'range generate
porteout(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
end generate;
end generate;
PORTE_Not_Impl:if not CImplPORTE generate
porteout <= (others => 'Z');
end generate;
-- ****************** PORTF **************************
PORTF_Impl:if CImplPORTF generate
PORTF_COMP:component pport
generic map (PPortNum => 5)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portf_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portf_out_en,
-- External connection
portx => PortFReg,
ddrx => DDRFReg,
pinx => portf,
irqlines => open);
-- PORTF connection to the external multiplexer
io_port_out(8) <= portf_dbusout;
io_port_out_en(8) <= portf_out_en;
-- Tri-state control for PORTF
PortFZCtrl:for i in portf'range generate
portf(i) <= PortFReg(i) when DDRFReg(i)='1' else 'Z';
end generate;
end generate;
PORTF_Not_Impl:if not CImplPORTF generate
portf <= (others => 'Z');
end generate;
-- ************************************************
--****************** External IRQ Controller**************************
ExtIRQ_Impl:if CImplExtIRQ generate
ExtIRQ_Inst:component ExtIRQ_Controller port map(
-- AVR Control
nReset => core_ireset,
clk => clk16M, -- clk,
clken => vcc,
irq_clken => vcc,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => extirq_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => extirq_out_en,
------------------------------------------------
extpins => ext_irqlines,
INTx => core_irqlines(7 downto 0));
-- ExtIRQ connection to the external multiplexer
io_port_out(10) <= extirq_dbusout;
io_port_out_en(10) <= extirq_out_en;
end generate;
--****************** Timer/Counter **************************
TmrCnt_Impl:if CImplTmrCnt generate
TmrCnt_Inst:component Timer_Counter port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
cp2en => vcc,
tmr_cp2en => vcc,
stopped_mode => gnd,
tmr_running => gnd,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => tc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => tc_out_en,
-- External inputs/outputs
EXT1 => gnd,
EXT2 => gnd,
OC0_PWM0 => open,
OC1A_PWM1A => open,
OC1B_PWM1B => open,
OC2_PWM2 => open,
-- Interrupt related signals
TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020)
TC0OvfIRQ_Ack => ind_irq_ack(15),
TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E)
TC0CmpIRQ_Ack => ind_irq_ack(14),
TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014)
TC2OvfIRQ_Ack => ind_irq_ack(9),
TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012)
TC2CmpIRQ_Ack => ind_irq_ack(8),
TC1OvfIRQ => open,
TC1OvfIRQ_Ack => gnd,
TC1CmpAIRQ => open,
TC1CmpAIRQ_Ack => gnd,
TC1CmpBIRQ => open,
TC1CmpBIRQ_Ack => gnd,
TC1ICIRQ => open,
TC1ICIRQ_Ack => gnd,
PWM0bit => open,
PWM10bit => open,
PWM11bit => open,
PWM2bit => open);
-- Timer/Counter connection to the external multiplexer
io_port_out(4) <= tc_dbusout;
io_port_out_en(4) <= tc_out_en;
end generate;
-- Watchdog is not implemented
wdtmout <= '0';
-- Reset generator
ResetGenerator_Inst:component ResetGenerator port map(
-- Clock inputs
cp2 => clk16M, -- clk,
cp64m => gnd,
-- Reset inputs
nrst => nrst,
npwrrst => vcc,
wdovf => wdtmout,
jtagrst => JTAG_Rst,
-- Reset outputs
nrst_cp2 => core_ireset,
nrst_cp64m => nrst_cp64m_tmp,
nrst_clksw => nrst_clksw
);
ClockGatingDis:if not CImplClockSw generate
core_cp2 <= clk16M;
end generate;
-- ********************** JTAG and memory **********************************************
ram_cp2_n <= not clk16M;
---- Data memory(8-bit)
DM_Inst : entity work.XDM
generic map (
WIDTH => 8,
SIZE => CDATAMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(f_log2(CDATAMEMSIZE) - 1 downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst : entity work.XPM
generic map (
WIDTH => 16,
SIZE => CPROGMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(f_log2(CPROGMEMSIZE) - 1 downto 0),
din => pm_din,
dout => pm_dout,
we => pm_l_we
);
-- ********************** JTAG and memory **********************************************
-- Sleep mode is not implemented
sleep_mode <= '0';
JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
-- JTAG related inputs/outputs
TRSTn => TRSTn, -- Optional
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO_Out,
TDO_OE => TDO_OE,
-- From the core
PC => core_pc,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr,
-- CPU reset
jtag_rst => JTAG_Rst
);
-- JTAG OCD module connection to the external multiplexer
io_port_out(3) <= (others => '0');
io_port_out_en(3) <= gnd;
TDO <= TDO_Out when TDO_OE='1' else 'Z';
-- *******************************************************************************************************
-- DMA, Memory decoder, ...
-- *******************************************************************************************************
-- ****************** SPI **************************
spi_is_used:if CImplSPI generate
spi_mod_inst:component spi_mod port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => spi_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => spi_out_en,
-- SPI i/f
misoi => spi_misoi,
mosii => spi_mosii,
scki => spi_scki,
ss_b => spi_ss_b,
misoo => spi_misoo,
mosio => spi_mosio,
scko => spi_scko,
spe => spi_spe,
spimaster => spi_spimaster,
-- IRQ
spiirq => core_irqlines(16),
spiack => ind_irq_ack(16),
-- Slave Programming Mode
por => gnd,
spiextload => gnd,
spidwrite => open,
spiload => open
);
-- SPI connection to the external multiplexer
io_port_out(9) <= spi_dbusout;
io_port_out_en(9) <= spi_out_en;
-- Pads
--mosi_SIG <= spi_mosio when (spi_spimaster='1') else 'Z';
--miso_SIG <= spi_misoo when (spi_spimaster='0') else 'Z';
--sck_SIG <= spi_scko when (spi_spimaster='1') else 'Z';
--
--spi_misoi <= miso_SIG;
--spi_mosii <= mosi_SIG;
--spi_scki <= sck_SIG;
spi_ss_b <= vcc;
-- Pads
spi_slv_sel_inst:component spi_slv_sel generic map(num_of_slvs => c_spi_slvs_num)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => open,
iore => core_iore,
iowe => core_iowe,
out_en => open,
-- Output
slv_sel_n => spi_slv_sel_n
);
end generate;
spi_cs_n <= spi_slv_sel_n(0);
no_spi:if not CImplSPI generate
--mosi_SIG <= 'Z';
--miso_SIG <= 'Z';
--sck_SIG <= 'Z';
--io_slv_out(1).dbusout <= (others => '0');
--io_slv_out(1).out_en <= gnd;
spi_slv_sel_n <= (others => '1');
end generate;
uart_Inst:component uart port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => uart_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => uart_out_en,
-- UART
rxd => rxd,
rx_en => open,
txd => txd,
tx_en => open,
-- IRQ
txcirq => core_irqlines(19),
txc_irqack => ind_irq_ack(19),
udreirq => core_irqlines(18),
rxcirq => core_irqlines(17)
);
-- UART connection to the external multiplexer
io_port_out(2) <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;
-- Arbiter and mux
ArbiterAndMux_Inst:component ArbiterAndMux port map(
--Clock and reset
ireset => core_ireset,
cp2 => core_cp2,
-- Bus masters
busmin => busmin,
busmwait => busmwait,
-- Memory Address,Data and Control
ramadr => mem_ramadr,
ramdout => mem_ram_dbus_in,
ramre => mem_ramre,
ramwe => mem_ramwe,
cpuwait => slv_cpuwait
);
-- cpuwait
slv_cpuwait <= '0';
-- Core connection
busmin(0).ramadr <= core_ramadr;
busmin(0).dout <= ram_din; -- !!!
busmin(0).ramre <= core_ramre;
busmin(0).ramwe <= core_ramwe;
core_cpuwait <= busmwait(0);
-- UART DMA connection
busmin(1).ramadr <= (others => '0');
busmin(1).dout <= (others => '0'); -- !!!
busmin(1).ramre <= gnd;
busmin(1).ramwe <= gnd;
udma_mack <= not busmwait(1);
-- AES DMA connection
busmin(2).ramadr <= (others => '0');
busmin(2).dout <= (others => '0');
busmin(2).ramre <= gnd;
busmin(2).ramwe <= gnd;
aes_mack <= not busmwait(2);
-- UART DMA slave part
slv_outs(0).dout <= (others => '0');
slv_outs(0).out_en <= gnd;
-- AES DMA slave part
slv_outs(1).dout <= (others => '0');
slv_outs(1).out_en <= gnd;
-- Memory read mux
MemRdMux_inst:component MemRdMux port map(
slv_outs => slv_outs,
ram_sel => ram_sel, -- Data RAM selection(optional input)
ram_dout => mem_ram_dbus_out, -- Data memory output (From RAM)
dout => mem_mux_out -- Data output (To the core and other bus masters)
);
-- Address decoder
RAMAdrDcd_Inst:component RAMAdrDcd port map(
ramadr => mem_ramadr,
ramre => mem_ramre,
ramwe => mem_ramwe,
-- Memory mapped I/O i/f
stb_IO => stb_IO,
stb_IOmod => stb_IOmod,
-- Data memory i/f
ram_we => ram_ramwe,
ram_ce => ram_ce,
ram_sel => ram_sel
);
end Struct;
|
-- Samples the line and stores it in 3 rams
-- This is then sent in a 3x3 array to a filter
-- Copyright Erik Zachrisson [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity LineSampler is
generic (
DataW : positive;
Buffers : positive;
OutRes : positive
);
port (
Clk : in bit1;
RstN : in bit1;
--
Vsync : in bit1;
RdAddr : out word(bits(FrameW)-1 downto 0);
--
PixelIn : in word(DataW-1 downto 0);
PixelInVal : in bit1;
--
PixelOut : out PixVec2D(OutRes-1 downto 0);
PixelOutVal : out bit1
);
end entity;
architecture rtl of LineSampler is
signal Addr_N, Addr_D : word(FrameWW-1 downto 0);
type AddrArr is array (natural range <>) of word(Buffers-1 downto 0);
signal PixArr_N, PixArr_D : PixVec2D(3-1 downto 0);
--
signal LineCnt_N, LineCnt_D : word(bits(Buffers)-1 downto 0);
signal WrEn : word(Buffers-1 downto 0);
type BuffArr is array (natural range <>) of word(PixelW-1 downto 0);
signal RamOut : BuffArr(Buffers-1 downto 0);
signal PixelVal_D : bit1;
function CalcLine(CurLine : word; Offs : natural) return natural is
begin
return ((conv_integer(CurLine) + Offs + 1) mod Buffers);
end function;
begin
SyncRstProc : process (RstN, Clk)
begin
if RstN = '0' then
PixelVal_D <= '0';
elsif rising_edge(Clk) then
PixelVal_D <= PixelInVal;
end if;
end process;
SyncNoRstProc : process (Clk)
begin
if rising_edge(Clk) then
LineCnt_D <= LineCnt_N;
Addr_D <= Addr_N;
PixArr_D <= PixArr_N;
if Vsync = '1' then
LineCnt_D <= (others => '0');
Addr_D <= (others => '0');
PixArr_D <= (others => (others => (others => '0')));
end if;
end if;
end process;
AsyncProc : process (LineCnt_D, Addr_D, PixArr_D, PixelInVal, RamOut)
begin
LineCnt_N <= LineCnt_D;
Addr_N <= Addr_D;
PixArr_N <= PixArr_D;
if PixelInVal = '1' then
Addr_N <= Addr_D + 1;
if Addr_D + 1 = FrameW then
Addr_N <= (others => '0');
LineCnt_N <= LineCnt_D + 1;
if LineCnt_D + 1 = Buffers then
LineCnt_N <= (others => '0');
end if;
end if;
-- Shift all entries one step to the left
for i in 0 to OutRes-1 loop
PixArr_N(i)(0) <= PixArr_D(i)(1);
PixArr_N(i)(1) <= PixArr_D(i)(2);
PixArr_N(i)(2) <= RamOut(CalcLine(LineCnt_D, i));
-- Clear buffer on the end of the line
-- FIXME: is this necessary?
end loop;
end if;
end process;
OneHotProc : process (LineCnt_D, PixelInVal)
begin
WrEn <= (others => '0');
if PixelInVal = '1' then
WrEn(conv_integer(LineCnt_D)) <= '1';
end if;
end process;
Ram : for i in 0 to Buffers-1 generate
R : entity work.LineSampler1pRAM
port map (
Clock => Clk,
Data => PixelIn,
WrEn => WrEn(i),
address => Addr_D,
--
q => RamOut(i)
);
end generate;
AddrFeed : RdAddr <= Addr_D;
PixelOutValFeed : PixelOutVal <= PixelVal_D;
PixelOutFeed : PixelOut <= PixArr_D;
end architecture rtl;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
slave_wait <= dscl_oen and not sSCL;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif ( (cnt = 0) or (ena = '0') ) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= scl_i;
sSDA <= sda_i;
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen);
else
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
-- $Id: tb_nexys2_core.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_core - sim
-- Description: Test bench for nexys2 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_nexys2_core is
port (
I_SWI : out slv8; -- n2 switches
I_BTN : out slv4; -- n2 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys2_core;
architecture sim of tb_nexys2_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
-- NEED RESULT: ARCH00688: Allocators with static scalar qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00688
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (3)
-- 7.3.6 (4)
-- 7.3.6 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00688)
-- ENT00688_Test_Bench(ARCH00688_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00688 of E00000 is
begin
process
variable correct : boolean := true ;
type a_boolean is access boolean ;
variable va_boolean_1, va_boolean_2 : a_boolean
:= new boolean ;
type a_bit is access bit ;
variable va_bit_1, va_bit_2 : a_bit
:= new bit ;
type a_severity_level is access severity_level ;
variable va_severity_level_1, va_severity_level_2 : a_severity_level
:= new severity_level ;
type a_character is access character ;
variable va_character_1, va_character_2 : a_character
:= new character ;
type a_t_enum1 is access t_enum1 ;
variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1
:= new t_enum1 ;
type a_st_enum1 is access st_enum1 ;
variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1
:= new st_enum1 ;
type a_integer is access integer ;
variable va_integer_1, va_integer_2 : a_integer
:= new integer ;
type a_t_int1 is access t_int1 ;
variable va_t_int1_1, va_t_int1_2 : a_t_int1
:= new t_int1 ;
type a_st_int1 is access st_int1 ;
variable va_st_int1_1, va_st_int1_2 : a_st_int1
:= new st_int1 ;
type a_time is access time ;
variable va_time_1, va_time_2 : a_time
:= new time ;
type a_t_phys1 is access t_phys1 ;
variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1
:= new t_phys1 ;
type a_st_phys1 is access st_phys1 ;
variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1
:= new st_phys1 ;
type a_real is access real ;
variable va_real_1, va_real_2 : a_real
:= new real ;
type a_t_real1 is access t_real1 ;
variable va_t_real1_1, va_t_real1_2 : a_t_real1
:= new t_real1 ;
type a_st_real1 is access st_real1 ;
variable va_st_real1_1, va_st_real1_2 : a_st_real1
:= new st_real1 ;
begin
va_boolean_1 := new boolean ' (c_boolean_1) ;
va_bit_1 := new bit ' (c_bit_1) ;
va_severity_level_1 := new severity_level ' (c_severity_level_1) ;
va_character_1 := new character ' (c_character_1) ;
va_t_enum1_1 := new t_enum1 ' (c_t_enum1_1) ;
va_st_enum1_1 := new st_enum1 ' (c_st_enum1_1) ;
va_integer_1 := new integer ' (c_integer_1) ;
va_t_int1_1 := new t_int1 ' (c_t_int1_1) ;
va_st_int1_1 := new st_int1 ' (c_st_int1_1) ;
va_time_1 := new time ' (c_time_1) ;
va_t_phys1_1 := new t_phys1 ' (c_t_phys1_1) ;
va_st_phys1_1 := new st_phys1 ' (c_st_phys1_1) ;
va_real_1 := new real ' (c_real_1) ;
va_t_real1_1 := new t_real1 ' (c_t_real1_1) ;
va_st_real1_1 := new st_real1 ' (c_st_real1_1) ;
correct := correct and
va_boolean_1.all = c_boolean_1 ;
correct := correct and
va_bit_1.all = c_bit_1 ;
correct := correct and
va_severity_level_1.all = c_severity_level_1 ;
correct := correct and
va_character_1.all = c_character_1 ;
correct := correct and
va_t_enum1_1.all = c_t_enum1_1 ;
correct := correct and
va_st_enum1_1.all = c_st_enum1_1 ;
correct := correct and
va_integer_1.all = c_integer_1 ;
correct := correct and
va_t_int1_1.all = c_t_int1_1 ;
correct := correct and
va_st_int1_1.all = c_st_int1_1 ;
correct := correct and
va_time_1.all = c_time_1 ;
correct := correct and
va_t_phys1_1.all = c_t_phys1_1 ;
correct := correct and
va_st_phys1_1.all = c_st_phys1_1 ;
correct := correct and
va_real_1.all = c_real_1 ;
correct := correct and
va_t_real1_1.all = c_t_real1_1 ;
correct := correct and
va_st_real1_1.all = c_st_real1_1 ;
test_report ( "ARCH00688" ,
"Allocators with static scalar qualified expression" ,
correct) ;
wait ;
end process ;
end ARCH00688 ;
--
entity ENT00688_Test_Bench is
end ENT00688_Test_Bench ;
--
architecture ARCH00688_Test_Bench of ENT00688_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00688 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00688_Test_Bench ;
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