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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2306.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02306ent IS
END c07s02b07x00p01n01i02306ent;
ARCHITECTURE c07s02b07x00p01n01i02306arch OF c07s02b07x00p01n01i02306ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
variable x : array_one;
variable z : integer;
BEGIN
z := abs(x); -- Failure_here
-- abs is not defined for array types.
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02306 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02306arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2306.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02306ent IS
END c07s02b07x00p01n01i02306ent;
ARCHITECTURE c07s02b07x00p01n01i02306arch OF c07s02b07x00p01n01i02306ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
variable x : array_one;
variable z : integer;
BEGIN
z := abs(x); -- Failure_here
-- abs is not defined for array types.
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02306 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02306arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2306.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02306ent IS
END c07s02b07x00p01n01i02306ent;
ARCHITECTURE c07s02b07x00p01n01i02306arch OF c07s02b07x00p01n01i02306ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
variable x : array_one;
variable z : integer;
BEGIN
z := abs(x); -- Failure_here
-- abs is not defined for array types.
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02306 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02306arch;
|
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, string'("two"));
writeline(output, l);
write(l, string'("hello"), left, 10);
write(l, '|');
write(l, string'("world"), right, 10);
writeline(output, l);
write(l, bit'( '0' ), left, 4);
write(l, bit_vector'("0110101"));
writeline(output, l);
write(l, true);
writeline(output, l);
write(l, 10 ns);
writeline(output, l);
write(l, 50 ns, field => 20, justified => right, unit => us);
writeline(output, l);
write(l, 1.234);
writeline(output, l);
write(l, 1.234, digits => 1);
writeline(output, l);
write(l, 1.234567, digits => 4);
writeline(output, l);
deallocate(l);
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu_pkg is
-----------------------------------------------------------------------------
-- tool chain selection (because no suppoprt of 'val attritube in ISE XST)
-----------------------------------------------------------------------------
constant ISE_TOOL : boolean := true; -- true = ISE XST
-- false = other synthesizer (e.g. Vivado)
-- system clock frequency in Hz
constant CF : natural := 50_000_000; -- 50 MHz
-- prescaler factor
constant DUR_SCALE : natural := 5_000; -- constant scale factor -> Tclk 1ms
constant NCO_SCALE : natural := 5; -- constant scale factor -> Tclk 1ms
-----------------------------------------------------------------------------
-- Helper functions (prototypes)
-----------------------------------------------------------------------------
-- std_logic_vector(to_signed(i,w))
function i2slv(i : integer; w : positive) return std_logic_vector;
-- std_logic_vector(to_unsigned(n,w))
function n2slv(n : natural; w : positive) return std_logic_vector;
-- form instruction word for NOP instruction
function iw_nop return std_logic_vector;
-----------------------------------------------------------------------------
-- design parameters: Memory Map
-----------------------------------------------------------------------------
-- bus architecture parameters
constant DW : natural range 4 to 64 := 16; -- data word width
constant AW : natural range 2 to 64 := 10; -- total address width
constant AWH : natural range 1 to 64 := 4; -- high address width
constant AWL : natural range 1 to 64 := AW-AWH; -- low address width
-- fmc rom parameters
constant FMC_NUM_CHN: natural range 1 to 8 := 8; -- # of FMC channels
constant FMC_ROM_AW : natural range 1 to 10 := 10; --FMC_ROM address width
constant FMC_ROM_DW : natural range 1 to 20 := 20; --FMC_ROM data word width
constant FMC_DUR_WW : natural range 1 to 16 := 14; --FMC_ROM tone duration word width
constant FMC_TON_WW : natural range 1 to 16 := 6; --FMC_ROM tone duration word width
constant FMC_LAST_TONE : unsigned(FMC_DUR_WW-1 downto 0) := (others => '1'); -- last-tone indicator
-- memory map
type t_bus_slave is (ROM, RAM, GPIO, FMC, TIM, UART); -- list of bus slaves
type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0);
constant BA : t_ba := ( -- full base addresses
ROM => "0-" & "----" & "----",
RAM => "10" & "----" & "----",
GPIO => "11" & "00--" & "----",
FMC => "11" & "01--" & "----",
TIM => "11" & "10--" & "----",
UART => "11" & "11--" & "----"
);
type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0);
constant HBA : t_hba := ( -- high base address for decoding
ROM => BA(ROM) (AW-1 downto AW-AWH),
RAM => BA(RAM) (AW-1 downto AW-AWH),
GPIO => BA(GPIO)(AW-1 downto AW-AWH),
FMC => BA(FMC) (AW-1 downto AW-AWH),
TIM => BA(TIM) (AW-1 downto AW-AWH),
UART => BA(UART)(AW-1 downto AW-AWH)
);
-- Relative Register Addresses of Peripherals
-- GPIO
constant c_addr_gpio_data_in : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL);
constant c_addr_gpio_data_out : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL);
constant c_addr_gpio_out_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 2, AWL);
type t_gpio_addr_sel is (none, gpio_data_in, gpio_data_out, gpio_enb);
-- FMC
constant N_FMC : natural range 1 to 8 := 8; --# of FMC channels
constant c_addr_fmc_chn_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL);
constant c_addr_fmc_tmp_ctrl : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL);
type t_fmc_addr_sel is (none, fmc_chn_enb, fmc_tmp_ctrl);
-- TIM
-- UART
-----------------------------------------------------------------------------
-- design parameters: CPU Instructions
-----------------------------------------------------------------------------
-- CPU instruction set
-- Note: Defining the OPcode in the way shown below, allows assembler-style
-- programming with mnemonics rather than machine coding (see rom.vhd).
constant OPCW : natural range 1 to DW := 5; -- Opcode word width
constant OPAW : natural range 1 to DW := 4; -- ALU operation word width
constant IOWW : natural range 1 to DW := 8; -- immediate operand word width
type t_instr is (add, sub, andi, ori, xori, slai, srai, mov,
ld, st,
addil, addih, setil, setih,
jmp, bne, bge, blt, bca, bov,
nop);
-- Instructions targeted at the ALU are defined by means of a sub-type.
-- This allows changing the opcode of instructions without having to
-- modify the source code of the ALU.
subtype t_alu_instr is t_instr range add to mov;
type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0);
constant OPC : t_opcode := ( -- OPcode
-- ALU operations -------------------------------
add => "00000", -- 0: addition
sub => "00001", -- 1: subtraction
andi => "00010", -- 2: bit-wise AND
ori => "00011", -- 3: bit-wise OR
xori => "00100", -- 4: bit-wise XOR
slai => "00101", -- 5: shift-left arithmetically
srai => "00110", -- 6: shift-right arithmetically
mov => "00111", -- 7: move between register
-- Immediate Operands ---------------------------
addil => "01100", -- 12: add imm. constant low
addih => "01101", -- 13: add imm. constant high
setil => "01110", -- 14: set imm. constant low
setih => "01111", -- 15: set imm. constant high
-- Memory load/store ----------------------------
ld => "10000", -- 16: load from memory
st => "10001", -- 17: store to memory
-- Jump/Branch ----------------------------------
jmp => "11000", -- 24: absolute jump
bne => "11001", -- 25: branch if not equal (not Z)
bge => "11010", -- 26: branch if greater/equal (not N or Z)
blt => "11011", -- 27: branch if less than (N)
bca => "11100", -- 28: branch if carry set (C)
bov => "11101", -- 29: branch if overflow set (O)
-- Others ---------------------------------------
nop => "11111" -- 31: no operation
);
type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow)
type t_flag_arr is array (t_flags) of std_logic;
-- register block
constant RIDW : natural range 1 to DW := 3; -- register ID word width
type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0);
constant reg : t_regid := ("000","001","010","011","100","101","110","111");
type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0);
-- CPU address generation
type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi
type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions
-----------------------------------------------------------------------------
-- global types
-----------------------------------------------------------------------------
-- Master bus interface -----------------------------------------------------
type t_bus2cpu is record
data : std_logic_vector(DW-1 downto 0);
end record;
type t_cpu2bus is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
rd_enb : std_logic;
wr_enb : std_logic;
end record;
-- Read-only slave bus interface -------------------------------------------
type t_bus2ros is record
addr : std_logic_vector(AWL-1 downto 0);
rd_enb : std_logic;
end record;
type t_ros2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- read/write slave bus interface -------------------------------------------
type t_bus2rws is record
addr : std_logic_vector(AWL-1 downto 0);
data : std_logic_vector(DW-1 downto 0);
rd_enb : std_logic; -- use of this signal is optional, depending on slave
wr_enb : std_logic;
end record;
type t_rws2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- CPU internal types
-----------------------------------------------------------------------------
-- Control Unit / Register Block interface ----------------------------------
type t_ctr2reg is record
src1 : std_logic_vector(RIDW-1 downto 0);
src2 : std_logic_vector(RIDW-1 downto 0);
dest : std_logic_vector(RIDW-1 downto 0);
enb_res : std_logic;
data : std_logic_vector(DW-1 downto 0);
enb_data : std_logic;
end record;
type t_reg2ctr is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
end record;
-- Control Unit / Program Counter interface --------------------------------
type t_ctr2prc is record
enb : std_logic;
mode : t_pc_mode;
addr : std_logic_vector(AW-1 downto 0);
end record;
type t_prc2ctr is record
pc : std_logic_vector(AW-1 downto 0);
exc : t_addr_exc;
end record;
-- Control Unit / ALU interface ---------------------------------------------
type t_ctr2alu is record
op : std_logic_vector(OPAW-1 downto 0); -- operation
imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand
enb : std_logic; -- enable flag update
end record;
type t_alu2ctr is record
flag : t_flag_arr;
end record;
end package mcu_pkg;
package body mcu_pkg is
-----------------------------------------------------------------------------
-- Function Implementations
-----------------------------------------------------------------------------
function i2slv(i : integer;w : positive) return std_logic_vector is
begin
return std_logic_vector(to_signed(i,w));
end function i2slv;
function n2slv(n : natural;w : positive) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n,w));
end function n2slv;
function iw_nop return std_logic_vector is
variable v : std_logic_vector(DW-1 downto 0);
begin
for k in DW-1 downto DW-OPCW loop
v(k) := OPC(nop)(k-DW+OPCW);
end loop;
for k in DW-OPCW-1 downto 0 loop
v(k) := '0';
end loop;
return v;
end function iw_nop;
end package body mcu_pkg;
|
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7200)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
UfKdpckab3affGFi+2eLUnCKsj7bFfZwk5q86NecNln9ikBsEghKOL3p+GYfg3eferq51dNHCizd
ai/6bIG/CQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7200)
`protect data_block
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`protect end_protected
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2004/04/06 10:50:32 wig Exp $
-- $Date: 2004/04/06 10:50:32 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:32 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
cgs_ramclk : out std_ulogic;
nreset : out std_ulogic;
si_vclkx2 : in std_ulogic;
tmu_dac_reset : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
entity xtc_top_sdram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
-- DMA
dmawbi: in wb_mosi_type;
dmawbo: out wb_miso_type;
-- SDRAM signals
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity;
architecture behave of xtc_top_sdram is
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_tago: std_logic_vector(31 downto 0);
signal wb_tagi: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_stall: std_logic;
--signal rstreq: std_logic;
component sdram_ctrl is
generic (
HIGH_BIT: integer := 24
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
dbg: out memory_debug_type;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component;
signal wbo,romwbo,bootwbo,sdramorbootwbo,ramwbo,piowbo,sdram_wbo,cpu_sdram_wbo: wb_mosi_type;
signal wbi,romwbi,bootwbi,sdramorbootwbi,ramwbi,piowbi,sdram_wbi,cpu_sdram_wbi: wb_miso_type;
signal edbg: memory_debug_type;
begin
sdram_wbi.err <= '0';
sdram_wbi.int <= '0';
cpu: entity work.xtc
port map (
wb_syscon => wb_syscon,
-- Master wishbone interface
wbo => ramwbo,
wbi => ramwbi,
-- ROM wb interface
romwbo => romwbo,
romwbi => romwbi,
nmi => nmi,
nmiack => nmiack,
rstreq => rstreq,
edbg => edbg
);
data_mux_io: entity work.xtc_wbmux2
generic map (
select_line => 31,
address_high => 31,
address_low => 2
)
port map (
wb_syscon => wb_syscon,
-- Master
m_wbi => ramwbo,
m_wbo => ramwbi,
-- Slave 0 signals
s0_wbi => wbi,
s0_wbo => wbo,
-- Slave 0 signals
s1_wbi => piowbi,
s1_wbo => piowbo
);
dma_arb: entity work.wbarb2_1
port map (
wb_syscon => wb_syscon,
-- Master 0 signals
m0_wbi => cpu_sdram_wbo,
m0_wbo => cpu_sdram_wbi,
-- Master 1 signals
m1_wbi => dmawbi,
m1_wbo => dmawbo,
-- Slave signals
s0_wbi => sdram_wbi,
s0_wbo => sdram_wbo
);
--ramwbi.int <= iowbi.int;
i_d_arb: entity work.wbarb2_1
port map (
wb_syscon => wb_syscon,
-- Master 0 signals
m0_wbi => wbo,
m0_wbo => wbi,
-- Master 1 signals
m1_wbi => romwbo,
m1_wbo => romwbi,
-- Slave signals
s0_wbi => sdramorbootwbi,
s0_wbo => sdramorbootwbo
);
boot_sdram_mux: entity work.xtc_wbmux2
generic map (
select_line => 30,
address_high => 31,
address_low => 2
)
port map (
wb_syscon => wb_syscon,
-- Master
m_wbi => sdramorbootwbo,
m_wbo => sdramorbootwbi,
-- Slave 0 signals
s0_wbi => cpu_sdram_wbi,
s0_wbo => cpu_sdram_wbo,
-- Slave 0 signals
s1_wbi => bootwbi,
s1_wbo => bootwbo
);
bootrom: entity work.bootrom
port map (
syscon => wb_syscon,
wbi => bootwbo,
wbo => bootwbi
);
ioadaptor: entity work.wb_master_p_to_slave_np
port map (
syscon => wb_syscon,
mwbo => piowbi,
mwbi => piowbo,
swbi => iowbi,
swbo => iowbo
);
sdramcrtl_inst: entity work.sdram_ctrl
generic map (
HIGH_BIT => 22
)
port map (
wb_clk_i => wb_syscon.clk,
wb_rst_i => wb_syscon.rst,
wb_dat_o => sdram_wbi.dat,
wb_dat_i => sdram_wbo.dat,
wb_adr_i => sdram_wbo.adr,
wb_we_i => sdram_wbo.we,
wb_cyc_i => sdram_wbo.cyc,
wb_stb_i => sdram_wbo.stb,
wb_sel_i => sdram_wbo.sel,
wb_tag_i => sdram_wbo.tag,
wb_ack_o => sdram_wbi.ack,
wb_stall_o => sdram_wbi.stall,
wb_tag_o => sdram_wbi.tag,
dbg => edbg,
-- extra clocking
clk_off_3ns => clk_off_3ns,
-- SDRAM signals
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
entity clock_counter is
generic
(
f: integer := 50000000
);
port
(
clock_i: in std_logic;
clock_o: out std_logic
);
end entity;
architecture behavior of clock_counter is
begin
process (clock_i)
variable counter: integer := 0;
begin
if rising_edge(clock_i) then
if counter < f/2 then
counter := counter + 1;
clock_o <= '0';
elsif counter < f then
counter := counter + 1;
clock_o <= '1';
end if;
if counter = f then
counter := 0;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Codeword_Generator_1
-- Module Name: Controller_Codeword_Generator_1
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
--
-- This circuit is the state machine controller for Codeword_Generator_1 and
-- Codeword_Generator_n_m. The state machine is composed of a step to copy the
-- original message and another for multiplying the message by matrix A.
-- This matrix multiplication is designed for matrices composed of dyadic blocks.
-- The algorithm computes one dyadic matrix at time.
-- Each dyadic matrix is computed in a column wise strategy.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.00
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_codeword_generator_1 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
message_into_new_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end controller_codeword_generator_1;
architecture Behavioral of controller_codeword_generator_1 is
type State is (reset, load_counter, prepare_message, load_message, copy_message, last_message, write_last_message, prepare_counters_a, new_acc, calc_codeword_a, last_column_value_a, write_last_column_value_a, last_row_value_a, write_last_row_value_a, last_value_a, write_last_value_a, prepare_counters_b, load_acc, calc_codeword_b, last_column_value_b, write_last_column_value_b, last_row_value_b, write_last_row_value_b, last_value_b, write_last_value_b, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_counter =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_message =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_message =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when copy_message =>
if(limit_ctr_dyadic_row_q = '1' and limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
elsif(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
elsif(limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_message =>
if(limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when write_last_message =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_counters_a =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when new_acc =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when calc_codeword_a =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when last_row_value_a =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value_a =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_column_value_a =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value_a =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_value_a =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value_a =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when prepare_counters_b =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when calc_codeword_b =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when last_row_value_b =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value_b =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when last_column_value_b =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value_b =>
if(limit_ctr_address_codeword_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_value_b =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value_b =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when final =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '1';
when others =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end case;
end process;
NewState : process(actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= prepare_message;
when prepare_message =>
next_state <= load_message;
when load_message =>
next_state <= copy_message;
when copy_message =>
if(limit_ctr_address_message_q = '1') then
next_state <= last_message;
else
next_state <= copy_message;
end if;
when last_message =>
next_state <= write_last_message;
when write_last_message =>
next_state <= prepare_counters_a;
when prepare_counters_a =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_a;
else
next_state <= last_column_value_a;
end if;
else
next_state <= last_row_value_a;
end if;
else
next_state <= new_acc;
end if;
when new_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_a;
else
next_state <= last_column_value_a;
end if;
else
next_state <= last_row_value_a;
end if;
else
next_state <= calc_codeword_a;
end if;
when calc_codeword_a =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_a;
else
next_state <= last_column_value_a;
end if;
else
next_state <= last_row_value_a;
end if;
else
next_state <= calc_codeword_a;
end if;
when last_column_value_a =>
next_state <= write_last_column_value_a;
when write_last_column_value_a =>
next_state <= prepare_counters_a;
when last_row_value_a =>
next_state <= write_last_row_value_a;
when write_last_row_value_a =>
next_state <= prepare_counters_a;
when last_value_a =>
next_state <= write_last_value_a;
when write_last_value_a =>
next_state <= prepare_counters_b;
when prepare_counters_b =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_b;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_row_value_b;
end if;
else
next_state <= load_acc;
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_b;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_row_value_b;
end if;
else
next_state <= calc_codeword_b;
end if;
when calc_codeword_b =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_b;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_row_value_b;
end if;
else
next_state <= calc_codeword_b;
end if;
when last_column_value_b =>
next_state <= write_last_column_value_b;
when write_last_column_value_b =>
next_state <= prepare_counters_b;
when last_row_value_b =>
next_state <= write_last_row_value_b;
when write_last_row_value_b =>
next_state <= prepare_counters_b;
when last_value_b =>
next_state <= write_last_value_b;
when write_last_value_b =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
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`protect end_protected
|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect end_protected
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.serial_interface_defs.all;
entity serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end entity serial_interface;
-- not in book
architecture test of serial_interface is
begin
end architecture test;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.serial_interface_defs.all;
entity serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end entity serial_interface;
-- not in book
architecture test of serial_interface is
begin
end architecture test;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.serial_interface_defs.all;
entity serial_interface is
port ( clock_phi1, clock_phi2 : in std_logic;
serial_select : in std_logic;
reg_address : in reg_address_vector;
data : inout data_vector;
interrupt_request : out std_logic;
rx_serial_data : in std_logic;
tx_serial_data : out std_logic );
end entity serial_interface;
-- not in book
architecture test of serial_interface is
begin
end architecture test;
-- end not in book
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:44:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb888_to_g8_0_0 -prefix
-- system_rgb888_to_g8_0_0_ system_rgb888_to_g8_0_0_stub.vhdl
-- Design : system_rgb888_to_g8_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_to_g8_0_0 is
Port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_rgb888_to_g8_0_0;
architecture stub of system_rgb888_to_g8_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb888[23:0],g8[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_to_g8,Vivado 2016.4";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_9_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_9_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_9_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_9_e
--
architecture rtl of inst_9_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
ENTITY fx2_fifo_tb IS
END ENTITY;
ARCHITECTURE fx2_fifo_arch OF fx2_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fx2_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fx2_fifo_synth
fx2_fifo_synth_inst:fx2_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 10
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll_vga.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY wizpll_vga IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END wizpll_vga;
ARCHITECTURE SYN OF wizpll_vga IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2000,
clk0_duty_cycle => 50,
clk0_multiply_by => 1007,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=wizpll_vga",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "wizpll_vga.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2000"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovec.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity to_vector is
port ( r : in real;
vec : out std_ulogic_vector(15 downto 0) );
end entity to_vector;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovec.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity to_vector is
port ( r : in real;
vec : out std_ulogic_vector(15 downto 0) );
end entity to_vector;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovec.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity to_vector is
port ( r : in real;
vec : out std_ulogic_vector(15 downto 0) );
end entity to_vector;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103392)
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KuIcqRDYpA9pQcMQLIgMarrYzoryZXFNgTzQ9xeJmw20QI6Kzl4mqpcUnZ1Gw1e35hut9GKjM4sq
B/gwDQDYynWpG/tt/vGRvjhOE1SUgwQVrSWjjUZCx9idlX5bSBbpI+++3Wi7BBjnk1u3+STqGYMS
8n6r1KWpJUzs39EEwO2KWfNrd9z0q3szVSBESnThY7MqDQe3nGwWic/YxnDElbORmWcIeS9MKDNG
VIfj65CNRLpDB196C/9uCJQRLOp9+FZD4BrKeCmflimXMQI+X9NSBM+zAjBw21vq0jxy
`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity sys_wb8_tb is
end sys_wb8_tb;
architecture Behavior of sys_wb8_tb is
component sys_toplevel_wb8
Port(
I_clk: in std_logic;
I_reset: in std_logic := '0';
I_serial_rx: in std_logic;
I_interrupt: in std_logic;
O_leds: out std_logic_vector(7 downto 0) := X"00";
O_serial_tx: out std_logic;
O_vga_vsync, O_vga_hsync, O_vga_r, O_vga_g, O_vga_b: out std_logic := '0'
);
end component;
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_reset: std_logic := '0';
signal I_serial_rx, O_serial_tx: std_logic := '0';
signal I_interrupt: std_logic := '0';
signal O_leds: std_logic_vector(7 downto 0) := X"00";
signal O_vga_vsync, O_vga_hsync, O_vga_r, O_vga_g, O_vga_b: std_logic := '0';
begin
-- instantiate unit under test
uut: sys_toplevel_wb8 port map(
I_clk => I_clk,
I_reset => I_reset,
I_serial_rx => I_serial_rx,
I_interrupt => I_interrupt,
O_leds => O_leds,
O_serial_tx => O_serial_tx,
O_vga_vsync => O_vga_vsync,
O_vga_hsync => O_vga_hsync,
O_vga_r => O_vga_r,
O_vga_g => O_vga_g,
O_vga_b => O_vga_b
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
I_reset <= '0';
wait for 10 * I_clk_period;
I_reset <= '1';
wait for 100 * I_clk_period;
I_reset <= '0';
wait for 10* I_clk_period;
I_reset <= '1';
wait for 10000 * I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture; |
--------------------------------------------------------------------------------
-- sha1_pad.vhd
-- Pads SHA1 input to nearest 16 word msg and appends length nibble
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_pad is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
valid_i : in std_ulogic;
dat_w_o : out w_input
);
end sha1_pad;
architecture RTL of sha1_pad is
signal w: w_input;
signal w_temp: w_input;
-- Max length of WPA2 will never go over two frames
signal i : integer range 0 to 127;
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
for i in 0 to 15 loop
w(i) <= "00000000000000000000000000000000";
end loop;
else
for i in 1 to 15 loop
w(i) <= w_temp(i - 1);
end loop;
end if;
end if;
end process;
dat_w_o <= w_temp;
--Alt: Use a generate statement
w_temp(0) <= dat_i;
w_temp(1) <= w(1);
w_temp(2) <= w(2);
w_temp(3) <= w(3);
w_temp(4) <= w(4);
w_temp(5) <= w(5);
w_temp(6) <= w(6);
w_temp(7) <= w(7);
w_temp(8) <= w(8);
w_temp(9) <= w(9);
w_temp(10) <= w(10);
w_temp(11) <= w(11);
w_temp(12) <= w(12);
w_temp(13) <= w(13);
w_temp(14) <= w(14);
w_temp(15) <= w(15);
end RTL; |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2;
USE mdm_v3_2.MDM;
ENTITY design_1_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC
);
END design_1_mdm_1_0;
ARCHITECTURE design_1_mdm_1_0_arch OF design_1_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "MDM,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mdm_1_0_arch : ARCHITECTURE IS "design_1_mdm_1_0,MDM,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "design_1_mdm_1_0,MDM,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mdm,x_ipVersion=3.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_JTAG_CHAIN=2,C_USE_BSCAN=0,C_USE_CONFIG_RESET=0,C_INTERCONNECT=2,C_MB_DBG_PORTS=1,C_USE_UART=0,C_DBG_REG_ACCESS=0,C_DBG_MEM_ACCESS=0,C_USE_CROSS_TRIGGER=0,C_TRACE_OUTPUT=0,C_TRACE_DATA_WIDTH=32,C_TRACE_CLK_FREQ_HZ=200000000,C_TRACE_CLK_OUT_PHASE=90,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_FREQ_HZ=100000000,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_THREAD_ID_WIDTH=1,C_DATA_SIZE=32,C_M_AXIS_DATA_WIDTH=32,C_M_AXIS_ID_WIDTH=7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END design_1_mdm_1_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2;
USE mdm_v3_2.MDM;
ENTITY design_1_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC
);
END design_1_mdm_1_0;
ARCHITECTURE design_1_mdm_1_0_arch OF design_1_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "MDM,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mdm_1_0_arch : ARCHITECTURE IS "design_1_mdm_1_0,MDM,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "design_1_mdm_1_0,MDM,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mdm,x_ipVersion=3.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_JTAG_CHAIN=2,C_USE_BSCAN=0,C_USE_CONFIG_RESET=0,C_INTERCONNECT=2,C_MB_DBG_PORTS=1,C_USE_UART=0,C_DBG_REG_ACCESS=0,C_DBG_MEM_ACCESS=0,C_USE_CROSS_TRIGGER=0,C_TRACE_OUTPUT=0,C_TRACE_DATA_WIDTH=32,C_TRACE_CLK_FREQ_HZ=200000000,C_TRACE_CLK_OUT_PHASE=90,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_FREQ_HZ=100000000,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_THREAD_ID_WIDTH=1,C_DATA_SIZE=32,C_M_AXIS_DATA_WIDTH=32,C_M_AXIS_ID_WIDTH=7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END design_1_mdm_1_0_arch;
|
-- $Id: miglib_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: miglib_arty
-- Description: MIG interface components - for arty
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.miglib.all;
package miglib_arty is
constant mig_bawidth : positive := 4; -- byte addr width
constant mig_mawidth : positive := 28; -- mem addr width
constant mig_mwidth : positive := 2**mig_bawidth; -- mask width ( 16)
constant mig_dwidth : positive := 8*mig_mwidth; -- data width (128)
component sramif_mig_arty is -- SRAM to DDR via MIG for arty
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- die temperature
MONI : out sramif2migui_moni_type;-- monitor signals
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end component;
component migui_arty is -- MIG generated for arty
port (
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0); -- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh reques
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end component;
end package miglib_arty;
|
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
component pr_region_alternate_mm_bridge_0 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component pr_region_alternate_mm_bridge_0;
u0 : component pr_region_alternate_mm_bridge_0
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2830.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RANGE is
end RANGE;
ENTITY c13s09b00x00p99n01i02830ent IS
END c13s09b00x00p99n01i02830ent;
ARCHITECTURE c13s09b00x00p99n01i02830arch OF c13s09b00x00p99n01i02830ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02830 - Reserved word RANGE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02830arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2830.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RANGE is
end RANGE;
ENTITY c13s09b00x00p99n01i02830ent IS
END c13s09b00x00p99n01i02830ent;
ARCHITECTURE c13s09b00x00p99n01i02830arch OF c13s09b00x00p99n01i02830ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02830 - Reserved word RANGE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02830arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2830.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity RANGE is
end RANGE;
ENTITY c13s09b00x00p99n01i02830ent IS
END c13s09b00x00p99n01i02830ent;
ARCHITECTURE c13s09b00x00p99n01i02830arch OF c13s09b00x00p99n01i02830ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02830 - Reserved word RANGE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02830arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_master
-- File: pt_pci_master.vhd
-- Author: Nils Johan Wessman, Aeroflex Gaisler
-- Description: PCI Testbench Master
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
use grlib.stdlib.tost;
use grlib.testlib.print;
entity pt_pci_master is
generic (
slot : integer := 0;
tval : time := 7 ns);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- Debug interface signals
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end pt_pci_master;
architecture behav of pt_pci_master is
-- NEW =>
type access_element_type;
type access_element_ptr is access access_element_type;
type access_element_type is record
acc : pt_pci_access_type;
nxt : access_element_ptr;
end record;
constant idle_acc : pt_pci_access_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'),
0, 0, 0, 0, false, false, false, false, 0, 0);
signal pci_core : pt_pci_master_in_type;
signal core_pci : pt_pci_master_out_type;
-- Description: Insert a access at the "tail" of the linked list of accesses
procedure add_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type) is
variable elem : access_element_ptr;
begin -- insert_access
elem := acc_tail;
if elem /= NULL then
elem.nxt := new access_element_type'(acc, NULL);
acc_tail := elem.nxt;
else
acc_head := new access_element_type'(acc, NULL);
acc_tail := acc_head;
end if;
end add_acc;
-- Description: Get the access at the "head" of the linked list of accesses
-- and remove if from the list
procedure pop_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem : access_element_ptr;
begin -- pop_access
elem := acc_head;
if elem /= NULL then
found := true;
acc <= elem.acc;
if elem = acc_tail then
acc_head := NULL;
acc_tail := NULL;
else
acc_head := elem.nxt;
end if;
deallocate(elem);
else
found := false;
acc <= idle_acc;
end if;
end pop_acc;
-- Description: Searches the list for a result to a particular id.
procedure get_res (
variable res_head : inout access_element_ptr;
variable res_tail : inout access_element_ptr;
signal accin : in pt_pci_access_type;
signal acc : out pt_pci_access_type;
variable found : out boolean) is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- get_result
prev := res_head;
elem := res_head;
while elem /= NULL and not lfound loop
-- Check if result is a match for id
if accin.id = elem.acc.id then
acc <= elem.acc;
lfound := true;
if prev = res_head then
res_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = res_tail then
res_tail := NULL;
end if;
deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
if lfound then found := true;
else found := false; acc <= idle_acc; end if;
end get_res;
-- Description:
procedure rm_acc (
variable acc_head : inout access_element_ptr;
variable acc_tail : inout access_element_ptr;
signal acc : in pt_pci_access_type;
constant rmall : in boolean )is
variable elem, prev : access_element_ptr;
variable lfound : boolean := false;
begin -- rm_access
prev := acc_head;
elem := acc_head;
while elem /= NULL and not lfound loop
if rmall = true then
prev := elem;
elem := elem.nxt;
deallocate(prev);
else
if acc.addr = elem.acc.addr then
if prev = acc_head then
acc_head := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
if elem = acc_tail then
acc_tail := NULL;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end if;
end loop;
if rmall = true then
acc_head := NULL;
acc_tail := NULL;
end if;
end rm_acc;
-- <= NEW
type state_type is(idle, addr, data, turn, active, done);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
perren : std_logic_vector(1 downto 0);
read : std_logic;
grant : std_logic;
perr_ad : std_logic_vector(31 downto 0);
perr_cbe : std_logic_vector(3 downto 0);
devsel_timeout : integer range 0 to 3;
pci : pci_type;
acc : pt_pci_access_type;
parerr : std_logic;
end record;
signal r,rin : reg_type;
begin
-- NEW =>
core_acc : process
variable acc_head : access_element_ptr := NULL;
variable acc_tail : access_element_ptr := NULL;
variable res_head : access_element_ptr := NULL;
variable res_tail : access_element_ptr := NULL;
variable res_to_find : pt_pci_access_type := idle_acc;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
dbgo.res_found <= '0';
if dbgi.add = true then
add_acc(acc_head, acc_tail, dbgi.acc);
elsif dbgi.remove = true then
rm_acc(acc_head, acc_tail, dbgi.acc, dbgi.rmall);
elsif dbgi.get_res = true then
dbgo.valid <= false;
get_res(res_head, res_tail, dbgi.acc, dbgo.acc, found);
if found = true then dbgo.valid <= true; res_to_find := idle_acc;
else res_to_find := dbgi.acc; end if;
else
dbgo.valid <= false;
pop_acc(acc_head, acc_tail, dbgo.acc, found);
if found = true then dbgo.valid <= true; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.add = true then
add_acc(acc_head, acc_tail, pci_core.acc);
elsif pci_core.add_res = true then
add_acc(res_head, res_tail, pci_core.acc);
if res_to_find.valid = true and pci_core.acc.id = res_to_find.id then
dbgo.res_found <= '1';
end if;
else
core_pci.valid <= false;
pop_acc(acc_head, acc_tail, core_pci.acc, found);
if found = true then core_pci.valid <= true; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
-- <= NEW
pt_pci_core : process
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
function check_data(
constant pci_data : std_logic_vector(31 downto 0);
constant comp_data : std_logic_vector(31 downto 0);
constant cbe : std_logic_vector(3 downto 0))
return boolean is
variable res : boolean := true;
variable data : std_logic_vector(31 downto 0);
begin
data := comp_data;
if cbe(0) = '1' then data(7 downto 0) := (others => '-'); end if;
if cbe(1) = '1' then data(15 downto 8) := (others => '-'); end if;
if cbe(2) = '1' then data(23 downto 16) := (others => '-'); end if;
if cbe(3) = '1' then data(31 downto 24) := (others => '-'); end if;
for i in 0 to 31 loop
if pci_data(i) /= data(i) and data(i) /= '-' then res := false; end if;
end loop;
return res;
end check_data;
variable v : reg_type;
variable vpciin : pci_type;
begin
if to_x01(pciin.syst.rst) = '0' then
v.state := idle;
v.pcien := (others => '0');
v.pci := pci_idle;
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
v.read := '0';
v.perren := (others => '0');
v.parerr := '0';
elsif rising_edge(pciin.syst.clk) then
v := r;
vpciin := pciin;
v.grant := to_x01(vpciin.ifc.frame) and to_x01(vpciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(vpciin.arb.gnt(slot));
v.pcien(1) := r.pcien(0); v.pcien(2) := r.pcien(1);
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe & r.parerr);
v.perr_ad := vpciin.ad.ad; v.perr_cbe := vpciin.ad.cbe;
v.pci.err.perr := (not xorv(r.perr_ad & r.perr_cbe & to_x01(vpciin.ad.par))) or not r.read;
v.perren(1) := r.perren(0);
case r.state is
when idle =>
if core_pci.valid = true then
if r.acc.idle = false then
v.pci.arb.req(slot) := '0';
if v.grant = '1' then
v.pcien(0) := '1';
v.pci.ifc.frame := '0';
v.pci.ad.ad := core_pci.acc.addr;
v.pci.ad.cbe := core_pci.acc.cbe_cmd;
if core_pci.acc.parerr = 2 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := addr;
v.read := '0';
v.perren := (others => '0');
end if;
else -- Idle cycle
if r.acc.ws <= 0 then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
else
v.acc.ws := r.acc.ws - 1;
end if;
end if;
else
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
end if;
when addr =>
if r.acc.last = true and r.acc.ws <= 0 then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
if (r.acc.cbe_cmd = MEM_READ or r.acc.cbe_cmd = MEM_R_MULT or r.acc.cbe_cmd = MEM_R_LINE
or r.acc.cbe_cmd = IO_READ or r.acc.cbe_cmd = CONF_READ) then
v.read := '1';
end if;
if r.acc.ws <= 0 then v.pci.ifc.irdy := '0'; v.pci.ad.ad := r.acc.data;
else v.acc.ws := r.acc.ws - 1; v.pci.ad.ad := (others => '-'); end if;
v.pci.ad.cbe := r.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
v.state := data;
v.devsel_timeout := 0;
when data =>
if r.pci.ifc.irdy = '1' and r.acc.ws /= 0 then
v.acc.ws := r.acc.ws - 1;
else
v.pci.ifc.irdy := '0';
v.pci.ad.ad := r.acc.data;
if r.acc.last = true or to_x01(vpciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
end if;
if to_x01(vpciin.ifc.devsel) = '1' then
if r.devsel_timeout < 3 then
v.devsel_timeout := r.devsel_timeout + 1;
else
v.pci.ifc.frame := '1';
v.pci.ifc.irdy := '1';
if r.pci.ifc.frame = '1' then
v.pcien(0) := '0';
v.state := idle;
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: MASTER ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: MASTER ABORT");
end if;
end if;
end if;
end if;
end if;
--if to_x01(vpciin.ifc.trdy) = '0' and r.pci.ifc.irdy = '0' then
if (to_x01(vpciin.ifc.trdy) = '0' or (r.acc.cod = 1 and to_x01(vpciin.ifc.stop) = '0')) and r.pci.ifc.irdy = '0' then
if r.read = '1' then v.perren(0) := '1'; end if; -- only drive perr from read
if r.pci.ifc.frame = '1' then -- done
v.pcien(0) := '0'; v.pci.ifc.irdy := '1';
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= vpciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
v.state := idle;
else
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc;
if r.read = '1' then pci_core.acc.data <= vpciin.ad.ad; end if;
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if core_pci.valid = true then
v.pci.ad.cbe := v.acc.cbe_data;
if core_pci.acc.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if;
if v.acc.ws <= 0 then
v.pci.ad.ad := v.acc.data;
if v.acc.last = true or to_x01(vpciin.ifc.stop) = '0' then v.pci.ifc.frame := '1'; v.pci.arb.req(slot) := '1'; end if;
else
v.pci.ad.ad := (others => '-');
if v.pci.ifc.frame = '0' then v.pci.ifc.irdy := '1'; end if; -- If frame => '1', do not add waitstates (irdey => '1')
v.acc.ws := v.acc.ws - 1;
end if;
else
assert false
report "No valid acces in list, access required! (no access is marked LAST)"
severity FAILURE;
end if;
end if;
if r.acc.debug >= 1 then
if r.acc.cod = 1 and to_x01(vpciin.ifc.stop) = '0' and to_x01(vpciin.ifc.trdy) = '1' then
if r.read = '1' then
print("PCITBM Read[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
else
print("PCITBM WRITE[" & tost(r.acc.addr) & "]: CANCELED ON DISCONNECT");
end if;
else
if r.read = '1' then
if check_data(vpciin.ad.ad, r.pci.ad.ad, r.pci.ad.cbe) = false then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad) & " != " & tost(r.pci.ad.ad));
elsif r.acc.debug >= 2 then
print("PCITBM Read[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad));
end if;
else
if r.acc.debug >= 2 then
print("PCITBM Write[" & tost(r.acc.addr) & "]: " & tost(vpciin.ad.ad));
end if;
end if;
end if;
end if;
elsif to_x01(vpciin.ifc.stop) = '0' and r.pci.ifc.frame = '1' then -- Disconnect
v.pcien(0) := '0';
v.pci.ifc.irdy := '1';
v.state := idle;
if to_x01(vpciin.ifc.devsel) = '1' then
if r.acc.list_res = true then -- store result
pci_core.acc <= r.acc; -- should set Master abort status in this response
pci_core.add_res <= true; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
wait for 1 ps;
end if;
pci_core.add_res <= false; pci_core.add <= false; pci_core.remove <= false; sync_with_core;
v.acc := core_pci.acc;
if r.acc.debug >= 1 then
if r.read = '1' then
print("ERROR: PCITBM Read[" & tost(r.acc.addr) & "]: TARGET ABORT");
else
print("ERROR: PCITBM WRITE[" & tost(r.acc.addr) & "]: TARGET ABORT");
end if;
end if;
end if;
end if;
when turn =>
when active =>
when done =>
when others =>
end case;
end if;
r <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.pcien(0) and not r.read) = '1' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '1' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.pcien(1) = '1' and (r.read = '0' or r.pcien(3 downto 0) = "0011")) else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '1' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '1' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when (r.pcien(2) and r.perren(1)) = '1' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '1' else 'Z' after tval;
-- Unused signals
pciout.arb <= arb_const;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
-- Unused signals
pciout.ifc.trdy <= 'Z';
pciout.ifc.stop <= 'Z';
pciout.ifc.devsel <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc358.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00358ent IS
END c03s02b01x01p02n01i00358ent;
ARCHITECTURE c03s02b01x01p02n01i00358arch OF c03s02b01x01p02n01i00358ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
type MVL3 is array(MVL1'LOW to MVL2'HIGH) of Integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00358 - Bounds are of different discrete types."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00358arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc358.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00358ent IS
END c03s02b01x01p02n01i00358ent;
ARCHITECTURE c03s02b01x01p02n01i00358arch OF c03s02b01x01p02n01i00358ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
type MVL3 is array(MVL1'LOW to MVL2'HIGH) of Integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00358 - Bounds are of different discrete types."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00358arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc358.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00358ent IS
END c03s02b01x01p02n01i00358ent;
ARCHITECTURE c03s02b01x01p02n01i00358arch OF c03s02b01x01p02n01i00358ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
type MVL3 is array(MVL1'LOW to MVL2'HIGH) of Integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00358 - Bounds are of different discrete types."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00358arch;
|
-- $Id: gen_crc8_tbl_check.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to test crc8 transition table
--
-- Dependencies: -
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 use now 'A6' polynomial of Koopman et al.
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity gen_crc8_tbl_check is
end gen_crc8_tbl_check;
architecture sim of gen_crc8_tbl_check is
begin
process
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174,
242, 191, 104, 37, 139, 198, 17, 92,
169, 228, 51, 126, 208, 157, 74, 7,
91, 22, 193, 140, 34, 111, 184, 245,
31, 82, 133, 200, 102, 43, 252, 177,
237, 160, 119, 58, 148, 217, 14, 67,
182, 251, 44, 97, 207, 130, 85, 24,
68, 9, 222, 147, 61, 112, 167, 234,
62, 115, 164, 233, 71, 10, 221, 144,
204, 129, 86, 27, 181, 248, 47, 98,
151, 218, 13, 64, 238, 163, 116, 57,
101, 40, 255, 178, 28, 81, 134, 203,
33, 108, 187, 246, 88, 21, 194, 143,
211, 158, 73, 4, 170, 231, 48, 125,
136, 197, 18, 95, 241, 188, 107, 38,
122, 55, 224, 173, 3, 78, 153, 212,
124, 49, 230, 171, 5, 72, 159, 210,
142, 195, 20, 89, 247, 186, 109, 32,
213, 152, 79, 2, 172, 225, 54, 123,
39, 106, 189, 240, 94, 19, 196, 137,
99, 46, 249, 180, 26, 87, 128, 205,
145, 220, 11, 70, 232, 165, 114, 63,
202, 135, 80, 29, 179, 254, 41, 100,
56, 117, 162, 239, 65, 12, 219, 150,
66, 15, 216, 149, 59, 118, 161, 236,
176, 253, 42, 103, 201, 132, 83, 30,
235, 166, 113, 60, 146, 223, 8, 69,
25, 84, 131, 206, 96, 45, 250, 183,
93, 16, 199, 138, 36, 105, 190, 243,
175, 226, 53, 120, 214, 155, 76, 1,
244, 185, 110, 35, 141, 192, 23, 90,
6, 75, 156, 209, 127, 50, 229, 168
);
variable crc : integer := 0;
variable oline : line;
begin
loop_i: for i in 0 to 255 loop
write(oline, i, right, 4);
write(oline, string'(": cycle length = "));
crc := i;
loop_n: for n in 1 to 256 loop
crc := crc8_tbl(crc);
if crc = i then
write(oline, n, right, 4);
writeline(output, oline);
exit loop_n;
end if;
end loop; -- n
end loop; -- i
wait;
end process;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter50 is
port(C, CLR, hold : in std_logic;
Q : out std_logic_vector(5 downto 0));
end counter50;
architecture archi of counter50 is
signal tmp: std_logic_vector(5 downto 0);
begin
process (C, CLR, hold)
begin
if (hold = '0') then
if (CLR='1') then
tmp <= "000000";
elsif (C'event and C='1') then
if (tmp = "110011") then
tmp <= "000001";
else
tmp <= tmp + 1;
end if;
end if;
end if;
end process;
Q <= tmp;
end archi; |
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity control_tb is
end;
architecture bench of control_tb is
component control
Port ( Switches : in STD_LOGIC_VECTOR (0 to 7);
clk_12hz : in std_logic;
clk_1hz5 : in std_logic;
Leds : out STD_LOGIC_VECTOR (0 to 7) := "10000000"; --left to right
butn_in : in STD_LOGIC_VECTOR (0 to 2);
en : out STD_LOGIC_VECTOR (0 to 3):= "0000";
options0 : out STD_LOGIC_VECTOR (0 to 3);
options1 : out STD_LOGIC_VECTOR (0 to 3);
options2 : out STD_LOGIC_VECTOR (0 to 3);
options3 : out STD_LOGIC_VECTOR (0 to 3)
);
end component;
signal Switches: STD_LOGIC_VECTOR (0 to 7);
signal clk_12hz : std_logic;
signal clk_1hz5 : std_logic;
signal Leds : STD_LOGIC_VECTOR (0 to 7) := "10000000"; --left to right
signal butn_in : STD_LOGIC_VECTOR (0 to 2);
signal en : STD_LOGIC_VECTOR (0 to 3):= "0000";
signal options0 : STD_LOGIC_VECTOR (0 to 3);
signal options1 : STD_LOGIC_VECTOR (0 to 3);
signal options2 : STD_LOGIC_VECTOR (0 to 3);
signal options3 : STD_LOGIC_VECTOR (0 to 3);
constant clock_period: time := 83 ms;
constant clock_period2: time := 0.66 sec;
begin
uut: control port map ( Switches => Switches,
clk_12hz => clk_12hz,
clk_1hz5 => clk_1hz5,
Leds => Leds,
butn_in => butn_in,
en => en,
options0 => options0,
options1 => options1,
options2 => options2,
options3 => options3 );
clk_process: process
begin
clk_12hz <= '1';
wait for clock_period/2;
clk_12hz <= '0';
wait for clock_period/2;
end process;
clk2_process: process
begin
clk_1hz5 <= '1';
wait for clock_period2/2;
clk_1hz5 <= '0';
wait for clock_period2/2;
end process;
stimulus: process
begin
butn_in <= "001";
wait for 100ms;
butn_in <= "00000";
wait for 50ms;
butn_in <= "001";
wait for 200ms;
butn_in <= "00000";
wait for 50ms;
-- butn_in <= "00100";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
-- butn_in <= "00010";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
--butn_in <= "00001";
-- wait for 100ms;
-- butn_in <= "00000";
-- wait for 50ms;
-- butn_in <= "01000";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 50ms;
-- butn_in <= "00100";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
-- butn_in <= "00010";
-- wait for 200ms;
-- butn_in <= "00000";
-- wait for 100ms;
wait;
end process;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_0_0 is
Port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_0_0;
architecture stub of system_ov7670_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x2,active,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_0_0 is
Port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_0_0;
architecture stub of system_ov7670_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x2,active,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_0_0 is
Port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_0_0;
architecture stub of system_ov7670_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x2,active,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vector(7 downto 0) := "10101010";
begin
assert c1(1) = c0;
assert c1(0) = cmp;
wait;
end process;
end architecture;
|
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vector(7 downto 0) := "10101010";
begin
assert c1(1) = c0;
assert c1(0) = cmp;
wait;
end process;
end architecture;
|
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vector(7 downto 0) := "10101010";
begin
assert c1(1) = c0;
assert c1(0) = cmp;
wait;
end process;
end architecture;
|
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vector(7 downto 0) := "10101010";
begin
assert c1(1) = c0;
assert c1(0) = cmp;
wait;
end process;
end architecture;
|
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vector(7 downto 0) := "10101010";
begin
assert c1(1) = c0;
assert c1(0) = cmp;
wait;
end process;
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
pcie_target_simulation : integer := 0; -- set to 1 to test pci express, only if pcie_target is enabled
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := 40;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_reset_n: std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
-----------------------------------------------------FOR PCIE---------------
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
-----------------------------------------------pcie end--------------
begin
-- clock and reset
clk27 <= not clk27 after ct * 1 ns;
clk33 <= not clk33 after 15 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch <= "0000";
---------------------pcie----------------------------------------------
pcie_sim: if pcie_target_simulation = 1 generate
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => 1,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end generate;
--------------------------------------pcie---------------------------
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
data, oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, button,
switch, led,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spi_sel_n, spi_clk, spi_mosi, ep_pci_exp_txn(0), ep_pci_exp_txp(0), rp_pci_exp_txn(0),
rp_pci_exp_txp(0), ep_sys_clk_p, ep_sys_clk_n, sys_reset_n,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d
);
-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
-- writen, oen);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
address(0) <= '0';
u1 : ddr3ram
generic map (
width => 16, abits => 13, fname => sdramfile,
speedbin => 3,
ldguard => 1
)
port map (
ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, odt => ddr_odt,
rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, resetn => ddr_reset_n,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn,
doload => led(2)
);
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sysace_mpirq <= '0';
sysace_d <= (others => 'Z');
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_endpoint is
end entity psl_test_endpoint;
architecture test of psl_test_endpoint is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_test_endpoint test case";
report "==========================================";
s_write <= '0'; -- named assertion should hit
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
stop(0);
end process TestP;
-- psl default clock is rising_edge(s_clk);
-- psl endpoint E_TEST is {not(s_write); s_write};
-- psl sequence abc_seq is {not(s_write); s_write};
-- psl ENDPOINT_ASSERT : assert always {E_TEST; s_read} report "ENDPOINT ASSERT";
-- psl COVERAGE0 : cover {not(s_write); s_write} report "COVERED0";
-- psl COVERAGE1 : cover {abc_seq} report "COVERED1";
-- psl COVERAGE2 : cover {E_TEST} report "COVERED2";
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_endpoint is
end entity psl_test_endpoint;
architecture test of psl_test_endpoint is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_test_endpoint test case";
report "==========================================";
s_write <= '0'; -- named assertion should hit
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
stop(0);
end process TestP;
-- psl default clock is rising_edge(s_clk);
-- psl endpoint E_TEST is {not(s_write); s_write};
-- psl sequence abc_seq is {not(s_write); s_write};
-- psl ENDPOINT_ASSERT : assert always {E_TEST; s_read} report "ENDPOINT ASSERT";
-- psl COVERAGE0 : cover {not(s_write); s_write} report "COVERED0";
-- psl COVERAGE1 : cover {abc_seq} report "COVERED1";
-- psl COVERAGE2 : cover {E_TEST} report "COVERED2";
end architecture test;
|
entity jcore4 is
end entity;
architecture test of jcore4 is
type rt is record
x : bit_vector(1 to 3);
end record;
type at is array (integer range <>) of rt;
signal a : at(1 to 3);
begin
end architecture;
|
entity jcore4 is
end entity;
architecture test of jcore4 is
type rt is record
x : bit_vector(1 to 3);
end record;
type at is array (integer range <>) of rt;
signal a : at(1 to 3);
begin
end architecture;
|
entity jcore4 is
end entity;
architecture test of jcore4 is
type rt is record
x : bit_vector(1 to 3);
end record;
type at is array (integer range <>) of rt;
signal a : at(1 to 3);
begin
end architecture;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: if_func_C
-- Date: 23:00:30 10/04/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity if_func_C is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
gts : in std_logic; -- go to standby
rpp : in std_logic; -- request parallel poll
tcs : in std_logic; -- take control synchronously
tca : in std_logic; -- take control asynchronously
sic : in std_logic; -- send interface clear
rsc : in std_logic; -- request system control
sre : in std_logic; -- send remote enable
-- state inputs
TADS : in std_logic; -- talker addressed state (T or TE)
ACDS : in std_logic; -- accept data state (AH)
ANRS : in std_logic; -- acceptor not ready state (AH)
STRS : in std_logic; -- source transfer state (SH)
SDYS : in std_logic; -- source delay state (SH)
-- command inputs
ATN_in : in std_logic; -- attention
IFC_in : in std_logic; -- interface clear
TCT_in : in std_logic; -- take control
SRQ_in : in std_logic; -- service request
-- command outputs
ATN_out : out std_logic; -- attention
IFC_out : out std_logic; -- interface clear
TCT_out : out std_logic; -- take control
IDY_out : out std_logic; -- identify
REN_out : out std_logic; -- remote enable
-- reported states
CACS : out std_logic; -- controller active state
CTRS : out std_logic; -- controller transfer state
CSBS : out std_logic; -- controller standby state
CPPS : out std_logic; -- controller parallel poll state
CSRS : out std_logic; -- controller service requested state
SACS : out std_logic -- system control active state
);
end if_func_C;
architecture Behavioral of if_func_C is
-- states
type C_STATE_1 is (
-- controller idle state
ST_CIDS,
-- controller addressed state
ST_CADS,
-- controller transfer state
ST_CTRS,
-- controller active state
ST_CACS,
-- controller standby state
ST_CSBS,
-- controllet synchronous wait state
ST_CSWS,
-- controller active wait state
ST_CAWS,
-- controller parallel poll wait state
ST_CPWS,
-- controller parallel poll wait state
ST_CPPS
);
-- states
type C_STATE_2 is (
-- controller service not requested state
ST_CSNS,
-- controller service requested state
ST_CSRS
);
-- states
type C_STATE_3 is (
-- system control interface clear idle state
ST_SIIS,
-- system control interface clear active state
ST_SIAS,
-- system control interface clear not active state
ST_SINS
);
-- states
type C_STATE_4 is (
-- system control remote enable idle state
ST_SRIS,
-- system control remote enable active state
ST_SRAS,
-- system control remote enable not active state
ST_SRNS
);
-- states
type C_STATE_5 is (
-- system control not active state
ST_SNAS,
-- system control active state
ST_SACS
);
-- current state
signal current_state_1 : C_STATE_1;
signal current_state_2 : C_STATE_2;
signal current_state_3 : C_STATE_3;
signal current_state_4 : C_STATE_4;
signal current_state_5 : C_STATE_5;
-- events
signal event1_1, event1_2, event1_3, event1_4, event1_5,
event1_6, event1_7, event1_8, event1_9, event1_10,
event1_11, event1_12 : boolean;
signal event2_1, event2_2 : boolean;
signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;
signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;
signal event5_1, event5_2 : boolean;
-- timers
constant TIMER_T6_TIMEOUT : integer := 110;
constant TIMER_T7_TIMEOUT : integer := 25;
constant TIMER_T9_TIMEOUT : integer := 75;
constant TIMER_A_MAX : integer := 128;
signal timer_a : integer range 0 to TIMER_A_MAX;
signal timer_T6Expired : boolean;
signal timer_T7Expired : boolean;
signal timer_T9Expired : boolean;
constant TIMER_T8_TIMEOUT : integer := 5000;
constant TIMER_B_MAX : integer := 5004;
signal timer_b : integer range 0 to TIMER_B_MAX;
signal timer_b_1 : integer range 0 to TIMER_B_MAX;
signal timer_T8Expired : boolean;
signal timer_T8_1Expired : boolean;
begin
-- state machine process - C_STATE_1
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_1 <= ST_CIDS;
elsif rising_edge(clk) then
-- timer
if timer_a < TIMER_A_MAX then
timer_a <= timer_a + 1;
end if;
-- state machine
case current_state_1 is
------------------
when ST_CIDS =>
if event1_1 then
-- no state change
elsif event1_2 then
current_state_1 <= ST_CADS;
end if;
------------------
when ST_CADS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_4 then
current_state_1 <= ST_CACS;
end if;
------------------
when ST_CACS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_5 then
current_state_1 <= ST_CTRS;
elsif event1_6 then
current_state_1 <= ST_CSBS;
elsif event1_7 then
timer_a <= 0;
current_state_1 <= ST_CPWS;
end if;
------------------
when ST_CTRS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_3 or event1_1 then
current_state_1 <= ST_CIDS;
end if;
------------------
when ST_CSBS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_9 then
timer_a <= 0;
current_state_1 <= ST_CSWS;
end if;
------------------
when ST_CSWS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_10 then
timer_a <= 0;
current_state_1 <= ST_CAWS;
end if;
------------------
when ST_CAWS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_8 then
current_state_1 <= ST_CACS;
elsif event1_7 then
timer_a <= 0;
current_state_1 <= ST_CPWS;
end if;
------------------
when ST_CPWS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_11 then
current_state_1 <= ST_CPPS;
end if;
------------------
when ST_CPPS =>
if event1_1 then
current_state_1 <= ST_CIDS;
elsif event1_12 then
current_state_1 <= ST_CAWS;
end if;
------------------
when others =>
current_state_1 <= ST_CIDS;
end case;
end if;
end process;
-- state machine process - C_STATE_2
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_2 <= ST_CSNS;
elsif rising_edge(clk) then
-- state machine
case current_state_2 is
------------------
when ST_CSNS =>
if event2_1 then
current_state_2 <= ST_CSRS;
end if;
------------------
when ST_CSRS =>
if event2_2 then
current_state_2 <= ST_CSNS;
end if;
------------------
when others =>
current_state_2 <= ST_CSNS;
end case;
end if;
end process;
-- state machine process - C_STATE_3
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_3 <= ST_SIIS;
elsif rising_edge(clk) then
-- timer
if timer_b < TIMER_B_MAX then
timer_b <= timer_b + 1;
end if;
-- state machine
case current_state_3 is
------------------
when ST_SIIS =>
if event3_1 then
-- no state change
elsif event3_2 then
timer_b <= 0;
current_state_3 <= ST_SIAS;
elsif event3_3 then
current_state_3 <= ST_SINS;
end if;
------------------
when ST_SIAS =>
if event3_1 then
current_state_3 <= ST_SIIS;
elsif event3_5 then
current_state_3 <= ST_SINS;
end if;
------------------
when ST_SINS =>
if event3_1 then
current_state_3 <= ST_SIIS;
elsif event3_4 then
current_state_3 <= ST_SIAS;
end if;
------------------
when others =>
current_state_3 <= ST_SIIS;
end case;
end if;
end process;
-- state machine process - C_STATE_4
process(pon, clk) begin
-- async reset
if pon='1' then
timer_b_1 <= 0;
current_state_4 <= ST_SRIS;
elsif rising_edge(clk) then
-- timer
if timer_b_1 < TIMER_B_MAX then
timer_b_1 <= timer_b_1 + 1;
end if;
-- state machine
case current_state_4 is
------------------
when ST_SRIS =>
if event4_1 then
-- no state change
elsif event4_2 then
timer_b_1 <= 0;
current_state_4 <= ST_SRAS;
elsif event4_3 then
current_state_4 <= ST_SRNS;
end if;
------------------
when ST_SRAS =>
if event4_1 then
current_state_4 <= ST_SRIS;
elsif event4_5 then
current_state_4 <= ST_SRNS;
end if;
------------------
when ST_SRNS =>
if event4_1 then
current_state_4 <= ST_SRIS;
elsif event4_4 then
timer_b_1 <= 0;
current_state_4 <= ST_SRAS;
end if;
------------------
when others =>
current_state_4 <= ST_SRIS;
end case;
end if;
end process;
-- state machine process - C_STATE_5
process(pon, clk) begin
-- async reset
if pon='1' then
current_state_5 <= ST_SNAS;
elsif rising_edge(clk) then
-- state machine
case current_state_5 is
------------------
when ST_SNAS =>
if event5_1 then
current_state_5 <= ST_SACS;
end if;
------------------
when ST_SACS =>
if event5_2 then
current_state_5 <= ST_SNAS;
end if;
------------------
when others =>
current_state_5 <= ST_SNAS;
end case;
end if;
end process;
-- events
event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;
event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;
event1_3 <= STRS='0';
event1_4 <= ATN_in='0';
event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';
event1_6 <= SDYS='0' and STRS='0' and gts='1';
event1_7 <= rpp='1';
event1_8 <= timer_T9Expired and rpp='0';
event1_9 <= (tcs='1' and ANRS='1') or tca='1';
event1_10 <= timer_T7Expired;
event1_11 <= timer_T6Expired;
event1_12 <= rpp='0';
event2_1 <= SRQ_in='1';
event2_2 <= SRQ_in='0';
event3_1 <= current_state_5/=ST_SACS;
event3_2 <= current_state_5=ST_SACS and sic='1';
event3_3 <= current_state_5=ST_SACS and sic='0';
event3_4 <= sic='1';
event3_5 <= sic='0' and timer_T8Expired;
event4_1 <= current_state_5/=ST_SACS;
event4_2 <= current_state_5=ST_SACS and sre='1';
event4_3 <= current_state_5=ST_SACS and sre='0';
event4_4 <= sre='1';
event4_5 <= sre='0' and timer_T8_1Expired;
event5_1 <= rsc='1';
event5_2 <= rsc='0';
-- timers
timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;
timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;
timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;
timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;
timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;
CPPS <= to_stdl(current_state_1 = ST_CPPS);
CSRS <= to_stdl(current_state_2 = ST_CSRS);
CSBS <= to_stdl(current_state_1 = ST_CSBS);
CACS <= to_stdl(current_state_1 = ST_CACS);
SACS <= to_stdl(current_state_5 = ST_SACS);
-- CTRS
with current_state_1 select
CTRS <=
'1' when ST_CTRS,
'0' when others;
-- ATN
with current_state_1 select
ATN_out <=
'0' when ST_CIDS,
'0' when ST_CADS,
'0' when ST_CSBS,
'1' when others;
-- IDY_out
with current_state_1 select
IDY_out <=
'1' when ST_CPWS,
'1' when ST_CPPS,
'0' when others;
-- TCT
with current_state_1 select
TCT_out <=
'1' when ST_CTRS,
'0' when others;
-- IFC
with current_state_3 select
IFC_out <=
'1' when ST_SIAS,
'0' when others;
-- REN
with current_state_4 select
REN_out <=
'1' when ST_SRAS,
'0' when others;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: lvds_combo.vhd
-- File: lvds_combo.vhd.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential input/output pads with IREF/OREF logic wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1';
lvdsrefo : out std_logic
);
end ;
architecture rtl of lvds_combo is
signal gnd : std_ulogic;
signal oen : std_logic_vector(0 to width-1);
constant level : integer := lvds;
begin
gnd <= '0';
gen0 : if has_ds_combo(tech) = 0 generate
swloop : for i in 0 to width-1 generate
od0 : outpad_ds generic map (tech, level, voltage, oepol) port map (odpadp(i), odpadn(i), odval(i), en(i));
os0 : outpad_ds generic map (tech, level, voltage, oepol) port map (ospadp(i), ospadn(i), osval(i), en(i));
id0 : inpad_ds generic map (tech, level, voltage) port map (idpadp(i), idpadn(i), idval(i));
is0 : inpad_ds generic map (tech, level, voltage) port map (ispadp(i), ispadn(i), isval(i));
end generate;
end generate;
combo : if has_ds_combo(tech) /= 0 generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
ut025 : if tech = ut25 generate
u0: ut025crh_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
ut13 : if tech = ut130 generate
u0: ut130hbd_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
um : if tech = umc generate
u0: umc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
rhu : if tech = rhumc generate
u0: rhumc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
end generate;
end;
|
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
context bad is -- Error
end context;
|
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
context bad is -- Error
end context;
|
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
context bad is -- Error
end context;
|
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
context bad is -- Error
end context;
|
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in vl_logic;
AA : in vl_logic_vector(8 downto 0);
AB : in vl_logic_vector(8 downto 0);
DIA : in vl_logic_vector(31 downto 0);
DIB : in vl_logic_vector(31 downto 0);
DOA : out vl_logic_vector(31 downto 0);
DOB : out vl_logic_vector(31 downto 0);
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0);
RB_TEST : in vl_logic;
TEST_MODE : in vl_logic
);
end dp512x32_col;
|
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in vl_logic;
AA : in vl_logic_vector(8 downto 0);
AB : in vl_logic_vector(8 downto 0);
DIA : in vl_logic_vector(31 downto 0);
DIB : in vl_logic_vector(31 downto 0);
DOA : out vl_logic_vector(31 downto 0);
DOB : out vl_logic_vector(31 downto 0);
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0);
RB_TEST : in vl_logic;
TEST_MODE : in vl_logic
);
end dp512x32_col;
|
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in vl_logic;
AA : in vl_logic_vector(8 downto 0);
AB : in vl_logic_vector(8 downto 0);
DIA : in vl_logic_vector(31 downto 0);
DIB : in vl_logic_vector(31 downto 0);
DOA : out vl_logic_vector(31 downto 0);
DOB : out vl_logic_vector(31 downto 0);
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0);
RB_TEST : in vl_logic;
TEST_MODE : in vl_logic
);
end dp512x32_col;
|
----------------------------------------------------------------------------------
-- Simple FIR filter using systolic form.
-- Initial version: Colm Ryan ([email protected])
-- Create Date: 06/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
entity FIR_Systolic is
generic(
coeffs : integer_vector := (2,3,4,5,6);
data_in_width : natural := 16
);
port (
rst : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(data_in_width-1 downto 0);
data_in_vld : std_logic;
data_in_last : std_logic;
data_out : out std_logic_vector(47 downto 0));
end FIR_Systolic;
architecture Behavioral of FIR_Systolic is
constant NUM_TAPS : natural := coeffs'length;
type chainedSum_t is array(0 to NUM_TAPS-1) of signed(47 downto 0);
signal chainedSum : chainedSum_t := (others => (others => '0'));
type dataRegs_t is array(0 to NUM_TAPS-2) of signed(data_in_width-1 downto 0);
signal dataRegs_1, dataRegs_2 : dataRegs_t := (others => (others => '0'));
signal data_in_d : signed(data_in_width-1 downto 0);
--Vivado does not infer DSP for constant multiplier so force DSP
-- see http://www.xilinx.com/support/answers/60913.html
attribute use_dsp48 : string;
attribute use_dsp48 of chainedSum : signal is "yes";
begin
main : process(clk)
begin
if rising_edge(clk) then
--register input data and convert to signed for DSP slice
data_in_d <= signed(data_in);
-- double register
dataRegs_1(0) <= data_in_d;
regLooper1 : for ct in 1 to NUM_TAPS-2 loop
dataRegs_1(ct) <= dataRegs_2(ct-1);
end loop;
regLooper2 : for ct in 0 to NUM_TAPS-2 loop
dataRegs_2(ct) <= dataRegs_1(ct);
end loop;
--Multiply by coeffs and chain the sum
--We resize to 18 bits because the DSP slices offer 18x25 bit multipliers
chainedSum(0) <= resize(data_in_d * to_signed(coeffs(0),18), 48);
sumLooper : for ct in 1 to NUM_TAPS-1 loop
chainedSum(ct) <= resize(dataRegs_2(ct-1) * to_signed(coeffs(ct),18), 48) + chainedSum(ct-1);
end loop;
--register out
data_out <= std_logic_vector(chainedSum(chainedSum'high));
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Module Name: tb_test_source_3840_2160 - Behavioral
--
-- Description: A testbench for tb_test_source
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_test_source_3840_2160 is
end entity;
architecture arch of tb_test_source_3840_2160 is
component test_source_3840_2160_YCC_422_ch2 is
port (
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0) := (others => '0'));
end component;
component idle_pattern_inserter is
port (
clk : in std_logic;
channel_ready : in std_logic;
source_ready : in std_logic;
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(71 downto 0) := (others => '0')
);
end component;
component scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler is
port (
clk : in std_logic;
bypass0 : in std_logic;
bypass1 : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0)
);
end component;
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0);
out_data0forceneg : out std_logic;
out_data1forceneg : out std_logic
);
end component;
component data_to_8b10b is
port (
clk : in std_logic;
forceneg : in std_logic_vector(1 downto 0);
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(19 downto 0) := (others => '0')
);
end component;
signal clk : std_logic;
signal test_signal_data : std_logic_vector(72 downto 0);
signal test_signal_ready : std_logic;
signal msa_merged_data : std_logic_vector(72 downto 0);
signal signal_data : std_logic_vector(71 downto 0);
signal sr_inserted_data : std_logic_vector(71 downto 0);
signal scramble_bypass : std_logic := '1';
signal scrambled_data : std_logic_vector(17 downto 0);
signal ch0_data : std_logic_vector(17 downto 0);
signal ch0_forceneg : std_logic_vector(1 downto 0);
signal ch0_symbols : std_logic_vector(19 downto 0);
signal dec0 : std_logic_vector(8 downto 0);
signal rd : unsigned(9 downto 0) := (others => '0');
signal c0s0 : std_logic_vector(8 downto 0);
signal c0s1 : std_logic_vector(8 downto 0);
signal c1s0 : std_logic_vector(8 downto 0);
signal c1s1 : std_logic_vector(8 downto 0);
signal ccount : unsigned(15 downto 0) := (others => '0');
begin
i_test_source: test_source_3840_2160_YCC_422_ch2 port map (
clk => clk,
ready => test_signal_ready,
data => test_signal_data
);
i_insert_main_stream_attrbutes_two_channels: insert_main_stream_attrbutes_two_channels port map (
clk => clk,
active => '1',
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value => x"07DA13", -- For 265MHz/270Mhz
N_value => x"080000",
H_visible => x"F00", -- 3840
H_total => x"FC0", -- 4032
H_sync_width => x"030", -- 128
H_start => x"0A0", -- 160
V_visible => x"870", -- 2160
V_total => x"88F", -- 2191
V_sync_width => x"003", -- 3
V_start => x"01A", -- 26
H_vsync_active_high => '1',
V_vsync_active_high => '1',
flag_sync_clock => '1',
flag_YCCnRGB => '1',
flag_422n444 => '1',
flag_range_reduced => '1',
flag_interlaced_even => '0',
flag_YCC_colour_709 => '0',
flags_3d_Indicators => (others => '0'),
bits_per_colour => "01000",
-- M_value => x"012F68",
-- N_value => x"080000",
-- H_visible => x"320", -- 800
-- V_visible => x"258", -- 600
-- H_total => x"420", -- 1056
-- V_total => x"274", -- 628
-- H_sync_width => x"080", -- 128
-- V_sync_width => x"004", -- 4
-- H_start => x"0D8", -- 216
-- V_start => x"01b", -- 37
-- H_vsync_active_high => '0',
-- V_vsync_active_high => '0',
-- flag_sync_clock => '1',
-- flag_YCCnRGB => '0',
-- flag_422n444 => '0',
-- flag_range_reduced => '0',
-- flag_interlaced_even => '0',
-- flag_YCC_colour_709 => '0',
-- flags_3d_Indicators => (others => '0'),
-- bits_per_colour => "01000",
-----------------------------------------------------
-- The stream of pixel data coming in
-----------------------------------------------------
in_data => test_signal_data,
-----------------------------------------------------
-- The stream of pixel data going out
-----------------------------------------------------
out_data => msa_merged_data);
i_idle_pattern_inserter: idle_pattern_inserter port map (
clk => clk,
channel_ready => '1',
source_ready => test_signal_ready,
in_data => msa_merged_data,
out_data => signal_data
);
i_scrambler_reset_inserter : scrambler_reset_inserter
port map (
clk => clk,
in_data => signal_data,
out_data => sr_inserted_data
);
-- Bypass the scrambler for the test pattens.
c0s0 <= sr_inserted_data( 8 downto 0);
c0s1 <= sr_inserted_data(17 downto 9);
c1s0 <= sr_inserted_data(26 downto 18);
c1s1 <= sr_inserted_data(35 downto 27);
scramble_bypass <= '1'; -- tx_clock_train or tx_align_train;
i_scrambler : scrambler
port map (
clk => clk,
bypass0 => scramble_bypass,
bypass1 => scramble_bypass,
in_data => sr_inserted_data(17 downto 0),
out_data => scrambled_data(17 downto 0)
);
i_train_channel0: training_and_channel_delay port map (
clk => clk,
channel_delay => "00",
clock_train => '0',
align_train => '0',
in_data => scrambled_data(17 downto 0),
out_data => ch0_data,
out_data0forceneg => ch0_forceneg(0),
out_data1forceneg => ch0_forceneg(1)
);
i_data_to_8b10b: data_to_8b10b port map (
clk => clk,
in_data => ch0_data,
forceneg => ch0_forceneg,
out_data => ch0_symbols
);
process(clK)
begin
if rising_edge(clk) then
rd <= rd - to_unsigned(10,10)
+ unsigned(ch0_symbols(0 downto 0))
+ unsigned(ch0_symbols(1 downto 1))
+ unsigned(ch0_symbols(2 downto 2))
+ unsigned(ch0_symbols(3 downto 3))
+ unsigned(ch0_symbols(4 downto 4))
+ unsigned(ch0_symbols(5 downto 5))
+ unsigned(ch0_symbols(6 downto 6))
+ unsigned(ch0_symbols(7 downto 7))
+ unsigned(ch0_symbols(8 downto 8))
+ unsigned(ch0_symbols(9 downto 9))
+ unsigned(ch0_symbols(10 downto 10))
+ unsigned(ch0_symbols(11 downto 11))
+ unsigned(ch0_symbols(12 downto 12))
+ unsigned(ch0_symbols(13 downto 13))
+ unsigned(ch0_symbols(14 downto 14))
+ unsigned(ch0_symbols(15 downto 15))
+ unsigned(ch0_symbols(16 downto 16))
+ unsigned(ch0_symbols(17 downto 17))
+ unsigned(ch0_symbols(18 downto 18))
+ unsigned(ch0_symbols(19 downto 19));
end if;
end process;
--data_dec0: dec_8b10b port map (
-- RESET => '0',
-- RBYTECLK => clk,
-- AI => ch0_symbols(0),
-- BI => ch0_symbols(1),
-- CI => ch0_symbols(2),
-- DI => ch0_symbols(3),
-- EI => ch0_symbols(4),
-- II => ch0_symbols(5),
-- FI => ch0_symbols(6),
-- GI => ch0_symbols(7),
-- HI => ch0_symbols(8),
-- JI => ch0_symbols(9),
--
-- KO => dec0(8),
-- HO => dec0(7),
-- GO => dec0(6),
-- FO => dec0(5),
-- EO => dec0(4),
-- DO => dec0(3),
-- CO => dec0(2),
-- BO => dec0(1),
-- AO => dec0(0)
-- );
process(clK)
begin
if rising_edge(clK) then
if c0s0 = "111111011" then
if c0s1(8) = '1' then
ccount <= (others => '0');
else
ccount <= (0=>'1',others => '0');
end if;
elsif c0s1 = "111111011" then
ccount <= (others => '0');
elsif c0s0(8) = '0' and c0s1(8) = '0' then
ccount <= ccount + 2;
elsif c0s0(8) = '0' or c0s1(8) = '0' then
ccount <= ccount +1;
end if;
end if;
end process;
process
begin
clk <= '1';
wait for 3.703 ns;
clk <= '0';
wait for 3.703 ns;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20.08.2015 21:08:13
-- Design Name:
-- Module Name: video_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity video_generator is
Port ( clk : in STD_LOGIC;
h_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
h_front_len : in std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : in std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : in std_logic_vector(11 downto 0) := (others => '0');
v_front_len : in std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : in std_logic_vector(11 downto 0) := (others => '0');
vid_blank : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vsync : out STD_LOGIC);
end video_generator;
architecture Behavioral of video_generator is
signal h_counter : unsigned(11 downto 0) := (others => '0');
signal v_counter : unsigned(11 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
-- Generate the sync and blanking signals
if h_counter >= unsigned(h_front_len) and h_counter < unsigned(h_front_len) + unsigned(h_sync_len) then
vid_hsync <= '1';
else
vid_hsync <= '0';
end if;
if v_counter >= unsigned(v_front_len) and v_counter < unsigned(v_front_len) + unsigned(v_sync_len) then
vid_vsync <= '1';
else
vid_vsync <= '0';
end if;
if h_counter < unsigned(h_blank_len) or v_counter < unsigned(v_blank_len) then
vid_blank <= '1';
else
vid_blank <= '0';
end if;
-- Manage the counters
if h_counter = unsigned(h_visible_len)+unsigned(h_blank_len)-1 then
h_counter <= (others => '0');
if v_counter = unsigned(v_visible_len)+unsigned(v_blank_len)-1 then
v_counter <= (others => '0');
else
v_counter <= v_counter+1;
end if;
else
h_counter <= h_counter + 1;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 10:55:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-e.vhd,v 1.3 2005/07/18 08:59:29 wig Exp $
-- $Date: 2005/07/18 08:59:29 $
-- $Log: inst_aa_e-e.vhd,v $
-- Revision 1.3 2005/07/18 08:59:29 wig
-- do not write config for simple logic
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.56 2005/07/15 16:39:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa_e
--
entity inst_aa_e is
-- Generics:
-- No Generated Generics for Entity inst_aa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa_e
and_i1_1 : out std_ulogic;
and_i2_1 : out std_ulogic_vector(15 downto 0);
or_i1_1 : out std_ulogic;
or_i2_1 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end inst_aa_e;
--
-- End of Generated Entity inst_aa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Btrace 448
-- Btrace Package
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
package btrace_pack is
type color_t is (black, red, green, yellow, blue, magenta, cyan, white);
type comp_op is (gt, gte, eq);
type point is
record
-- Point coordinates, three dimensions
x, y, z: sfixed(15 downto -16);
end record;
type vector is
record
-- Vector component magnitudes
m_x, m_y, m_z: sfixed(15 downto -16);
end record;
type object is
record
position: point;
size: sfixed(15 downto -16);
color: std_logic_vector(11 downto 0);
end record;
end btrace_pack;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
|
----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Polynom Division with Inversion+Multiplication
-- Computes the g/h mod f IN GF(2**m)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- g_i - First input value
-- h_i - Seccond input value
-- z_o - Output value
-- ready_o - Ready flag after computation
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) divider with inversion
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_divider_inv IS
PORT(
-- Clock, reset and enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_divider_inv;
ARCHITECTURE rtl of e_gf2m_divider_inv IS
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_eea_inversion
COMPONENT e_gf2m_eea_inversion IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
SIGNAL invh: std_logic_vector(M-1 DOWNTO 0);
SIGNAL enable_inversion, done_inversion, enable_multiplication, done_multiplication: std_logic;
-- Define all available states
subtype states IS natural RANGE 0 TO 6;
SIGNAL current_state: states;
BEGIN
-- Instantiate inversion entity to compute h^-1
inversion: e_gf2m_eea_inversion GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_inversion,
a_i => h_i,
z_o => invh,
ready_o => done_inversion
);
-- Instantiate multiplier entity to g * h^-1
multiplier: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_multiplication,
a_i => g_i,
b_i => invh,
z_o => z_o,
ready_o => done_multiplication
);
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Calculate inversion
-- 4,5 : Calculate multiplication
CASE current_state IS
WHEN 0 TO 1 => enable_inversion <='0'; enable_multiplication <= '0'; ready_o <= '1';
WHEN 2 => enable_inversion <='1'; enable_multiplication <= '0'; ready_o <= '0';
WHEN 3 => enable_inversion <='0'; enable_multiplication <= '0'; ready_o <= '0';
WHEN 4 => enable_inversion <='0'; enable_multiplication <= '1'; ready_o <= '0';
WHEN 5 TO 6 => enable_inversion <='0'; enable_multiplication <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF done_inversion = '1' THEN
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF done_multiplication = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS control_unit;
END rtl;
|
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: mt45w8mw16b - sim
-- Description: Micron MT45W8MW16B CellularRAM model
-- Currently a much simplified model
-- - only async accesses
-- - ignores CLK and CRE
-- - simple model for response of DATA lines, but no
-- check for timing violations of control lines
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
-- 2010-06-03 298 1.3 add timing model again
-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
-- 2010-05-21 293 1.1 add BCR (only read of default so far)
-- 2010-05-16 291 1.0 Initial version (inspired by is61lv25616al)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Asynchronous Mode (BCR(15)=1)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Read L L L L H L L act data-out
-- Write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- CRE write L L L H L H X act 'z'
-- CRE read L L L L H H L act conf-out
--
-- Burst Mode (BCR(15)=0)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Async read L L L L H L L act data-out
-- Async write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- Initial burst read 0-1 L L X H L L act X
-- Initial burst write 0-1 L L H L L X act X
-- Burst continue 0-1 H L X X X X act data-in/out
-- CRE write 0-1 L L H L H X act 'z'
-- CRE read 0-1 L L L H H L act conf-out
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity mt45w8mw16b is -- Micron MT45W8MW16B CellularRAM model
port (
CLK : in slbit; -- clock for synchonous operation
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADV_N : in slbit; -- address valid (act.low)
CRE : in slbit; -- control register enable
MWAIT : out slbit; -- wait (for burst read/write)
ADDR : in slv23; -- address lines
DATA : inout slv16 -- data lines
);
end mt45w8mw16b;
architecture sim of mt45w8mw16b is
-- timing constants for -701 speed grade (70 ns; 104 MHz)
constant T_aa : time := 70 ns; -- address access time (max)
constant T_apa : time := 20 ns; -- page acess time (max)
constant T_oh : time := 5 ns; -- output hold from addr change (max)
constant T_oe : time := 20 ns; -- output enable to valid output (max)
constant T_ohz : time := 8 ns; -- output disable to high-z output (max)
constant T_olz : time := 3 ns; -- output enable to low-z output (min)
constant T_lz : time := 10 ns; -- chip enable to low-z output (min)
constant T_hz : time := 8 ns; -- chip disable to high-z output (max)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
constant bcr_f_mode : integer := 15; -- operating mode
constant bcr_f_ilat : integer := 14; -- initial latency
subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
constant bcr_f_wp : integer := 10; -- wait polarity
constant bcr_f_wc : integer := 8; -- wait configuration
subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
constant bcr_f_bw : integer := 3; -- burst wrap
subtype bcr_f_bl is integer range 2 downto 0; -- burst length
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
signal ADV : slbit := '0';
signal WE_L_EFF : slbit := '0';
signal WE_U_EFF : slbit := '0';
signal R_BCR_MODE : slbit := '1'; -- mode: def: async
signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
signal R_BCR_WP : slbit := '1'; -- wp: def: active high
signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
signal L_ADDR : slv23 := (others=>'0');
signal DOUT_VAL_EN : slbit := '0';
signal DOUT_VAL_AA : slbit := '0';
signal DOUT_VAL_PA : slbit := '0';
signal DOUT_VAL_OE : slbit := '0';
signal DOUT_LZ_CE : slbit := '0';
signal DOUT_LZ_OE : slbit := '0';
signal OEWE : slbit := '0';
signal DOUT : slv16 := (others=>'0');
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
ADV <= not ADV_N;
WE_L_EFF <= CE and WE and BE_L;
WE_U_EFF <= CE and WE and BE_U;
-- address valid logic, latch ADDR when ADV true
proc_adv: process (ADV, ADDR)
begin
if ADV = '1' then
L_ADDR <= ADDR;
end if;
end process proc_adv;
proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
variable addr_last : slv23 := (others=>'1');
begin
if (CE'event and CE='1') or
(BE_L'event and BE_L='1') or
(BE_U'event and BE_U='1') or
(WE'event and WE='0') or
(ADV'event and ADV='1') then
DOUT_VAL_EN <= '0', '1' after T_aa;
end if;
if L_ADDR'event then
DOUT_VAL_PA <= '0', '1' after T_apa;
if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
DOUT_VAL_AA <= '0', '1' after T_aa;
end if;
addr_last := L_ADDR;
end if;
if rising_edge(OE) then
DOUT_VAL_OE <= '0', '1' after T_oe;
end if;
end process proc_dout_val;
-- to simplify things assume that OE and (not WE) have same effect on output
-- drivers. The timing rules are very similar indeed...
OEWE <= OE and (not WE);
proc_dout_lz: process (CE, OEWE)
begin
if (CE'event) then
if CE = '1' then
DOUT_LZ_CE <= '1' after T_lz;
else
DOUT_LZ_CE <= '0' after T_hz;
end if;
end if;
if (OEwe'event) then
if OEWE = '1' then
DOUT_LZ_OE <= '1' after T_olz;
else
DOUT_LZ_OE <= '0' after T_ohz;
end if;
end if;
end process proc_dout_lz;
proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
-- end of write cycle
-- note: to_x01 used below to prevent that 'z' a written into mem.
if falling_edge(WE_L_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
end if;
if falling_edge(WE_U_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
end if;
DOUT <= ram(to_integer(unsigned(L_ADDR)));
end process proc_cram;
proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
DOUT_LZ_CE, DOUT_LZ_OE)
variable idout : slv16 := (others=>'0');
begin
idout := DOUT;
if DOUT_VAL_EN='0' or DOUT_VAL_AA='0' or
DOUT_VAL_PA='0' or DOUT_VAL_OE='0' then
idout := (others=>'X');
end if;
if DOUT_LZ_CE='0' or DOUT_LZ_OE='0' then
idout := (others=>'Z');
end if;
DATA <= idout;
end process proc_data;
proc_mwait: process (CE)
begin
-- WT driver (just a dummy)
if CE = '1' then
MWAIT <= '1';
else
MWAIT <= 'Z';
end if;
end process proc_mwait;
end sim;
|
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: mt45w8mw16b - sim
-- Description: Micron MT45W8MW16B CellularRAM model
-- Currently a much simplified model
-- - only async accesses
-- - ignores CLK and CRE
-- - simple model for response of DATA lines, but no
-- check for timing violations of control lines
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
-- 2010-06-03 298 1.3 add timing model again
-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
-- 2010-05-21 293 1.1 add BCR (only read of default so far)
-- 2010-05-16 291 1.0 Initial version (inspired by is61lv25616al)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Asynchronous Mode (BCR(15)=1)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Read L L L L H L L act data-out
-- Write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- CRE write L L L H L H X act 'z'
-- CRE read L L L L H H L act conf-out
--
-- Burst Mode (BCR(15)=0)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Async read L L L L H L L act data-out
-- Async write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- Initial burst read 0-1 L L X H L L act X
-- Initial burst write 0-1 L L H L L X act X
-- Burst continue 0-1 H L X X X X act data-in/out
-- CRE write 0-1 L L H L H X act 'z'
-- CRE read 0-1 L L L H H L act conf-out
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity mt45w8mw16b is -- Micron MT45W8MW16B CellularRAM model
port (
CLK : in slbit; -- clock for synchonous operation
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADV_N : in slbit; -- address valid (act.low)
CRE : in slbit; -- control register enable
MWAIT : out slbit; -- wait (for burst read/write)
ADDR : in slv23; -- address lines
DATA : inout slv16 -- data lines
);
end mt45w8mw16b;
architecture sim of mt45w8mw16b is
-- timing constants for -701 speed grade (70 ns; 104 MHz)
constant T_aa : time := 70 ns; -- address access time (max)
constant T_apa : time := 20 ns; -- page acess time (max)
constant T_oh : time := 5 ns; -- output hold from addr change (max)
constant T_oe : time := 20 ns; -- output enable to valid output (max)
constant T_ohz : time := 8 ns; -- output disable to high-z output (max)
constant T_olz : time := 3 ns; -- output enable to low-z output (min)
constant T_lz : time := 10 ns; -- chip enable to low-z output (min)
constant T_hz : time := 8 ns; -- chip disable to high-z output (max)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
constant bcr_f_mode : integer := 15; -- operating mode
constant bcr_f_ilat : integer := 14; -- initial latency
subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
constant bcr_f_wp : integer := 10; -- wait polarity
constant bcr_f_wc : integer := 8; -- wait configuration
subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
constant bcr_f_bw : integer := 3; -- burst wrap
subtype bcr_f_bl is integer range 2 downto 0; -- burst length
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
signal ADV : slbit := '0';
signal WE_L_EFF : slbit := '0';
signal WE_U_EFF : slbit := '0';
signal R_BCR_MODE : slbit := '1'; -- mode: def: async
signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
signal R_BCR_WP : slbit := '1'; -- wp: def: active high
signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
signal L_ADDR : slv23 := (others=>'0');
signal DOUT_VAL_EN : slbit := '0';
signal DOUT_VAL_AA : slbit := '0';
signal DOUT_VAL_PA : slbit := '0';
signal DOUT_VAL_OE : slbit := '0';
signal DOUT_LZ_CE : slbit := '0';
signal DOUT_LZ_OE : slbit := '0';
signal OEWE : slbit := '0';
signal DOUT : slv16 := (others=>'0');
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
ADV <= not ADV_N;
WE_L_EFF <= CE and WE and BE_L;
WE_U_EFF <= CE and WE and BE_U;
-- address valid logic, latch ADDR when ADV true
proc_adv: process (ADV, ADDR)
begin
if ADV = '1' then
L_ADDR <= ADDR;
end if;
end process proc_adv;
proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
variable addr_last : slv23 := (others=>'1');
begin
if (CE'event and CE='1') or
(BE_L'event and BE_L='1') or
(BE_U'event and BE_U='1') or
(WE'event and WE='0') or
(ADV'event and ADV='1') then
DOUT_VAL_EN <= '0', '1' after T_aa;
end if;
if L_ADDR'event then
DOUT_VAL_PA <= '0', '1' after T_apa;
if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
DOUT_VAL_AA <= '0', '1' after T_aa;
end if;
addr_last := L_ADDR;
end if;
if rising_edge(OE) then
DOUT_VAL_OE <= '0', '1' after T_oe;
end if;
end process proc_dout_val;
-- to simplify things assume that OE and (not WE) have same effect on output
-- drivers. The timing rules are very similar indeed...
OEWE <= OE and (not WE);
proc_dout_lz: process (CE, OEWE)
begin
if (CE'event) then
if CE = '1' then
DOUT_LZ_CE <= '1' after T_lz;
else
DOUT_LZ_CE <= '0' after T_hz;
end if;
end if;
if (OEwe'event) then
if OEWE = '1' then
DOUT_LZ_OE <= '1' after T_olz;
else
DOUT_LZ_OE <= '0' after T_ohz;
end if;
end if;
end process proc_dout_lz;
proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
-- end of write cycle
-- note: to_x01 used below to prevent that 'z' a written into mem.
if falling_edge(WE_L_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
end if;
if falling_edge(WE_U_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
end if;
DOUT <= ram(to_integer(unsigned(L_ADDR)));
end process proc_cram;
proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
DOUT_LZ_CE, DOUT_LZ_OE)
variable idout : slv16 := (others=>'0');
begin
idout := DOUT;
if DOUT_VAL_EN='0' or DOUT_VAL_AA='0' or
DOUT_VAL_PA='0' or DOUT_VAL_OE='0' then
idout := (others=>'X');
end if;
if DOUT_LZ_CE='0' or DOUT_LZ_OE='0' then
idout := (others=>'Z');
end if;
DATA <= idout;
end process proc_data;
proc_mwait: process (CE)
begin
-- WT driver (just a dummy)
if CE = '1' then
MWAIT <= '1';
else
MWAIT <= 'Z';
end if;
end process proc_mwait;
end sim;
|
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9AQ=
`protect end_protected
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file inst_mem.vhd when simulating
-- the core, inst_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY inst_mem IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(6 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END inst_mem;
ARCHITECTURE inst_mem_a OF inst_mem IS
-- synthesis translate_off
component wrapped_inst_mem
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(6 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_inst_mem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3e",
c_write_depth_b => 128,
c_write_depth_a => 128,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 7,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 7,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 128,
c_read_depth_a => 128,
c_byte_size => 9,
c_sim_collision_check => "NONE",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_inst_mem
port map (
clka => clka,
addra => addra,
douta => douta);
-- synthesis translate_on
END inst_mem_a;
|
--RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5_dec IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5_dec;
ARCHITECTURE rtl OF rc5_dec IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_post : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_post : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
-- RC5 state machine has five states: idle, round, post_round and ready
SIGNAL state : dec_StateType;
BEGIN
--B = ((B - S[2×i +1]) >>> A) xor A;
b<=b_reg - skey(CONV_INTEGER(i_cnt & '1')); --B - S[2*i+1]
WITH a_reg(4 DOWNTO 0) SELECT --B >>> A
b_rot<= b(0) & b(31 DOWNTO 01) WHEN "00001", --01
b(01 DOWNTO 0) & b(31 DOWNTO 02) WHEN "00010", --02
b(02 DOWNTO 0) & b(31 DOWNTO 03) WHEN "00011", --03
b(03 DOWNTO 0) & b(31 DOWNTO 04) WHEN "00100", --04
b(04 DOWNTO 0) & b(31 DOWNTO 05) WHEN "00101", --05
b(05 DOWNTO 0) & b(31 DOWNTO 06) WHEN "00110", --06
b(06 DOWNTO 0) & b(31 DOWNTO 07) WHEN "00111", --07
b(07 DOWNTO 0) & b(31 DOWNTO 08) WHEN "01000", --08
b(08 DOWNTO 0) & b(31 DOWNTO 09) WHEN "01001", --09
b(09 DOWNTO 0) & b(31 DOWNTO 10) WHEN "01010", --10
b(10 DOWNTO 0) & b(31 DOWNTO 11) WHEN "01011", --11
b(11 DOWNTO 0) & b(31 DOWNTO 12) WHEN "01100", --12
b(12 DOWNTO 0) & b(31 DOWNTO 13) WHEN "01101", --13
b(13 DOWNTO 0) & b(31 DOWNTO 14) WHEN "01110", --14
b(14 DOWNTO 0) & b(31 DOWNTO 15) WHEN "01111", --15
b(15 DOWNTO 0) & b(31 DOWNTO 16) WHEN "10000", --16
b(16 DOWNTO 0) & b(31 DOWNTO 17) WHEN "10001", --17
b(17 DOWNTO 0) & b(31 DOWNTO 18) WHEN "10010", --18
b(18 DOWNTO 0) & b(31 DOWNTO 19) WHEN "10011", --19
b(19 DOWNTO 0) & b(31 DOWNTO 20) WHEN "10100", --20
b(20 DOWNTO 0) & b(31 DOWNTO 21) WHEN "10101", --21
b(21 DOWNTO 0) & b(31 DOWNTO 22) WHEN "10110", --22
b(22 DOWNTO 0) & b(31 DOWNTO 23) WHEN "10111", --23
b(23 DOWNTO 0) & b(31 DOWNTO 24) WHEN "11000", --24
b(24 DOWNTO 0) & b(31 DOWNTO 25) WHEN "11001", --25
b(25 DOWNTO 0) & b(31 DOWNTO 26) WHEN "11010", --26
b(26 DOWNTO 0) & b(31 DOWNTO 27) WHEN "11011", --27
b(27 DOWNTO 0) & b(31 DOWNTO 28) WHEN "11100", --28
b(28 DOWNTO 0) & b(31 DOWNTO 29) WHEN "11101", --29
b(29 DOWNTO 0) & b(31 DOWNTO 30) WHEN "11110", --30
b(30 DOWNTO 0) & b(31) WHEN "11111", --31
b WHEN OTHERS; --32
ba_xor <= b_rot XOR a_reg; --B XOR A
--A = ((A - S[2×i]) >>> B) xor B;
a<=a_reg - skey(CONV_INTEGER(i_cnt & '0')); -- A - S[2*i]
WITH ba_xor(4 DOWNTO 0) SELECT --A >>> B
a_rot<= a(0) & a(31 DOWNTO 01) WHEN "00001", --01
a(01 DOWNTO 0) & a(31 DOWNTO 02) WHEN "00010", --02
a(02 DOWNTO 0) & a(31 DOWNTO 03) WHEN "00011", --03
a(03 DOWNTO 0) & a(31 DOWNTO 04) WHEN "00100", --04
a(04 DOWNTO 0) & a(31 DOWNTO 05) WHEN "00101", --05
a(05 DOWNTO 0) & a(31 DOWNTO 06) WHEN "00110", --06
a(06 DOWNTO 0) & a(31 DOWNTO 07) WHEN "00111", --07
a(07 DOWNTO 0) & a(31 DOWNTO 08) WHEN "01000", --08
a(08 DOWNTO 0) & a(31 DOWNTO 09) WHEN "01001", --09
a(09 DOWNTO 0) & a(31 DOWNTO 10) WHEN "01010", --10
a(10 DOWNTO 0) & a(31 DOWNTO 11) WHEN "01011", --11
a(11 DOWNTO 0) & a(31 DOWNTO 12) WHEN "01100", --12
a(12 DOWNTO 0) & a(31 DOWNTO 13) WHEN "01101", --13
a(13 DOWNTO 0) & a(31 DOWNTO 14) WHEN "01110", --14
a(14 DOWNTO 0) & a(31 DOWNTO 15) WHEN "01111", --15
a(15 DOWNTO 0) & a(31 DOWNTO 16) WHEN "10000", --16
a(16 DOWNTO 0) & a(31 DOWNTO 17) WHEN "10001", --17
a(17 DOWNTO 0) & a(31 DOWNTO 18) WHEN "10010", --18
a(18 DOWNTO 0) & a(31 DOWNTO 19) WHEN "10011", --19
a(19 DOWNTO 0) & a(31 DOWNTO 20) WHEN "10100", --20
a(20 DOWNTO 0) & a(31 DOWNTO 21) WHEN "10101", --21
a(21 DOWNTO 0) & a(31 DOWNTO 22) WHEN "10110", --22
a(22 DOWNTO 0) & a(31 DOWNTO 23) WHEN "10111", --23
a(23 DOWNTO 0) & a(31 DOWNTO 24) WHEN "11000", --24
a(24 DOWNTO 0) & a(31 DOWNTO 25) WHEN "11001", --25
a(25 DOWNTO 0) & a(31 DOWNTO 26) WHEN "11010", --26
a(26 DOWNTO 0) & a(31 DOWNTO 27) WHEN "11011", --27
a(27 DOWNTO 0) & a(31 DOWNTO 28) WHEN "11100", --28
a(28 DOWNTO 0) & a(31 DOWNTO 29) WHEN "11101", --29
a(29 DOWNTO 0) & a(31 DOWNTO 30) WHEN "11110", --30
a(30 DOWNTO 0) & a(31) WHEN "11111", --31
a WHEN OTHERS; --32
ab_xor <= a_rot XOR ba_xor; -- A XOR B
b_post<=b_reg - skey(1); --B = B - S[1]
a_post<=a_reg - skey(0); --A = A - S[0]
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_POST_ROUND) THEN
a_reg<=a_post;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=ab_xor;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_POST_ROUND) THEN
b_reg<=b_post;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=ba_xor;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(clk'EVENT AND clk='1') THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_ROUND_OP;
END IF;
WHEN ST_ROUND_OP=> IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY;
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_ROUND_OP;--can assume new keys and skip idle state
--state<=ST_IDLE; --If Input Changes then restart
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
i_cnt<="1100";
ELSIF(rising_edge(clk) AND state=ST_ROUND_OP) THEN
IF(i_cnt="0001") THEN
i_cnt<="1100";
ELSE
i_cnt<=i_cnt-'1';
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl; |
library IEEE;
use IEEE.std_logic_1164.ALL;
library WORK;
use WORK.cpu_pack.t_cpu_mem_word;
use WORK.cpu_pack.t_cpu_mask;
use WORK.cpu_pack.t_cpu_word;
package memory_pack is
-- synthesis translate_off
constant CPU_MEM_SIZE : natural := 256;
type t_cpu_memory is array(CPU_MEM_SIZE - 1 downto 0) of t_cpu_mem_word;
-- synthesis translate_on
component memory is
port(
clk : in std_logic;
rst : in std_logic;
wr_mask : in t_cpu_mask;
rd_mask : in t_cpu_mask;
instr_stall : out std_logic;
data_stall : out std_logic;
prog_addr : in t_cpu_word;
data_addr : in t_cpu_word;
prog_out : out t_cpu_word;
data_in : in t_cpu_word;
data_out : out t_cpu_word;
leds : out std_logic_vector(7 downto 0)
);
end component memory;
end package memory_pack;
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.ALL;
library WORK;
use WORK.memory_pack.ALL;
entity memory is
port(
clk : in std_logic;
rst : in std_logic;
wr_mask : in t_cpu_mask;
rd_mask : in t_cpu_mask;
instr_stall : out std_logic;
data_stall : out std_logic;
prog_addr : in t_cpu_word;
data_addr : in t_cpu_word;
prog_out : out t_cpu_word;
data_in : in t_cpu_word;
data_out : out t_cpu_word;
leds : out std_logic_vector(7 downto 0)
);
end entity memory;
-- synthesis translate_off
architecture simulation_memory of memory is
signal ram : t_cpu_memory;
begin
memory_access:
process( clk )
variable i_addr : natural := 0;
variable d_addr : natural := 0;
begin
if falling_edge( clk ) then
i_addr := to_integer(unsigned(prog_addr(7 downto 0)));
d_addr := to_integer(unsigned(data_addr(7 downto 0)));
-- ########### READ INSTRUCTION ###################
prog_out <= ram(i_addr) & ram(i_addr + 1) & ram(i_addr + 2) & ram(i_addr + 3);
-- ########### READ DATA ##########################
case rd_mask is
when CPU_MASK_READ8 => data_out <= ram(d_addr) & ram(d_addr) & ram(d_addr) & ram(d_addr);
when CPU_MASK_READ16 => data_out <= ram(d_addr) & ram(d_addr + 1) & ram(d_addr) & ram(d_addr + 1);
when CPU_MASK_READ32 => data_out <= ram(d_addr) & ram(d_addr + 1) & ram(d_addr + 2) & ram(d_addr + 3);
when others => data_out <= (others => '0');
end case;
-- ########### WRITE DATA #########################
case wr_mask is
when CPU_MASK_WRITE8 => ram(d_addr) <= data_in(31 downto 24);
when CPU_MASK_WRITE16 => ram(d_addr) <= data_in(31 downto 24);
ram(d_addr + 1) <= data_in(23 downto 16);
when CPU_MASK_WRITE32 => ram(d_addr) <= data_in(31 downto 24);
ram(d_addr + 1) <= data_in(23 downto 16);
ram(d_addr + 2) <= data_in(15 downto 8);
ram(d_addr + 3) <= data_in( 7 downto 0);
when others =>
end case;
leds <= ram(132);
end if;
end process;
instr_stall <= '0';
data_stall <= '0';
end simulation_memory;
-- synthesis translate_on
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.ALL;
library WORK;
use WORK.memory_pack.ALL;
architecture fpga_memory of memory is
--
-- address types
--
subtype t_addr is std_logic_vector(7 downto 0);
type t_word_addr is
record
byte_0 : unsigned(7 downto 0);
byte_1 : unsigned(7 downto 0);
byte_2 : unsigned(7 downto 0);
byte_3 : unsigned(7 downto 0);
end record;
--
-- extract address type
--
alias cpu_i_addr : t_addr is prog_addr(7 downto 0);
alias cpu_d_addr : t_addr is data_addr(7 downto 0);
--
-- instruction and data addresses
--
signal i_addr : t_word_addr;
signal d_addr : t_word_addr;
--
-- ########## STATE MACHINE ################
--
type t_state is (sONE, sTWO, sTHREE, sFOUR);
signal i_state, n_i_state : t_state;
signal d_state, n_d_state : t_state;
--
-- data access mask
--
signal mask : std_logic_vector(3 downto 0);
--
-- ram component
--
component ram is
port(
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(7 downto 0);
dpra : in std_logic_vector(7 downto 0);
di : in std_logic_vector(7 downto 0);
spo : out std_logic_vector(7 downto 0);
dpo : out std_logic_vector(7 downto 0);
leds : out std_logic_vector(7 downto 0)
);
end component ram;
--
-- RAM unit interface
--
signal ram_i_addr : std_logic_vector(7 downto 0);
signal ram_d_addr : std_logic_vector(7 downto 0);
signal i_data : std_logic_vector(7 downto 0);
signal d_data_in : std_logic_vector(7 downto 0);
signal d_data_out : std_logic_vector(7 downto 0);
--
-- store read bytes
--
signal i_reg : std_logic_vector(23 downto 0);
signal d_reg : std_logic_vector(23 downto 0);
--
-- detect instruction address change
--
signal prev_addr : t_addr;
signal new_addr : std_logic;
begin
-- _ _ _ ____ ___ ____ _ _ ____ ___ _ ____ _ _
-- | |\ | [__ | |__/ | | | | | | | |\ |
-- | | \| ___] | | \ |__| |___ | | |__| | \|
--
-- for instruction address changes read new instruction
--
process( i_state, new_addr, i_addr )
begin
-- default values
instr_stall <= '1';
ram_i_addr <= std_logic_vector(i_addr.byte_3);
n_i_state <= sONE;
-- state logic
case i_state is
when sONE =>
if new_addr = '1' then
ram_i_addr <= std_logic_vector(i_addr.byte_0);
n_i_state <= sTWO;
else
instr_stall <= '0';
end if;
when sTWO => n_i_state <= sTHREE; ram_i_addr <= std_logic_vector(i_addr.byte_1);
when sTHREE => n_i_state <= sFOUR; ram_i_addr <= std_logic_vector(i_addr.byte_2);
when sFOUR => n_i_state <= sONE; ram_i_addr <= std_logic_vector(i_addr.byte_3); instr_stall <= '0';
end case;
end process;
-- ___ ____ ___ ____
-- | \ |__| | |__|
-- |__/ | | | | |
--
-- check mask
--
process( d_state, mask, wr_mask, d_addr )
begin
-- default values
ram_d_addr <= std_logic_vector(d_addr.byte_0);
data_stall <= '0';
n_d_state <= sONE;
case d_state is
when sONE =>
if mask(1) = '1' then
data_stall <= '1';
n_d_state <= sTWO;
end if;
when sTWO =>
ram_d_addr <= std_logic_vector(d_addr.byte_1);
if mask(2) = '1' then
data_stall <= '1';
n_d_state <= sTHREE;
end if;
when sTHREE =>
ram_d_addr <= std_logic_vector(d_addr.byte_2);
data_stall <= '1';
n_d_state <= sFOUR;
when sFOUR =>
ram_d_addr <= std_logic_vector(d_addr.byte_3);
end case;
end process;
-- ____ ___ ___ ____ ____ ____ ____ ____ ____
-- |__| | \ | \ |__/ |___ [__ [__ |___ [__
-- | | |__/ |__/ | \ |___ ___] ___] |___ ___]
--
-- instruction addresses for whole word
--
i_addr.byte_0 <= unsigned(cpu_i_addr);
i_addr.byte_1 <= unsigned(cpu_i_addr) + 1;
i_addr.byte_2 <= unsigned(cpu_i_addr) + 2;
i_addr.byte_3 <= unsigned(cpu_i_addr) + 3;
--
-- data addresses for whole word
--
d_addr.byte_0 <= unsigned(cpu_d_addr);
d_addr.byte_1 <= unsigned(cpu_d_addr) + 1;
d_addr.byte_2 <= unsigned(cpu_d_addr) + 2;
d_addr.byte_3 <= unsigned(cpu_d_addr) + 3;
--
-- new instruction address detection
--
new_addr <= '1' when prev_addr /= prog_addr(7 downto 0) else '0';
-- ___ ____ ___ ____ _ _ _ ____ ____ ___ ____
-- | \ |__| | |__| | | | | | |__/ | \ [__
-- |__/ | | | | | |_|_| |__| | \ |__/ ___]
--
-- data mask
--
mask <= wr_mask or rd_mask;
--
-- data to write
--
with d_state select
d_data_in <= data_in(23 downto 16) when sTWO,
data_in(15 downto 8) when sTHREE,
data_in( 7 downto 0) when sFOUR,
data_in(31 downto 24) when others;
--
-- read data
--
prog_out <= i_reg & i_data;
data_out <= d_reg & d_data_out;
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
i_state <= sONE;
d_state <= sONE;
i_reg <= (others => '0');
d_reg <= (others => '0');
prev_addr <= (others => '1');
else
--
-- state variables
--
i_state <= n_i_state;
d_state <= n_d_state;
--
-- read instruction bytes
--
case i_state is
when sONE => i_reg <= i_data & i_data & i_data;
when sTWO => i_reg <= i_reg(23 downto 16) & i_data & i_data;
when sTHREE => i_reg <= i_reg(23 downto 8) & i_data;
when sFOUR => i_reg <= i_reg;
end case;
--
-- read data bytes
--
case d_state is
when sONE => d_reg <= d_data_out & d_data_out & d_data_out;
when sTWO => d_reg <= d_reg(23 downto 16) & d_data_out & d_data_out;
when sTHREE => d_reg <= d_reg(23 downto 8) & d_data_out;
when sFOUR => d_reg <= d_reg;
end case;
--
-- store previous address
--
if i_state = sONE then
prev_addr <= prog_addr(7 downto 0);
end if;
end if;
end if;
end process;
-- ____ ____ _ _
-- |__/ |__| |\/|
-- | \ | | | |
ram_unit: ram
PORT MAP(
clk => clk,
we => wr_mask(0),
a => ram_d_addr, dpra => ram_i_addr,
di => d_data_in,
spo => d_data_out, dpo => i_data,
leds => leds
);
end fpga_memory;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:26:06 03/11/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/FETCH/FETCH_TOPLEVEL_tbd.vhd
-- Project Name: FETCH
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: FETCH_TOPLEVEL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY FETCH_TOPLEVEL_tbd IS
END FETCH_TOPLEVEL_tbd;
ARCHITECTURE behavior OF FETCH_TOPLEVEL_tbd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FETCH_TOPLEVEL
PORT(
CLK : IN std_logic;
DATAIN : IN std_logic_vector(15 downto 0);
INST_OUT : OUT std_logic_vector(15 downto 0);
WE : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal DATAIN : std_logic_vector(15 downto 0) := (others => '0');
signal WE : std_logic := '0';
--Outputs
signal INST_OUT : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FETCH_TOPLEVEL PORT MAP (
CLK => CLK,
DATAIN => DATAIN,
INST_OUT => INST_OUT,
WE => WE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
-- hold reset state for 100 ns.
wait for 20 ns;
report "Start Debug Test Bench!" severity Note;
WE <= '1';
DATAIN <= x"0FC0";
wait for CLK_period;
WE <= '1';
DATAIN <= x"1671";
wait for CLK_period;
WE <= '1';
DATAIN <= x"467A";
wait for CLK_period;
WE <= '1';
DATAIN <= x"0682";
wait for CLK_period;
wait for 100 ns;
wait;
end process;
END;
|
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